mirror of
git://nv-tegra.nvidia.com/linux-nvgpu.git
synced 2025-12-23 09:57:08 +03:00
fba96fdc09
Delete the struct nvgpu_engine_info as it's essentially identical to
struct nvgpu_device. Duplicating data structures is not ideal as it's
terribly confusing what does what.
Update all uses of nvgpu_engine_info to use struct nvgpu_device. This
is often a fairly straight forward replacement. Couple of places though
where things got interesting:
- The enum_type that engine_info uses is defined in engines.h and
has a bit of SW abstraction - in particular the GRCE type. The only
place this seemed to be actually relevant (the IOCTL providing device
info to userspace) the GRCE engines can be worked out by comparing
runlist ID.
- Addition of masks based on intr_id and reset_id; those can be
computed easily enough using BIT32() but this is an area that
could be improved on.
This reaches into a lot of extraneous code that traverses the fifo
active engines list and dramtically simplifies this. Now, instead of
having to go through a table of engine IDs that point to the list of
all host engines, the active engine list is just a list of pointers to
valid engines. It's now trivial to do a for-all-active-engines type
loop. This could even be turned into a generic macro or otherwise
abstracted in the future.
JIRA NVGPU-5421
Change-Id: I3a810deb55a7dd8c09836fd2dae85d3e28eb23cf
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2319895
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
296 lines
7.3 KiB
C
296 lines
7.3 KiB
C
/*
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* GP10B master
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*
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* Copyright (c) 2014-2020, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#include <nvgpu/gk20a.h>
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#include <nvgpu/io.h>
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#include <nvgpu/mc.h>
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#include <nvgpu/engines.h>
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#include <nvgpu/device.h>
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#include <nvgpu/power_features/pg.h>
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#include "mc_gp10b.h"
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#include <nvgpu/hw/gp10b/hw_mc_gp10b.h>
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void mc_gp10b_intr_mask(struct gk20a *g)
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{
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nvgpu_writel(g, mc_intr_en_clear_r(NVGPU_MC_INTR_STALLING),
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U32_MAX);
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g->mc.intr_mask_restore[NVGPU_MC_INTR_STALLING] = 0;
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nvgpu_writel(g, mc_intr_en_clear_r(NVGPU_MC_INTR_NONSTALLING),
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U32_MAX);
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g->mc.intr_mask_restore[NVGPU_MC_INTR_NONSTALLING] = 0;
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}
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static u32 mc_gp10b_intr_pending_f(struct gk20a *g, u32 unit)
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{
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u32 intr_pending_f = 0;
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switch (unit) {
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case MC_INTR_UNIT_BUS:
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intr_pending_f = mc_intr_pbus_pending_f();
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break;
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case MC_INTR_UNIT_PRIV_RING:
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intr_pending_f = mc_intr_priv_ring_pending_f();
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break;
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case MC_INTR_UNIT_FIFO:
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intr_pending_f = mc_intr_pfifo_pending_f();
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break;
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case MC_INTR_UNIT_LTC:
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intr_pending_f = mc_intr_ltc_pending_f();
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break;
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case MC_INTR_UNIT_GR:
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intr_pending_f = nvgpu_gr_engine_interrupt_mask(g);
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break;
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case MC_INTR_UNIT_PMU:
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intr_pending_f = mc_intr_pmu_pending_f();
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break;
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case MC_INTR_UNIT_HUB:
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intr_pending_f = mc_intr_replayable_fault_pending_f();
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break;
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case MC_INTR_UNIT_CE:
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intr_pending_f = nvgpu_ce_engine_interrupt_mask(g);
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break;
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default:
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nvgpu_err(g, "Invalid MC interrupt unit specified !!!");
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break;
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}
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return intr_pending_f;
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}
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static void mc_gp10b_isr_stall_primary(struct gk20a *g, u32 mc_intr_0)
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{
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if ((mc_intr_0 & mc_intr_priv_ring_pending_f()) != 0U) {
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g->ops.priv_ring.isr(g);
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}
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}
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void mc_gp10b_isr_stall_secondary_1(struct gk20a *g, u32 mc_intr_0)
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{
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if ((mc_intr_0 & mc_intr_ltc_pending_f()) != 0U) {
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g->ops.mc.ltc_isr(g);
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}
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#ifdef CONFIG_NVGPU_DGPU
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if ((g->ops.mc.is_intr_nvlink_pending != NULL) &&
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g->ops.mc.is_intr_nvlink_pending(g, mc_intr_0)) {
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g->ops.nvlink.intr.isr(g);
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}
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if ((mc_intr_0 & mc_intr_pfb_pending_f()) != 0U &&
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(g->ops.mc.fbpa_isr != NULL)) {
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g->ops.mc.fbpa_isr(g);
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}
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#endif
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}
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void mc_gp10b_isr_stall_secondary_0(struct gk20a *g, u32 mc_intr_0)
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{
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if ((g->ops.mc.is_intr_hub_pending != NULL) &&
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g->ops.mc.is_intr_hub_pending(g, mc_intr_0)) {
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g->ops.fb.intr.isr(g, 0U);
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}
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if ((mc_intr_0 & mc_intr_pfifo_pending_f()) != 0U) {
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g->ops.fifo.intr_0_isr(g);
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}
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if ((mc_intr_0 & mc_intr_pmu_pending_f()) != 0U) {
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g->ops.pmu.pmu_isr(g);
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}
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}
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void mc_gp10b_isr_stall_engine(struct gk20a *g,
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const struct nvgpu_device *dev)
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{
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int err;
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/* GR Engine */
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if (nvgpu_device_is_graphics(g, dev)) {
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err = nvgpu_pg_elpg_protected_call(g,
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g->ops.gr.intr.stall_isr(g));
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if (err != 0) {
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nvgpu_err(g, "Unable to handle gr interrupt");
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}
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}
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/* CE Engine */
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if (nvgpu_device_is_ce(g, dev) &&
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(g->ops.ce.isr_stall != NULL)) {
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g->ops.ce.isr_stall(g, dev->inst_id, dev->pri_base);
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}
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}
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void mc_gp10b_intr_stall_unit_config(struct gk20a *g, u32 unit, bool enable)
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{
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u32 unit_pending_f = mc_gp10b_intr_pending_f(g, unit);
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u32 reg = 0U;
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if (enable) {
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reg = mc_intr_en_set_r(NVGPU_MC_INTR_STALLING);
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g->mc.intr_mask_restore[NVGPU_MC_INTR_STALLING] |=
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unit_pending_f;
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nvgpu_writel(g, reg, unit_pending_f);
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} else {
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reg = mc_intr_en_clear_r(NVGPU_MC_INTR_STALLING);
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g->mc.intr_mask_restore[NVGPU_MC_INTR_STALLING] &=
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~unit_pending_f;
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nvgpu_writel(g, reg, unit_pending_f);
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}
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}
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void mc_gp10b_intr_nonstall_unit_config(struct gk20a *g, u32 unit, bool enable)
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{
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u32 unit_pending_f = mc_gp10b_intr_pending_f(g, unit);
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u32 reg = 0U;
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if (enable) {
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reg = mc_intr_en_set_r(NVGPU_MC_INTR_NONSTALLING);
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g->mc.intr_mask_restore[NVGPU_MC_INTR_NONSTALLING] |=
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unit_pending_f;
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nvgpu_writel(g, reg, unit_pending_f);
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} else {
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reg = mc_intr_en_clear_r(NVGPU_MC_INTR_NONSTALLING);
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g->mc.intr_mask_restore[NVGPU_MC_INTR_NONSTALLING] &=
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~unit_pending_f;
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nvgpu_writel(g, reg, unit_pending_f);
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}
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}
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void mc_gp10b_isr_stall(struct gk20a *g)
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{
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u32 mc_intr_0;
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u32 i;
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const struct nvgpu_device *dev;
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mc_intr_0 = nvgpu_readl(g, mc_intr_r(NVGPU_MC_INTR_STALLING));
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nvgpu_log(g, gpu_dbg_intr, "stall intr 0x%08x", mc_intr_0);
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mc_gp10b_isr_stall_primary(g, mc_intr_0);
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for (i = 0U; i < g->fifo.num_engines; i++) {
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dev = g->fifo.active_engines[i];
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if ((mc_intr_0 & BIT32(dev->intr_id)) == 0U) {
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continue;
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}
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mc_gp10b_isr_stall_engine(g, dev);
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}
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mc_gp10b_isr_stall_secondary_0(g, mc_intr_0);
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mc_gp10b_isr_stall_secondary_1(g, mc_intr_0);
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nvgpu_log(g, gpu_dbg_intr, "stall intr done 0x%08x", mc_intr_0);
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}
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u32 mc_gp10b_intr_stall(struct gk20a *g)
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{
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return nvgpu_readl(g, mc_intr_r(NVGPU_MC_INTR_STALLING));
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}
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void mc_gp10b_intr_stall_pause(struct gk20a *g)
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{
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nvgpu_writel(g, mc_intr_en_clear_r(NVGPU_MC_INTR_STALLING), U32_MAX);
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}
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void mc_gp10b_intr_stall_resume(struct gk20a *g)
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{
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nvgpu_writel(g, mc_intr_en_set_r(NVGPU_MC_INTR_STALLING),
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g->mc.intr_mask_restore[NVGPU_MC_INTR_STALLING]);
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}
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u32 mc_gp10b_intr_nonstall(struct gk20a *g)
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{
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return nvgpu_readl(g, mc_intr_r(NVGPU_MC_INTR_NONSTALLING));
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}
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void mc_gp10b_intr_nonstall_pause(struct gk20a *g)
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{
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nvgpu_writel(g, mc_intr_en_clear_r(NVGPU_MC_INTR_NONSTALLING),
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U32_MAX);
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}
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void mc_gp10b_intr_nonstall_resume(struct gk20a *g)
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{
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nvgpu_writel(g, mc_intr_en_set_r(NVGPU_MC_INTR_NONSTALLING),
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g->mc.intr_mask_restore[NVGPU_MC_INTR_NONSTALLING]);
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}
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bool mc_gp10b_is_intr1_pending(struct gk20a *g,
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enum nvgpu_unit unit, u32 mc_intr_1)
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{
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u32 mask;
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bool is_pending;
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switch (unit) {
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case NVGPU_UNIT_FIFO:
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mask = mc_intr_pfifo_pending_f();
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break;
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default:
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mask = 0U;
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break;
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}
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if (mask == 0U) {
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nvgpu_err(g, "unknown unit %d", unit);
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is_pending = false;
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} else {
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is_pending = ((mc_intr_1 & mask) != 0U);
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}
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return is_pending;
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}
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#ifdef CONFIG_NVGPU_NON_FUSA
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void mc_gp10b_log_pending_intrs(struct gk20a *g)
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{
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u32 i, intr;
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for (i = 0U; i < MAX_MC_INTR_REGS; i++) {
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intr = nvgpu_readl(g, mc_intr_r(i));
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if (intr == 0U) {
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continue;
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}
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nvgpu_info(g, "Pending intr%d=0x%08x", i, intr);
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}
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}
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#endif
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void mc_gp10b_ltc_isr(struct gk20a *g)
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{
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u32 mc_intr;
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u32 ltc;
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mc_intr = nvgpu_readl(g, mc_intr_ltc_r());
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nvgpu_log(g, gpu_dbg_intr, "mc_ltc_intr: %08x", mc_intr);
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for (ltc = 0U; ltc < nvgpu_ltc_get_ltc_count(g); ltc++) {
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if ((mc_intr & BIT32(ltc)) == 0U) {
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continue;
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}
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g->ops.ltc.intr.isr(g, ltc);
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}
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}
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