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fba516ffae
PMU IRQs were not enabled assuming entire functionality for LS PMU. Debugging early init issues of PMU falcon ECC errors triggered during nvgpu power-on will be cumbersome if interrupts are not enabled early. FMEA analysis of the nvgpu init path also requires this interrupt be enabled earlier. Hence, Enable the PMU ECC IRQ early during nvgpu_finalize_poweron. pmu_enable_irq is updated to enable interrupts differently for safety and non-safety. PMU interrupts disabling is moved out of nvgpu_pmu_destroy to nvgpu_prepare_poweroff. Prepared new wrapper API nvgpu_pmu_enable_irq. PMU ECC init and isr mutex init is moved to the beginning of nvgpu_pmu_early_init as for safety, ls pmu code path is disabled. Fixed the pmu_early_init dependent and mc interrupt related unit tests. Update the doxygen for changed functions. JIRA NVGPU-4439 Change-Id: I1a1e792d2ad2cc7a926c8c1456d4d0d6d1f14d1a Signed-off-by: Sagar Kamble <skamble@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/2251732 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
75 lines
2.2 KiB
C
75 lines
2.2 KiB
C
/*
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* Copyright (c) 2011-2019, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#include <nvgpu/pmu/debug.h>
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#include <nvgpu/gk20a.h>
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#include <nvgpu/io.h>
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#include <nvgpu/hw/gk20a/hw_pwr_gk20a.h>
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#include "pmu_gk20a.h"
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void gk20a_pmu_isr(struct gk20a *g)
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{
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struct nvgpu_pmu *pmu = g->pmu;
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u32 intr, mask;
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nvgpu_log_fn(g, " ");
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nvgpu_mutex_acquire(&pmu->isr_mutex);
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if (!pmu->isr_enabled) {
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nvgpu_mutex_release(&pmu->isr_mutex);
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return;
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}
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mask = nvgpu_readl(g, pwr_falcon_irqmask_r());
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mask &= nvgpu_readl(g, pwr_falcon_irqdest_r());
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intr = nvgpu_readl(g, pwr_falcon_irqstat_r());
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nvgpu_pmu_dbg(g, "received falcon interrupt: 0x%08x", intr);
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intr = nvgpu_readl(g, pwr_falcon_irqstat_r()) & mask;
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if (intr == 0U) {
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nvgpu_mutex_release(&pmu->isr_mutex);
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return;
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}
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if (g->ops.pmu.handle_ext_irq != NULL) {
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g->ops.pmu.handle_ext_irq(g, intr);
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}
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nvgpu_writel(g, pwr_falcon_irqsclr_r(), intr);
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#ifdef CONFIG_NVGPU_LS_PMU
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if (nvgpu_pmu_get_fw_state(g, pmu) == PMU_FW_STATE_OFF) {
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nvgpu_mutex_release(&pmu->isr_mutex);
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return;
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}
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gk20a_pmu_handle_interrupts(g, intr);
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#endif
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nvgpu_mutex_release(&pmu->isr_mutex);
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}
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