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0cd90a1167
Move sec2_gp106.c and sec2_tu104.c to hal/sec2 as per new unit separation requirements. JIRA NVGPU-2024 JIRA NVGPU-2025 Change-Id: I511e1832aa63d4792729491428de0159decf2371 Signed-off-by: Sagar Kamble <skamble@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/2085755 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
54 lines
2.3 KiB
C
54 lines
2.3 KiB
C
/*
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* Copyright (c) 2018-2019, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#ifndef NVGPU_SEC2_TU104_H
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#define NVGPU_SEC2_TU104_H
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struct gk20a;
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struct nvgpu_sec2;
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int tu104_sec2_reset(struct gk20a *g);
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int tu104_sec2_flcn_copy_to_emem(struct gk20a *g,
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u32 dst, u8 *src, u32 size, u8 port);
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int tu104_sec2_flcn_copy_from_emem(struct gk20a *g,
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u32 src, u8 *dst, u32 size, u8 port);
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void tu104_sec2_flcn_setup_boot_config(struct gk20a *g);
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int tu104_sec2_queue_head(struct gk20a *g, u32 queue_id, u32 queue_index,
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u32 *head, bool set);
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int tu104_sec2_queue_tail(struct gk20a *g, u32 queue_id, u32 queue_index,
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u32 *tail, bool set);
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void tu104_sec2_msgq_tail(struct gk20a *g, struct nvgpu_sec2 *sec2,
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u32 *tail, bool set);
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bool tu104_sec2_is_interrupted(struct nvgpu_sec2 *sec2);
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u32 tu104_sec2_get_intr(struct gk20a *g);
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bool tu104_sec2_msg_intr_received(struct gk20a *g);
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void tu104_sec2_set_msg_intr(struct gk20a *g);
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void tu104_sec2_clr_intr(struct gk20a *g, u32 intr);
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void tu104_sec2_process_intr(struct gk20a *g, struct nvgpu_sec2 *sec2);
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void tu104_sec2_enable_irq(struct nvgpu_sec2 *sec2, bool enable);
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void tu104_start_sec2_secure(struct gk20a *g);
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u32 tu104_sec2_falcon_base_addr(void);
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#endif /* NVGPU_SEC2_TU104_H */
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