mirror of
git://nv-tegra.nvidia.com/linux-nvgpu.git
synced 2025-12-22 17:36:20 +03:00
e02ea5456b
The ctxsw'ed registers have been moved to a separate list starting from nvgpu_next chip onwards. Hence, update gr_tu104_get_offset_in_gpccs_segment function to account for ctxsw'ed registers in nvgpu_next. Introduce functions: nvgpu_netlist_get_gpc_ctxsw_regs_count to compute the number of ctxsw'ed gpc registers. Bug 2916121 Change-Id: I69fcd8df883af62999d0fa8d1f9a398f8f5d7454 Signed-off-by: Antony Clince Alex <aalex@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2394684 Tested-by: mobile promotions <svcmobile_promotions@nvidia.com> Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com> Reviewed-by: automaticguardword <automaticguardword@nvidia.com> Reviewed-by: Alex Waterman <alexw@nvidia.com> Reviewed-by: Seema Khowala <seemaj@nvidia.com> Reviewed-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com> Reviewed-by: Vaibhav Kachore <vkachore@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> GVS: Gerrit_Virtual_Submit
415 lines
14 KiB
C
415 lines
14 KiB
C
/*
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* Copyright (c) 2011-2020, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#ifndef NVGPU_NETLIST_H
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#define NVGPU_NETLIST_H
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/**
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* @file
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*
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* common.netlist unit interface
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*/
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#include <nvgpu/types.h>
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struct gk20a;
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/**
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* Description of netlist Address-Value(av) structure.
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*/
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struct netlist_av {
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/** U32 address in av structure. */
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u32 addr;
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/** U32 value in av structure. */
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u32 value;
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};
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/**
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* Description of netlist Address-Value64(av64) structure.
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*/
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struct netlist_av64 {
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/** U32 address in av64 structure. */
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u32 addr;
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/** Lower u32 value in av64 structure. */
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u32 value_lo;
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/** Higher u32 value in av64 structure. */
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u32 value_hi;
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};
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/**
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* Description of netlist Address-Index-Value(aiv) structure.
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*/
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struct netlist_aiv {
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/** U32 address in aiv structure. */
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u32 addr;
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/** U32 index in aiv structure. */
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u32 index;
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/** U32 value in aiv structure. */
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u32 value;
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};
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/**
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* Description of netlist aiv list bundle structure.
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*/
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struct netlist_aiv_list {
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/** Pointer to netlist aiv bundle. */
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struct netlist_aiv *l;
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/** Number of netlist aiv bundles. */
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u32 count;
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};
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/**
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* Description of netlist av list bundle structure.
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*/
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struct netlist_av_list {
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/** Pointer to netlist av bundle. */
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struct netlist_av *l;
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/** Number of netlist av bundles. */
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u32 count;
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};
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/**
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* Description of netlist av64 list bundle structure.
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*/
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struct netlist_av64_list {
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/** Pointer to netlist av64 bundle. */
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struct netlist_av64 *l;
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/** Number of netlist av64 bundles. */
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u32 count;
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};
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/**
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* Description of netlist u32 list bundle structure.
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*/
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struct netlist_u32_list {
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/** Pointer to u32 value. */
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u32 *l;
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/** Number of u32 elements in the list. */
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u32 count;
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};
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/**
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* @brief Allocates memory for netlist bundles and populates
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* ctxsw region info from ctxsw firmware file.
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*
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* @param g [in] Pointer to GPU driver struct.
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*
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* This function allocates memory for netlist unit variables and bundles.
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* Opens netlist ctxsw firmware file based on firmware definition and loads
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* different bundles into appropriate netlist regions structures.
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*
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* @return 0 in case of success, < 0 in case of failure.
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* @retval -ENOMEM if memory allocation for netlist variables or bundle fails.
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* @retval -ENOENT if it fails to find required netlist firmware file.
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* @retval -ENOENT if netlist s/w version mismatches with h/w config.
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*/
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int nvgpu_netlist_init_ctx_vars(struct gk20a *g);
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/**
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* @brief Frees memory allocated for netlist bundles.
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*
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* @param g [in] Pointer to GPU driver struct.
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*
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* This function frees all allocated memory for netlist bundles and
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* netlist vars.
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*/
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void nvgpu_netlist_deinit_ctx_vars(struct gk20a *g);
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/**
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* @brief Allocates memory for netlist av list bundle.
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*
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* @param g [in] Pointer to GPU driver struct.
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* @param avl [in] Pointer to #netlist_av_list struct.
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*
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* This function allocates memory for netlist av list bundles for the
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* requested size from #netlist_av_list count.
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*
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* @return Pointer to #netlist_av.
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* @retval NULL if memory allocation for #netlist_av bundles fails.
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*/
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struct netlist_av *nvgpu_netlist_alloc_av_list(struct gk20a *g,
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struct netlist_av_list *avl);
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/**
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* @brief Allocates memory for netlist av64 list bundle.
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*
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* @param g [in] Pointer to GPU driver struct.
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* @param av64l [in] Pointer to #netlist_av64_list struct.
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*
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* This function allocates memory for netlist av64 list bundles for the
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* requested size from #netlist_av64_list count.
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*
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* @return Pointer to #netlist_av64 struct.
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* @retval NULL if memory allocation for #netlist_av64 bundles fails.
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*/
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struct netlist_av64 *nvgpu_netlist_alloc_av64_list(struct gk20a *g,
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struct netlist_av64_list *av64l);
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/**
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* @brief Allocates memory for netlist aiv list bundle.
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*
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* @param g [in] Pointer to GPU driver struct.
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* @param aivl [in] Pointer to #netlist_avi_list struct.
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*
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* This function allocates memory for netlist aiv list bundles for the
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* requested size from #netlist_aiv_list count.
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*
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* @return Pointer to #netlist_aiv struct.
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* @retval NULL if memory allocation for #netlist_aiv bundles fails.
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*/
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struct netlist_aiv *nvgpu_netlist_alloc_aiv_list(struct gk20a *g,
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struct netlist_aiv_list *aivl);
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/**
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* @brief Allocates memory for netlist u32 list bundle.
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*
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* @param g [in] Pointer to GPU driver struct.
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* @param u32l [in] Pointer to #netlist_u32_list struct.
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*
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* This function allocates memory for netlist u32 list bundles for the
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* requested size from #netlist_u32_list count.
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*
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* @return Pointer to u32 list.
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* @retval NULL if memory allocation for u32 list bundles fails.
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*/
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u32 *nvgpu_netlist_alloc_u32_list(struct gk20a *g,
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struct netlist_u32_list *u32l);
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/**
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* @brief Get s/w non-context #netlist_av_list bundles from firmware.
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*
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* @param g [in] Pointer to GPU driver struct.
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*
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* This function returns non-context #netlist_av_list bundles from
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* netlist firmware. SW needs to program these bundles to h/w as part
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* of golden context creation.
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*
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* @return Pointer to #netlist_av_list struct.
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*/
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struct netlist_av_list *nvgpu_netlist_get_sw_non_ctx_load_av_list(
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struct gk20a *g);
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/**
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* @brief Get s/w context #netlist_aiv_list bundles from firmware.
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*
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* @param g [in] Pointer to GPU driver struct.
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*
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* This function returns s/w context #netlist_aiv_list bundles from
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* netlist firmware. SW needs to program these bundles to h/w as part
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* of golden context creation.
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*
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* @return Pointer to #netlist_aiv_list struct.
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*/
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struct netlist_aiv_list *nvgpu_netlist_get_sw_ctx_load_aiv_list(
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struct gk20a *g);
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/**
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* @brief Get s/w method init #netlist_av_list bundles from firmware.
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*
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* @param g [in] Pointer to GPU driver struct.
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*
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* This function returns s/w method init #netlist_av_list bundles from
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* netlist firmware. SW needs to program these bundles to h/w as part
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* of golden context creation.
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*
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* @return Pointer to #netlist_av_list struct.
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*/
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struct netlist_av_list *nvgpu_netlist_get_sw_method_init_av_list(
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struct gk20a *g);
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/**
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* @brief Get s/w init #netlist_av_list bundles from firmware.
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*
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* @param g [in] Pointer to GPU driver struct.
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*
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* This function returns s/w bundles #netlist_av_list bundles from
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* netlist firmware. SW needs to program these bundles to h/w as part
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* of golden context creation.
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*
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* @return Pointer to #netlist_av_list struct.
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*/
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struct netlist_av_list *nvgpu_netlist_get_sw_bundle_init_av_list(
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struct gk20a *g);
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/**
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* @brief Get s/w veid init #netlist_av_list bundles from firmware.
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*
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* @param g [in] Pointer to GPU driver struct.
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*
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* This function returns s/w veid #netlist_av_list bundles from
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* netlist firmware. SW needs to program these bundles to h/w as part
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* of golden context creation.
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*
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* @return Pointer to #netlist_av_list struct.
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*/
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struct netlist_av_list *nvgpu_netlist_get_sw_veid_bundle_init_av_list(
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struct gk20a *g);
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/**
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* @brief Get s/w u64 init #netlist_av64_list bundles from firmware.
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*
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* @param g [in] Pointer to GPU driver struct.
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*
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* This function returns s/w u64 #netlist_av64_list bundles from
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* netlist firmware. SW needs to program these bundles to h/w as part
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* of golden context creation.
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*
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* @return Pointer to #netlist_av64_list struct.
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*/
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struct netlist_av64_list *nvgpu_netlist_get_sw_bundle64_init_av64_list(
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struct gk20a *g);
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/**
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* @brief Get FECS imem ucode size from firmware.
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*
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* @param g [in] Pointer to GPU driver struct.
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*
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* This function returns h/w fecs imem ucode size from netlist firmware.
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* SW needs this information for falcon FECS ucode programming.
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*
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* @return FECS imem ucode size.
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*/
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u32 nvgpu_netlist_get_fecs_inst_count(struct gk20a *g);
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/**
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* @brief Get FECS dmem ucode size from firmware.
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*
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* @param g [in] Pointer to GPU driver struct.
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*
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* This function returns h/w fecs dmem ucode size from netlist firmware.
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* SW needs this information for falcon FECS ucode programming.
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*
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* @return FECS dmem ucode size.
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*/
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u32 nvgpu_netlist_get_fecs_data_count(struct gk20a *g);
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/**
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* @brief Get GPCCS imem ucode size from firmware.
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*
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* @param g [in] Pointer to GPU driver struct.
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*
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* This function returns h/w gpccs imem ucode size from netlist firmware.
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* SW needs this information for falcon GPCCS ucode programming.
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*
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* @return GPCCS imem ucode size.
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*/
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u32 nvgpu_netlist_get_gpccs_inst_count(struct gk20a *g);
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/**
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* @brief Get GPCCS dmem ucode size from firmware.
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*
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* @param g [in] Pointer to GPU driver struct.
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*
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* This function returns h/w gpccs dmem ucode size from netlist firmware.
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* SW needs this information for falcon GPCCS ucode programming.
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*
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* @return GPCCS dmem ucode size.
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*/
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u32 nvgpu_netlist_get_gpccs_data_count(struct gk20a *g);
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/**
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* @brief Get pointer to FECS imem ucode from firmware.
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*
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* @param g [in] Pointer to GPU driver struct.
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*
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* This function returns pointer to fecs imem ucode from netlist firmware.
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* SW will use this information for falcon FECS imem ucode programming.
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*
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* @return U32 pointer to FECS imem ucode.
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*/
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u32 *nvgpu_netlist_get_fecs_inst_list(struct gk20a *g);
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/**
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* @brief Get pointer to FECS dmem ucode from firmware.
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*
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* @param g [in] Pointer to GPU driver struct.
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*
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* This function returns pointer to fecs dmem ucode from netlist firmware.
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* SW will use this information for falcon FECS ucode programming.
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*
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* @return U32 pointer to FECS dmem ucode.
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*/
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u32 *nvgpu_netlist_get_fecs_data_list(struct gk20a *g);
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/**
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* @brief Get pointer Io GPCCS imem ucode from firmware.
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*
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* @param g [in] Pointer to GPU driver struct.
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*
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* This function returns pointer to gpccs imem ucode from netlist firmware.
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* SW will use this information for falcon GPCCS ucode programming.
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*
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* @return U32 pointer to GPCCS imem ucode.
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*/
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u32 *nvgpu_netlist_get_gpccs_inst_list(struct gk20a *g);
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/**
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* @brief Get pointer to GPCCS dmem ucode from firmware.
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*
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* @param g [in] Pointer to GPU driver struct.
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*
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* This function returns pointer to gpccs dmem ucode from netlist firmware.
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* SW will use this information for falcon GPCCS ucode programming.
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*
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* @return U32 pointer to GPCCS dmem ucode.
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*/
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u32 *nvgpu_netlist_get_gpccs_data_list(struct gk20a *g);
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/** @cond DOXYGEN_SHOULD_SKIP_THIS */
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#if defined(CONFIG_NVGPU_NON_FUSA) && defined(CONFIG_NVGPU_NEXT)
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#include <nvgpu/nvgpu_next_netlist.h>
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#endif
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#ifdef CONFIG_NVGPU_DEBUGGER
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struct netlist_aiv_list *nvgpu_netlist_get_sys_ctxsw_regs(struct gk20a *g);
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struct netlist_aiv_list *nvgpu_netlist_get_gpc_ctxsw_regs(struct gk20a *g);
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struct netlist_aiv_list *nvgpu_netlist_get_tpc_ctxsw_regs(struct gk20a *g);
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#ifdef CONFIG_NVGPU_GRAPHICS
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struct netlist_aiv_list *nvgpu_netlist_get_zcull_gpc_ctxsw_regs(
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struct gk20a *g);
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#endif
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struct netlist_aiv_list *nvgpu_netlist_get_ppc_ctxsw_regs(struct gk20a *g);
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struct netlist_aiv_list *nvgpu_netlist_get_pm_sys_ctxsw_regs(struct gk20a *g);
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struct netlist_aiv_list *nvgpu_netlist_get_pm_gpc_ctxsw_regs(struct gk20a *g);
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struct netlist_aiv_list *nvgpu_netlist_get_pm_tpc_ctxsw_regs(struct gk20a *g);
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struct netlist_aiv_list *nvgpu_netlist_get_pm_ppc_ctxsw_regs(struct gk20a *g);
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struct netlist_aiv_list *nvgpu_netlist_get_perf_sys_ctxsw_regs(struct gk20a *g);
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struct netlist_aiv_list *nvgpu_netlist_get_perf_gpc_ctxsw_regs(struct gk20a *g);
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struct netlist_aiv_list *nvgpu_netlist_get_fbp_ctxsw_regs(struct gk20a *g);
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struct netlist_aiv_list *nvgpu_netlist_get_fbp_router_ctxsw_regs(
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struct gk20a *g);
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struct netlist_aiv_list *nvgpu_netlist_get_gpc_router_ctxsw_regs(
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struct gk20a *g);
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struct netlist_aiv_list *nvgpu_netlist_get_pm_ltc_ctxsw_regs(struct gk20a *g);
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struct netlist_aiv_list *nvgpu_netlist_get_pm_fbpa_ctxsw_regs(struct gk20a *g);
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struct netlist_aiv_list *nvgpu_netlist_get_perf_sys_router_ctxsw_regs(
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struct gk20a *g);
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struct netlist_aiv_list *nvgpu_netlist_get_perf_pma_ctxsw_regs(struct gk20a *g);
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struct netlist_aiv_list *nvgpu_netlist_get_pm_rop_ctxsw_regs(struct gk20a *g);
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struct netlist_aiv_list *nvgpu_netlist_get_pm_ucgpc_ctxsw_regs(struct gk20a *g);
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struct netlist_aiv_list *nvgpu_netlist_get_etpc_ctxsw_regs(struct gk20a *g);
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struct netlist_aiv_list *nvgpu_netlist_get_pm_cau_ctxsw_regs(struct gk20a *g);
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struct netlist_aiv_list *nvgpu_netlist_get_perf_sys_control_ctxsw_regs(
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struct gk20a *g);
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struct netlist_aiv_list *nvgpu_netlist_get_perf_fbp_control_ctxsw_regs(
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struct gk20a *g);
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struct netlist_aiv_list *nvgpu_netlist_get_perf_gpc_control_ctxsw_regs(
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struct gk20a *g);
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struct netlist_aiv_list *nvgpu_netlist_get_perf_pma_control_ctxsw_regs(
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struct gk20a *g);
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u32 nvgpu_netlist_get_ppc_ctxsw_regs_count(struct gk20a *g);
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u32 nvgpu_netlist_get_gpc_ctxsw_regs_count(struct gk20a *g);
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u32 nvgpu_netlist_get_tpc_ctxsw_regs_count(struct gk20a *g);
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u32 nvgpu_netlist_get_etpc_ctxsw_regs_count(struct gk20a *g);
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#endif /* CONFIG_NVGPU_DEBUGGER */
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#ifdef CONFIG_NVGPU_NON_FUSA
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void nvgpu_netlist_set_fecs_inst_count(struct gk20a *g, u32 count);
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void nvgpu_netlist_set_fecs_data_count(struct gk20a *g, u32 count);
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void nvgpu_netlist_set_gpccs_inst_count(struct gk20a *g, u32 count);
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void nvgpu_netlist_set_gpccs_data_count(struct gk20a *g, u32 count);
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struct netlist_u32_list *nvgpu_netlist_get_fecs_inst(struct gk20a *g);
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struct netlist_u32_list *nvgpu_netlist_get_fecs_data(struct gk20a *g);
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struct netlist_u32_list *nvgpu_netlist_get_gpccs_inst(struct gk20a *g);
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struct netlist_u32_list *nvgpu_netlist_get_gpccs_data(struct gk20a *g);
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void nvgpu_netlist_vars_set_dynamic(struct gk20a *g, bool set);
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void nvgpu_netlist_vars_set_buffer_size(struct gk20a *g, u32 size);
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void nvgpu_netlist_vars_set_regs_base_index(struct gk20a *g, u32 index);
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#endif
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/** @endcond DOXYGEN_SHOULD_SKIP_THIS */
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#endif /* NVGPU_NETLIST_H */
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