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git://nv-tegra.nvidia.com/linux-nvgpu.git
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e8f2e3d514
Add nvgpu-next sim function prototypes. This resolves qnx and userspace build errors. JIRA NVGPU-5363 Change-Id: I7b20917ec73b2ca3a1514872620266bb7a54097c Signed-off-by: Vedashree Vidwans <vvidwans@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2369657 Reviewed-by: automaticguardword <automaticguardword@nvidia.com> Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Alex Waterman <alexw@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> GVS: Gerrit_Virtual_Submit Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
102 lines
3.3 KiB
C
102 lines
3.3 KiB
C
/*
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* Copyright (c) 2018-2020, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#ifndef NVGPU_SIM_H
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#define NVGPU_SIM_H
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#ifdef CONFIG_NVGPU_SIM
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#include <nvgpu/nvgpu_mem.h>
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#include <nvgpu/gk20a.h>
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/** @cond DOXYGEN_SHOULD_SKIP_THIS */
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#if defined(CONFIG_NVGPU_NON_FUSA) && defined(CONFIG_NVGPU_NEXT)
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#include <nvgpu/nvgpu_next_sim.h>
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#endif
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/** @endcond DOXYGEN_SHOULD_SKIP_THIS */
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struct sim_nvgpu {
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struct gk20a *g;
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u32 send_ring_put;
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u32 recv_ring_get;
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u32 recv_ring_put;
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u32 sequence_base;
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struct nvgpu_mem send_bfr;
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struct nvgpu_mem recv_bfr;
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struct nvgpu_mem msg_bfr;
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int (*sim_init_late)(struct gk20a *g);
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void (*remove_support)(struct gk20a *g);
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void (*esc_readl)(
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struct gk20a *g, const char *path, u32 index, u32 *data);
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};
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#ifdef __KERNEL__
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#include "linux/sim.h"
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#include "linux/sim_pci.h"
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#elif defined(__NVGPU_POSIX__)
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/* Nothing for POSIX-nvgpu. */
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#else
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#include <nvgpu_rmos/include/sim.h>
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#include <nvgpu_rmos/include/sim_pci.h>
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#endif
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int nvgpu_init_sim_support(struct gk20a *g);
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int nvgpu_init_sim_support_pci(struct gk20a *g);
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int nvgpu_alloc_sim_buffer(struct gk20a *g, struct nvgpu_mem *mem);
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void nvgpu_free_sim_buffer(struct gk20a *g, struct nvgpu_mem *mem);
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void nvgpu_free_sim_support(struct gk20a *g);
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void nvgpu_remove_sim_support(struct gk20a *g);
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void sim_writel(struct sim_nvgpu *sim, u32 r, u32 v);
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u32 sim_readl(struct sim_nvgpu *sim, u32 r);
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int nvgpu_init_sim_netlist_ctx_vars(struct gk20a *g);
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int issue_rpc_and_wait(struct gk20a *g);
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void sim_write_hdr(struct gk20a *g, u32 func, u32 size);
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static inline u32 sim_escape_read_hdr_size(void)
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{
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return 12U; /*TBD: fix NV_VGPU_SIM_ESCAPE_READ_HEADER*/
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}
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static inline u32 sim_msg_header_size(void)
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{
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return 24U;/*TBD: fix the header to gt this from NV_VGPU_MSG_HEADER*/
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}
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static inline u32 *sim_msg_bfr(struct gk20a *g, u32 byte_offset)
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{
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u8 *cpu_va;
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cpu_va = (u8 *)g->sim->msg_bfr.cpu_va;
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return (u32 *)(cpu_va + byte_offset);
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}
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static inline u32 *sim_msg_hdr(struct gk20a *g, u32 byte_offset)
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{
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return sim_msg_bfr(g, byte_offset); /*starts at 0*/
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}
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static inline u32 *sim_msg_param(struct gk20a *g, u32 byte_offset)
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{
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/*starts after msg header/cmn*/
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return sim_msg_bfr(g, byte_offset + sim_msg_header_size());
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}
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#endif
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#endif /* NVGPU_SIM_H */
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