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a73ca0b70e
Split GR ECC initialization into GPC/TPC and FECS ECC init as FECS ECC errors during acr_construct_execute need to be reported and handled hence FECS ECC counters are required to be initialized before acr_construct_execute. GPC/TPC ECC counters are dependent on the GR config that will be initialized only after acr_construct_execute. nvgpu_gr_intr_init_support is moved to nvgpu_gr_prepare_sw. FECS ECC interrupt is enabled by default hence interrupt is not enabled through gr_fecs_host_int_enable_r in nvgpu_gr_prepare_sw. JIRA NVGPU-4439 Change-Id: Ifc9912f0578015a6ba1e9d38765c42633632b15f Signed-off-by: Sagar Kamble <skamble@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/2261987 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com> Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com> Reviewed-by: Vinod Gopalakrishnakurup <vinodg@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Vaibhav Kachore <vkachore@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
63 lines
2.6 KiB
C
63 lines
2.6 KiB
C
/*
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* Copyright (c) 2018-2019, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#ifndef NVGPU_ECC_GV11B_H
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#define NVGPU_ECC_GV11B_H
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#include <nvgpu/nvgpu_err.h>
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#include <nvgpu/types.h>
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struct gk20a;
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struct nvgpu_hw_err_inject_info;
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struct nvgpu_hw_err_inject_info_desc;
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void gv11b_ecc_detect_enabled_units(struct gk20a *g);
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int gv11b_gr_gpc_tpc_ecc_init(struct gk20a *g);
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int gv11b_gr_fecs_ecc_init(struct gk20a *g);
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#ifdef CONFIG_NVGPU_INJECT_HWERR
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void gv11b_gr_intr_inject_fecs_ecc_error(struct gk20a *g,
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struct nvgpu_hw_err_inject_info *err, u32 error_info);
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struct nvgpu_hw_err_inject_info_desc *
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gv11b_gr_intr_get_fecs_err_desc(struct gk20a *g);
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void gv11b_gr_intr_inject_gpccs_ecc_error(struct gk20a *g,
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struct nvgpu_hw_err_inject_info *err, u32 error_info);
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struct nvgpu_hw_err_inject_info_desc *
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gv11b_gr_intr_get_gpccs_err_desc(struct gk20a *g);
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void gv11b_gr_intr_inject_sm_ecc_error(struct gk20a *g,
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struct nvgpu_hw_err_inject_info *err, u32 error_info);
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struct nvgpu_hw_err_inject_info_desc *
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gv11b_gr_intr_get_sm_err_desc(struct gk20a *g);
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void gv11b_gr_intr_inject_mmu_ecc_error(struct gk20a *g,
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struct nvgpu_hw_err_inject_info *err, u32 error_info);
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struct nvgpu_hw_err_inject_info_desc *
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gv11b_gr_intr_get_mmu_err_desc(struct gk20a *g);
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void gv11b_gr_intr_inject_gcc_ecc_error(struct gk20a *g,
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struct nvgpu_hw_err_inject_info *err, u32 error_info);
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struct nvgpu_hw_err_inject_info_desc *
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gv11b_gr_intr_get_gcc_err_desc(struct gk20a *g);
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#endif /* CONFIG_NVGPU_INJECT_HWERR */
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#endif /* NVGPU_ECC_GV11B_H */
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