mirror of
git://nv-tegra.nvidia.com/linux-nvgpu.git
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26de95b55f
Initialize the perfmon counters #3 masks to be same values as ELPG.
Hardware boots up with value NV_PPWR_PMU_IDLE_MASK_1(3) (0x10aa4c) = 0x1030,
but ELPG NV_PPWR_PMU_IDLE_MASK_1_SUPP(0) (0x10a9f4) boots up with 0.
Bug 2833620
Change-Id: I026ab236fd42f4f9c61e2f9b1f2b7988711a2927
Signed-off-by: David Ung <davidu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2335299
(cherry picked from commit bbef4c6927)
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2422675
Reviewed-by: automaticguardword <automaticguardword@nvidia.com>
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
74 lines
2.9 KiB
C
74 lines
2.9 KiB
C
/*
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* Copyright (c) 2016-2019, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#ifndef PMU_GV11B_H
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#define PMU_GV11B_H
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#include <nvgpu/nvgpu_err.h>
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#include <nvgpu/types.h>
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struct gk20a;
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struct nvgpu_hw_err_inject_info;
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struct nvgpu_hw_err_inject_info_desc;
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bool gv11b_pmu_is_debug_mode_en(struct gk20a *g);
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void gv11b_pmu_flcn_setup_boot_config(struct gk20a *g);
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void gv11b_setup_apertures(struct gk20a *g);
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bool gv11b_pmu_is_engine_in_reset(struct gk20a *g);
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void gv11b_pmu_engine_reset(struct gk20a *g, bool do_reset);
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u32 gv11b_pmu_falcon_base_addr(void);
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bool gv11b_is_pmu_supported(struct gk20a *g);
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void gv11b_pmu_handle_ext_irq(struct gk20a *g, u32 intr0);
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#ifdef CONFIG_NVGPU_LS_PMU
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int gv11b_pmu_bootstrap(struct gk20a *g, struct nvgpu_pmu *pmu,
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u32 args_offset);
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void gv11b_pmu_init_perfmon_counter(struct gk20a *g);
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void gv11b_pmu_setup_elpg(struct gk20a *g);
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void gv11b_secured_pmu_start(struct gk20a *g);
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void gv11b_write_dmatrfbase(struct gk20a *g, u32 addr);
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u32 gv11b_pmu_queue_head_r(u32 i);
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u32 gv11b_pmu_queue_head__size_1_v(void);
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u32 gv11b_pmu_queue_tail_r(u32 i);
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u32 gv11b_pmu_queue_tail__size_1_v(void);
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u32 gv11b_pmu_mutex__size_1_v(void);
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#endif
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void gv11b_clear_pmu_bar0_host_err_status(struct gk20a *g);
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int gv11b_pmu_bar0_error_status(struct gk20a *g, u32 *bar0_status,
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u32 *etype);
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bool gv11b_pmu_validate_mem_integrity(struct gk20a *g);
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#ifdef CONFIG_NVGPU_INJECT_HWERR
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struct nvgpu_hw_err_inject_info_desc * gv11b_pmu_intr_get_err_desc(struct gk20a *g);
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void gv11b_pmu_inject_ecc_error(struct gk20a *g,
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struct nvgpu_hw_err_inject_info *err, u32 error_info);
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#endif /* CONFIG_NVGPU_INJECT_HWERR */
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int gv11b_pmu_ecc_init(struct gk20a *g);
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void gv11b_pmu_ecc_free(struct gk20a *g);
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u32 gv11b_pmu_get_irqdest(struct gk20a *g);
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void gv11b_pmu_enable_irq(struct nvgpu_pmu *pmu, bool enable);
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#endif /* PMU_GV11B_H */
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