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ca39cacdaf
Rule 21.1 states that #define and #undef shall not be used on a reserved identifier or reserved macro name. Rule 21.2 states that a reserved identifier or macro name shall not be declared. Fix violations of the above rules in utils unit. Jira NVGPU-3878 Change-Id: I4302c498f5fb533699d2e53b9d1ffe1e7ccf53f2 Signed-off-by: ajesh <akv@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/2194035 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Alex Waterman <alexw@nvidia.com> Reviewed-by: Vaibhav Kachore <vkachore@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
73 lines
2.4 KiB
C
73 lines
2.4 KiB
C
/*
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* Copyright (c) 2016-2019, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#ifndef NVGPU_XVE_GP106_H
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#define NVGPU_XVE_GP106_H
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#ifdef CONFIG_NVGPU_DGPU
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#include <nvgpu/log2.h>
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#include <nvgpu/types.h>
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#include <nvgpu/gk20a.h>
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/*
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* Best guess for a reasonable timeout.
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*/
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#define GPU_XVE_TIMEOUT_MS 500
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/*
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* Debugging for the speed change.
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*/
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enum xv_speed_change_steps {
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PRE_CHANGE = 0,
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DISABLE_ASPM,
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DL_SAFE_MODE,
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CHECK_LINK,
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LINK_SETTINGS,
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EXEC_CHANGE,
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EXEC_VERIF,
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CLEANUP
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};
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#define xv_dbg(g, fmt, args...) \
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nvgpu_log(g, gpu_dbg_xv, fmt, ##args)
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#define xv_sc_dbg(g, step, fmt, args...) \
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xv_dbg(g, "[%d] %15s | " fmt, step, nvgpu_stringify(step), ##args)
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void xve_xve_writel_gp106(struct gk20a *g, u32 reg, u32 val);
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u32 xve_xve_readl_gp106(struct gk20a *g, u32 reg);
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void xve_reset_gpu_gp106(struct gk20a *g);
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int xve_get_speed_gp106(struct gk20a *g, u32 *xve_link_speed);
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void xve_disable_aspm_gp106(struct gk20a *g);
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int xve_set_speed_gp106(struct gk20a *g, u32 next_link_speed);
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void xve_available_speeds_gp106(struct gk20a *g, u32 *speed_mask);
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u32 xve_get_link_control_status(struct gk20a *g);
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#if defined(CONFIG_PCI_MSI)
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void xve_rearm_msi_gp106(struct gk20a *g);
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#endif
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void xve_enable_shadow_rom_gp106(struct gk20a *g);
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void xve_disable_shadow_rom_gp106(struct gk20a *g);
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#endif
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#endif /* NVGPU_XVE_GP106_H */
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