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ea3d83d98b
Bug 1450792 Change-Id: I09f7c727a773178613fe555eb025ac324da0008e Signed-off-by: Kevin Huang <kevinh@nvidia.com> Reviewed-on: http://git-master/r/381128 Reviewed-on: http://git-master/r/396373 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Arto Merilainen <amerilainen@nvidia.com> Reviewed-by: Bo Yan <byan@nvidia.com>
48 lines
1.3 KiB
C
48 lines
1.3 KiB
C
/*
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* GM20B Fifo
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*
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* Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*/
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#include "gk20a/gk20a.h"
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#include "fifo_gm20b.h"
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#include "hw_ccsr_gm20b.h"
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#include "hw_ram_gm20b.h"
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static void channel_gm20b_bind(struct channel_gk20a *ch_gk20a)
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{
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struct gk20a *g = ch_gk20a->g;
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u32 inst_ptr = ch_gk20a->inst_block.cpu_pa
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>> ram_in_base_shift_v();
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gk20a_dbg_info("bind channel %d inst ptr 0x%08x",
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ch_gk20a->hw_chid, inst_ptr);
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ch_gk20a->bound = true;
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gk20a_writel(g, ccsr_channel_inst_r(ch_gk20a->hw_chid),
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ccsr_channel_inst_ptr_f(inst_ptr) |
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ccsr_channel_inst_target_vid_mem_f() |
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ccsr_channel_inst_bind_true_f());
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gk20a_writel(g, ccsr_channel_r(ch_gk20a->hw_chid),
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(gk20a_readl(g, ccsr_channel_r(ch_gk20a->hw_chid)) &
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~ccsr_channel_enable_set_f(~0)) |
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ccsr_channel_enable_set_true_f());
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}
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void gm20b_init_fifo(struct gpu_ops *gops)
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{
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gops->fifo.bind_channel = channel_gm20b_bind;
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}
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