Files
linux-nvgpu/drivers/gpu/nvgpu/tu104/fifo_tu104.h
Debarshi Dutta eaab8ad1f2 gpu: nvgpu: move some fifo based HAL ops to hal.channel unit
a) free_channel_ctx_header is used to free the channel's underlying subctx
and belongs to the hal.channel unit instead of fifo. Moved the same and
renamed the HAL ops to free_ctx_header. The function
gv11b_free_subctx_header is moved to channel_gv11b.* files and also
renamed to gv11b_channel_free_subctx_header.

b) ch_abort_clean_up is moved to hal.channel unit

c) channel_resume and channel_suspend are used to resume and suspend all
the serviceable channels. This belongs to hal.channel unit and are
moved from the hal.fifo unit.

The HAL ops channel_resume and channel_suspend are renamed to
resume_all_serviceable_ch and suspend_all_serviceable_ch respectively.

gk20a_channel_resume and gk20a_channel_suspend are also renamed to
nvgpu_channel_resume_all_serviceable_ch and
nvgpu_channel_suspend_all_serviceable_ch respectively.

d) set_error_notifier HAL ops belongs to hal.channel and is moved
accordingly.

Jira NVGPU-2978

Change-Id: Icb52245cacba3004e2fd32519029a1acff60c23c
Signed-off-by: Debarshi Dutta <ddutta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2083593
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2019-04-09 01:48:16 -07:00

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C

/*
* Copyright (c) 2018-2019, NVIDIA CORPORATION. All rights reserved.
*
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* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
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* and/or sell copies of the Software, and to permit persons to whom the
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* The above copyright notice and this permission notice shall be included in
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* DEALINGS IN THE SOFTWARE.
*/
#ifndef NVGPU_FIFO_TU104_H
#define NVGPU_FIFO_TU104_H
#include <nvgpu/types.h>
struct gk20a;
struct channel_gk20a;
int tu104_init_fifo_setup_hw(struct gk20a *g);
void tu104_ring_channel_doorbell(struct channel_gk20a *ch);
u64 tu104_fifo_usermode_base(struct gk20a *g);
u32 tu104_fifo_doorbell_token(struct channel_gk20a *c);
int tu104_init_pdb_cache_war(struct gk20a *g);
void tu104_deinit_pdb_cache_war(struct gk20a *g);
#endif /* NVGPU_FIFO_TU104_H */