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Fifo scheduling APIs require the HW reg mask accessor fifo_sched_disable_runlist_m() to be used even from high-level logic. Restructure the APIs to take in an explicit bitmap of runlist IDs and translate the bitmap to units of fifo_sched_disable_runlist_m() (which happens to be an identical bitmap) only just before accessing hardware. Jira NVGPU-1309 Change-Id: I5d6ce5b719ef467172c07c8d7589d83942365025 Signed-off-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1960225 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>