Terje Bergstrom ec62c649b5 gpu: nvgpu: Idle GR before calling PMU ZBC save ...

On gk20a when PMU is updating ZBC colors it is reading them from L2.
But L2 has one port, and ZBC reads can race with other transactions.
Idle graphics before sending PMU the ZBC_UPDATE request.

Also makes pmu_save_zbc a HAL, because PMU ucode has changes to bypass
this problem on some chips.

Bug 1746047

Change-Id: Id8fcd6850af7ef1d8f0a6aafa0fe6b4f88b5f2d9
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/1129017

2016-04-26 09:46:04 -07:00

..

nvgpu

gpu: nvgpu: Idle GR before calling PMU ZBC save

2016-04-26 09:46:04 -07:00