mirror of
git://nv-tegra.nvidia.com/linux-nvgpu.git
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154 lines
4.3 KiB
C
154 lines
4.3 KiB
C
/*
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* Copyright (c) 2019-2021, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#ifndef ACR_BLOB_CONSTRUCT_H
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#define ACR_BLOB_CONSTRUCT_H
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#include <nvgpu/falcon.h>
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#include <nvgpu/flcnif_cmn.h>
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#include <nvgpu/pmu.h>
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#include "nvgpu_acr_interface.h"
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#define UCODE_NB_MAX_DATE_LENGTH 64U
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struct ls_falcon_ucode_desc {
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u32 descriptor_size;
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u32 image_size;
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u32 tools_version;
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u32 app_version;
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char date[UCODE_NB_MAX_DATE_LENGTH];
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u32 bootloader_start_offset;
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u32 bootloader_size;
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u32 bootloader_imem_offset;
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u32 bootloader_entry_point;
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u32 app_start_offset;
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u32 app_size;
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u32 app_imem_offset;
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u32 app_imem_entry;
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u32 app_dmem_offset;
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u32 app_resident_code_offset;
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u32 app_resident_code_size;
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u32 app_resident_data_offset;
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u32 app_resident_data_size;
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u32 nb_imem_overlays;
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u32 nb_dmem_overlays;
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struct {u32 start; u32 size; } load_ovl[UCODE_NB_MAX_DATE_LENGTH];
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u32 compressed;
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};
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struct ls_falcon_ucode_desc_v1 {
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u32 descriptor_size;
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u32 image_size;
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u32 tools_version;
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u32 app_version;
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char date[UCODE_NB_MAX_DATE_LENGTH];
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u32 secure_bootloader;
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u32 bootloader_start_offset;
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u32 bootloader_size;
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u32 bootloader_imem_offset;
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u32 bootloader_entry_point;
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u32 app_start_offset;
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u32 app_size;
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u32 app_imem_offset;
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u32 app_imem_entry;
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u32 app_dmem_offset;
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u32 app_resident_code_offset;
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u32 app_resident_code_size;
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u32 app_resident_data_offset;
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u32 app_resident_data_size;
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u32 nb_imem_overlays;
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u32 nb_dmem_overlays;
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struct {u32 start; u32 size; } load_ovl[64];
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u32 compressed;
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};
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struct flcn_ucode_img {
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u32 *data;
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struct ls_falcon_ucode_desc *desc;
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u32 data_size;
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struct lsf_ucode_desc *lsf_desc;
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bool is_next_core_img;
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#if defined(CONFIG_NVGPU_NEXT)
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struct falcon_next_core_ucode_desc *ndesc;
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#endif
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};
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struct lsfm_managed_ucode_img {
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struct lsfm_managed_ucode_img *next;
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struct lsf_wpr_header wpr_header;
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struct lsf_lsb_header lsb_header;
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struct flcn_bl_dmem_desc bl_gen_desc;
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u32 bl_gen_desc_size;
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u32 full_ucode_size;
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struct flcn_ucode_img ucode_img;
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};
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#ifdef CONFIG_NVGPU_DGPU
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/*
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* LSF shared SubWpr Header
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*
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* use_case_id - Shared SubWpr use case ID (updated by nvgpu)
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* start_addr - start address of subWpr (updated by nvgpu)
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* size_4K - size of subWpr in 4K (updated by nvgpu)
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*/
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struct lsf_shared_sub_wpr_header {
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u32 use_case_id;
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u32 start_addr;
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u32 size_4K;
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};
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/*
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* LSFM SUB WPRs struct
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* pnext : Next entry in the list, NULL if last
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* sub_wpr_header : SubWpr Header struct
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*/
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struct lsfm_sub_wpr {
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struct lsfm_sub_wpr *pnext;
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struct lsf_shared_sub_wpr_header sub_wpr_header;
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};
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#endif
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struct ls_flcn_mgr {
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u16 managed_flcn_cnt;
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u32 wpr_size;
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struct lsfm_managed_ucode_img *ucode_img_list;
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#ifdef CONFIG_NVGPU_DGPU
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u16 managed_sub_wpr_count;
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struct lsfm_sub_wpr *psub_wpr_list;
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#endif
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};
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int nvgpu_acr_prepare_ucode_blob(struct gk20a *g);
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#ifdef CONFIG_NVGPU_LS_PMU
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int nvgpu_acr_lsf_pmu_ucode_details(struct gk20a *g, void *lsf_ucode_img);
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#if defined(CONFIG_NVGPU_NEXT)
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s32 nvgpu_acr_lsf_pmu_ncore_ucode_details(struct gk20a *g, void *lsf_ucode_img);
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#endif
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#endif
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int nvgpu_acr_lsf_fecs_ucode_details(struct gk20a *g, void *lsf_ucode_img);
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int nvgpu_acr_lsf_gpccs_ucode_details(struct gk20a *g, void *lsf_ucode_img);
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#ifdef CONFIG_NVGPU_DGPU
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int nvgpu_acr_lsf_sec2_ucode_details(struct gk20a *g, void *lsf_ucode_img);
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#endif
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#endif /* ACR_BLOB_CONSTRUCT_H */
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