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a0a941e571
MISRA Rule-17.7 requires the return value of all functions to be used. Fix is either to use the return value or change the function to return void. This patch changes pmu_elpg_statistics to return a status based on the result of nvgpu_falcon_copy_from_dmem and propagate it upstream. JIRA NVGPU-677 Change-Id: I7c85bf2b1b9f5a8eb09040229a1112c84713eb70 Signed-off-by: Nicolas Benech <nbenech@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/2008825 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
42 lines
1.7 KiB
C
42 lines
1.7 KiB
C
/*
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* GP10B PMU
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*
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* Copyright (c) 2015-2019, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#ifndef NVGPU_PMU_GP10B_H
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#define NVGPU_PMU_GP10B_H
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struct gk20a;
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bool gp10b_is_lazy_bootstrap(u32 falcon_id);
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bool gp10b_is_priv_load(u32 falcon_id);
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bool gp10b_is_pmu_supported(struct gk20a *g);
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int gp10b_pmu_elpg_statistics(struct gk20a *g, u32 pg_engine_id,
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struct pmu_pg_stats_data *pg_stat_data);
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int gp10b_pmu_setup_elpg(struct gk20a *g);
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int gp10b_load_falcon_ucode(struct gk20a *g, u32 falconidmask);
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int gp10b_pg_gr_init(struct gk20a *g, u32 pg_engine_id);
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void gp10b_write_dmatrfbase(struct gk20a *g, u32 addr);
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#endif /* NVGPU_PMU_GP10B_H */
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