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6b90684cee
On gv11b we can have multiple SMs per TPC. Add sm_per_tpc in vgpu constants to properly dimension the virtual SM to TPC/GPC mapping in virtualization case. Use TEGRA_VGPU_CMD_GET_SMS_MAPPING to query current mapping. Bug 2039676 Change-Id: I817be18f9a28cfb9bd8af207d7d6341a2ec3994b Signed-off-by: Thomas Fleury <tfleury@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1631203 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
67 lines
2.5 KiB
C
67 lines
2.5 KiB
C
/*
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* Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef _GR_VGPU_H_
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#define _GR_VGPU_H_
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#include <nvgpu/types.h>
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struct gk20a;
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struct channel_gk20a;
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struct gr_gk20a;
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struct gr_zcull_info;
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struct zbc_entry;
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struct zbc_query_params;
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struct dbg_session_gk20a;
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void vgpu_gr_detect_sm_arch(struct gk20a *g);
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void vgpu_gr_free_channel_ctx(struct channel_gk20a *c, bool is_tsg);
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int vgpu_gr_alloc_obj_ctx(struct channel_gk20a *c, u32 class_num, u32 flags);
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int vgpu_gr_bind_ctxsw_zcull(struct gk20a *g, struct gr_gk20a *gr,
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struct channel_gk20a *c, u64 zcull_va,
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u32 mode);
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int vgpu_gr_get_zcull_info(struct gk20a *g, struct gr_gk20a *gr,
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struct gr_zcull_info *zcull_params);
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u32 vgpu_gr_get_gpc_tpc_mask(struct gk20a *g, u32 gpc_index);
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u32 vgpu_gr_get_max_fbps_count(struct gk20a *g);
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u32 vgpu_gr_get_fbp_en_mask(struct gk20a *g);
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u32 vgpu_gr_get_max_ltc_per_fbp(struct gk20a *g);
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u32 vgpu_gr_get_max_lts_per_ltc(struct gk20a *g);
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u32 *vgpu_gr_rop_l2_en_mask(struct gk20a *g);
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int vgpu_gr_add_zbc(struct gk20a *g, struct gr_gk20a *gr,
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struct zbc_entry *zbc_val);
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int vgpu_gr_query_zbc(struct gk20a *g, struct gr_gk20a *gr,
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struct zbc_query_params *query_params);
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int vgpu_gr_set_sm_debug_mode(struct gk20a *g,
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struct channel_gk20a *ch, u64 sms, bool enable);
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int vgpu_gr_update_smpc_ctxsw_mode(struct gk20a *g,
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struct channel_gk20a *ch, bool enable);
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int vgpu_gr_update_hwpm_ctxsw_mode(struct gk20a *g,
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struct channel_gk20a *ch, bool enable);
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int vgpu_gr_clear_sm_error_state(struct gk20a *g,
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struct channel_gk20a *ch, u32 sm_id);
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int vgpu_gr_suspend_contexts(struct gk20a *g,
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struct dbg_session_gk20a *dbg_s,
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int *ctx_resident_ch_fd);
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int vgpu_gr_resume_contexts(struct gk20a *g,
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struct dbg_session_gk20a *dbg_s,
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int *ctx_resident_ch_fd);
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int vgpu_gr_commit_inst(struct channel_gk20a *c, u64 gpu_va);
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int vgpu_gr_init_sm_id_table(struct gk20a *g);
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int vgpu_gr_init_fs_state(struct gk20a *g);
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#endif
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