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8e840a5af1
Current clk unit has multiple header files under include folder. This has combination of public struct which is accessed outside the unit and private struct which is accessed within clk unit. This patch segregates them based on their accessibility. All private items are moved into ucode_clk_inf.h from include which only clk can access. All public items are moved into include/clk.h which other units can access and removed the clk_xxx.h files NVGPU-4689 Change-Id: I469270ae539e09a3f6fe6187207791732407863e Signed-off-by: Abdul Salam <absalam@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2298220 Tested-by: mobile promotions <svcmobile_promotions@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
113 lines
3.3 KiB
C
113 lines
3.3 KiB
C
/*
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* Copyright (c) 2016-2020, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#ifndef NVGPU_CLK_DOMAIN_H
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#define NVGPU_CLK_DOMAIN_H
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#include <nvgpu/pmu/pmuif/ctrlboardobj.h>
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#include <nvgpu/pmu/pmuif/nvgpu_cmdif.h>
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#define CLK_DOMAIN_BOARDOBJGRP_VERSION 0x30
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#define CLK_DOMAIN_BOARDOBJGRP_VERSION_35 0x35
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#define CLK_TABLE_HAL_ENTRY_GP 0x02
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#define CLK_TABLE_HAL_ENTRY_GV 0x03
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#define CLK_CLKMON_VFE_INDEX_INVALID 0xFF
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struct nvgpu_clk_domains;
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struct nvgpu_clk_domain;
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typedef int clkgetslaveclk(struct gk20a *g, struct nvgpu_clk_pmupstate *pclk,
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struct nvgpu_clk_domain *pdomain, u16 *clkmhz,
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u16 masterclkmhz);
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struct clk_domain_3x {
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struct nvgpu_clk_domain super;
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bool b_noise_aware_capable;
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};
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struct clk_domain_3x_fixed {
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struct clk_domain_3x super;
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u16 freq_mhz;
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};
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struct clk_domain_3x_prog {
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struct clk_domain_3x super;
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u8 clk_prog_idx_first;
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u8 clk_prog_idx_last;
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bool b_force_noise_unaware_ordering;
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struct ctrl_clk_freq_delta factory_delta;
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short freq_delta_min_mhz;
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short freq_delta_max_mhz;
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struct ctrl_clk_clk_delta deltas;
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u8 noise_unaware_ordering_index;
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u8 noise_aware_ordering_index;
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};
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struct clk_domain_35_prog {
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struct clk_domain_3x_prog super;
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u8 pre_volt_ordering_index;
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u8 post_volt_ordering_index;
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u8 clk_pos;
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u8 clk_vf_curve_count;
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struct ctrl_clk_domain_info_35_prog_clk_mon clkmon_info;
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struct ctrl_clk_domain_control_35_prog_clk_mon clkmon_ctrl;
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u32 por_volt_delta_uv[CTRL_VOLT_VOLT_RAIL_CLIENT_MAX_RAILS];
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};
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struct clk_domain_3x_master {
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struct clk_domain_3x_prog super;
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u32 slave_idxs_mask;
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};
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struct clk_domain_35_master {
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struct clk_domain_35_prog super;
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struct clk_domain_3x_master master;
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struct boardobjgrpmask_e32 master_slave_domains_grp_mask;
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};
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struct clk_domain_3x_slave {
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struct clk_domain_3x_prog super;
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u8 master_idx;
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clkgetslaveclk *clkdomainclkgetslaveclk;
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};
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struct clk_domain_30_slave {
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u8 rsvd;
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u8 master_idx;
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clkgetslaveclk *clkdomainclkgetslaveclk;
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};
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struct clk_domain_35_slave {
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struct clk_domain_35_prog super;
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struct clk_domain_30_slave slave;
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};
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int clk_domain_init_pmupstate(struct gk20a *g);
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void clk_domain_free_pmupstate(struct gk20a *g);
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int clk_pmu_clk_domains_load(struct gk20a *g);
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int clk_domain_sw_setup(struct gk20a *g);
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int clk_domain_pmu_setup(struct gk20a *g);
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#endif /* NVGPU_CLK_DOMAIN_H */
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