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6663a1feaf
Added doxygen documentation for netlist public functions and data structures. Moved struct ctxsw_buf_offset_map_entry to correct location from netlist.h to gr/hwpm_map.h. JIRA NVGPU-3929 Change-Id: Ibefd89475bcf59d01cfad83a1e702e10d70a0de1 Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/2216186 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com> Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Vinod Gopalakrishnakurup <vinodg@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
61 lines
2.0 KiB
C
61 lines
2.0 KiB
C
/*
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* Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#ifndef NVGPU_GR_HWPM_MAP_H
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#define NVGPU_GR_HWPM_MAP_H
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#ifdef CONFIG_NVGPU_DEBUGGER
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#include <nvgpu/types.h>
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struct gk20a;
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struct ctxsw_buf_offset_map_entry;
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struct nvgpu_gr_config;
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struct ctxsw_buf_offset_map_entry {
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u32 addr; /* Register address */
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u32 offset; /* Offset in ctxt switch buffer */
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};
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struct nvgpu_gr_hwpm_map {
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u32 pm_ctxsw_image_size;
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u32 count;
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struct ctxsw_buf_offset_map_entry *map;
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bool init;
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};
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int nvgpu_gr_hwpm_map_init(struct gk20a *g, struct nvgpu_gr_hwpm_map **hwpm_map,
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u32 size);
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void nvgpu_gr_hwpm_map_deinit(struct gk20a *g,
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struct nvgpu_gr_hwpm_map *hwpm_map);
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u32 nvgpu_gr_hwpm_map_get_size(struct nvgpu_gr_hwpm_map *hwpm_map);
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int nvgpu_gr_hwmp_map_find_priv_offset(struct gk20a *g,
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struct nvgpu_gr_hwpm_map *hwpm_map,
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u32 addr, u32 *priv_offset, struct nvgpu_gr_config *config);
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#endif /* CONFIG_NVGPU_DEBUGGER */
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#endif /* NVGPU_GR_HWPM_MAP_H */
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