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406913dc42
Currently, size of zbc index table is defined as a macro. This macro is independent of the number of address bits in the ltc zbc index register. Adding below hal will update zbc index table size as per number of address bits. Add hal to get gr_zbc_index_table_size: u32 (*zbc_table_size)(struct gk20a *g); ZBC index table address 0 is reserved. Logic to start zbc table index from 1 is moved to corresponding hals. JIRA NVGPU-4838 Change-Id: I700cadfdd1f3dc5f323055b8f44d769d6627920a Signed-off-by: Vedashree Vidwans <vvidwans@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2288479 Tested-by: mobile promotions <svcmobile_promotions@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
97 lines
3.9 KiB
C
97 lines
3.9 KiB
C
/*
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* Copyright (c) 2019-2020, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#ifndef NVGPU_GR_ZBC_H
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#define NVGPU_GR_ZBC_H
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#include <nvgpu/types.h>
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#define NVGPU_GR_ZBC_COLOR_VALUE_SIZE 4U /* RGBA */
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/* index zero reserved to indicate "not ZBCd" */
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#define NVGPU_GR_ZBC_STARTOF_TABLE 1U
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#define NVGPU_GR_ZBC_TYPE_INVALID 0U
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#define NVGPU_GR_ZBC_TYPE_COLOR 1U
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#define NVGPU_GR_ZBC_TYPE_DEPTH 2U
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#define NVGPU_GR_ZBC_TYPE_STENCIL 3U
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struct gk20a;
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struct zbc_color_table;
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struct zbc_depth_table;
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struct zbc_s_table;
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struct nvgpu_gr_zbc_entry;
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struct nvgpu_gr_zbc;
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struct nvgpu_gr_zbc_query_params {
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u32 color_ds[NVGPU_GR_ZBC_COLOR_VALUE_SIZE];
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u32 color_l2[NVGPU_GR_ZBC_COLOR_VALUE_SIZE];
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u32 depth;
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u32 ref_cnt;
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u32 format;
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u32 type; /* color or depth */
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u32 index_size; /* [out] size, [in] index */
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};
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int nvgpu_gr_zbc_init(struct gk20a *g, struct nvgpu_gr_zbc **zbc);
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void nvgpu_gr_zbc_deinit(struct gk20a *g, struct nvgpu_gr_zbc *zbc);
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int nvgpu_gr_zbc_load_table(struct gk20a *g, struct nvgpu_gr_zbc *zbc);
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int nvgpu_gr_zbc_add_depth(struct gk20a *g, struct nvgpu_gr_zbc *zbc,
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struct nvgpu_gr_zbc_entry *depth_val, u32 index);
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int nvgpu_gr_zbc_add_color(struct gk20a *g, struct nvgpu_gr_zbc *zbc,
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struct nvgpu_gr_zbc_entry *color_val, u32 index);
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int nvgpu_gr_zbc_query_table(struct gk20a *g, struct nvgpu_gr_zbc *zbc,
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struct nvgpu_gr_zbc_query_params *query_params);
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int nvgpu_gr_zbc_set_table(struct gk20a *g, struct nvgpu_gr_zbc *zbc,
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struct nvgpu_gr_zbc_entry *zbc_val);
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int nvgpu_gr_zbc_stencil_query_table(struct gk20a *g, struct nvgpu_gr_zbc *zbc,
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struct nvgpu_gr_zbc_query_params *query_params);
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bool nvgpu_gr_zbc_add_type_stencil(struct gk20a *g, struct nvgpu_gr_zbc *zbc,
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struct nvgpu_gr_zbc_entry *zbc_val,
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int *ret_val);
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int nvgpu_gr_zbc_load_stencil_default_tbl(struct gk20a *g,
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struct nvgpu_gr_zbc *zbc);
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int nvgpu_gr_zbc_load_stencil_tbl(struct gk20a *g, struct nvgpu_gr_zbc *zbc);
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struct nvgpu_gr_zbc_entry *nvgpu_gr_zbc_entry_alloc(struct gk20a *g);
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void nvgpu_gr_zbc_entry_free(struct gk20a *g, struct nvgpu_gr_zbc_entry *entry);
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u32 nvgpu_gr_zbc_get_entry_color_ds(struct nvgpu_gr_zbc_entry *entry,
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int idx);
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void nvgpu_gr_zbc_set_entry_color_ds(struct nvgpu_gr_zbc_entry *entry,
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int idx, u32 ds);
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u32 nvgpu_gr_zbc_get_entry_color_l2(struct nvgpu_gr_zbc_entry *entry,
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int idx);
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void nvgpu_gr_zbc_set_entry_color_l2(struct nvgpu_gr_zbc_entry *entry,
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int idx, u32 l2);
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u32 nvgpu_gr_zbc_get_entry_depth(struct nvgpu_gr_zbc_entry *entry);
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void nvgpu_gr_zbc_set_entry_depth(struct nvgpu_gr_zbc_entry *entry,
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u32 depth);
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u32 nvgpu_gr_zbc_get_entry_type(struct nvgpu_gr_zbc_entry *entry);
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void nvgpu_gr_zbc_set_entry_type(struct nvgpu_gr_zbc_entry *entry,
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u32 type);
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u32 nvgpu_gr_zbc_get_entry_format(struct nvgpu_gr_zbc_entry *entry);
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void nvgpu_gr_zbc_set_entry_format(struct nvgpu_gr_zbc_entry *entry,
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u32 format);
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#endif /* NVGPU_GR_ZBC_H */
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