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MISRA rule 21.2 forbids the usage of identifier names which start with an underscore. Fix the violations of MISRA rule 21.2 in atomic unit. Jira NVGPU-3139 Change-Id: I4fbed30542bdd2a2444a5619b5bb2bb5c7736472 Signed-off-by: ajesh <akv@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/2111441 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Philip Elcan <pelcan@nvidia.com> Reviewed-by: Alex Waterman <alexw@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
197 lines
4.8 KiB
C
197 lines
4.8 KiB
C
/*
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* Copyright (c) 2017-2019, NVIDIA CORPORATION. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef __NVGPU_ATOMIC_LINUX_H__
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#define __NVGPU_ATOMIC_LINUX_H__
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#ifdef __KERNEL__
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#include <linux/atomic.h>
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#endif
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typedef struct nvgpu_atomic {
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atomic_t atomic_var;
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} nvgpu_atomic_t;
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typedef struct nvgpu_atomic64 {
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atomic64_t atomic_var;
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} nvgpu_atomic64_t;
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#define nvgpu_atomic_init_impl(i) { ATOMIC_INIT(i) }
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#define nvgpu_atomic64_init_impl(i) { ATOMIC64_INIT(i) }
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static inline void nvgpu_atomic_set_impl(nvgpu_atomic_t *v, int i)
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{
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atomic_set(&v->atomic_var, i);
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}
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static inline int nvgpu_atomic_read_impl(nvgpu_atomic_t *v)
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{
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return atomic_read(&v->atomic_var);
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}
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static inline void nvgpu_atomic_inc_impl(nvgpu_atomic_t *v)
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{
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atomic_inc(&v->atomic_var);
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}
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static inline int nvgpu_atomic_inc_return_impl(nvgpu_atomic_t *v)
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{
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return atomic_inc_return(&v->atomic_var);
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}
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static inline void nvgpu_atomic_dec_impl(nvgpu_atomic_t *v)
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{
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atomic_dec(&v->atomic_var);
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}
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static inline int nvgpu_atomic_dec_return_impl(nvgpu_atomic_t *v)
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{
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return atomic_dec_return(&v->atomic_var);
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}
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static inline int nvgpu_atomic_cmpxchg_impl(nvgpu_atomic_t *v, int old, int new)
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{
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return atomic_cmpxchg(&v->atomic_var, old, new);
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}
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static inline int nvgpu_atomic_xchg_impl(nvgpu_atomic_t *v, int new)
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{
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return atomic_xchg(&v->atomic_var, new);
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}
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static inline bool nvgpu_atomic_inc_and_test_impl(nvgpu_atomic_t *v)
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{
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return atomic_inc_and_test(&v->atomic_var);
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}
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static inline bool nvgpu_atomic_dec_and_test_impl(nvgpu_atomic_t *v)
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{
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return atomic_dec_and_test(&v->atomic_var);
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}
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static inline void nvgpu_atomic_sub_impl(int i, nvgpu_atomic_t *v)
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{
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atomic_sub(i, &v->atomic_var);
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}
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static inline int nvgpu_atomic_sub_return_impl(int i, nvgpu_atomic_t *v)
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{
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return atomic_sub_return(i, &v->atomic_var);
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}
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static inline bool nvgpu_atomic_sub_and_test_impl(int i, nvgpu_atomic_t *v)
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{
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return atomic_sub_and_test(i, &v->atomic_var);
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}
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static inline void nvgpu_atomic_add_impl(int i, nvgpu_atomic_t *v)
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{
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atomic_add(i, &v->atomic_var);
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}
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static inline int nvgpu_atomic_add_return_impl(int i, nvgpu_atomic_t *v)
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{
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return atomic_add_return(i, &v->atomic_var);
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}
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static inline int nvgpu_atomic_add_unless_impl(nvgpu_atomic_t *v, int a, int u)
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{
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return atomic_add_unless(&v->atomic_var, a, u);
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}
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static inline void nvgpu_atomic64_set_impl(nvgpu_atomic64_t *v, long x)
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{
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atomic64_set(&v->atomic_var, x);
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}
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static inline long nvgpu_atomic64_read_impl(nvgpu_atomic64_t *v)
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{
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return atomic64_read(&v->atomic_var);
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}
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static inline void nvgpu_atomic64_add_impl(long x, nvgpu_atomic64_t *v)
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{
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atomic64_add(x, &v->atomic_var);
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}
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static inline long nvgpu_atomic64_add_return_impl(long x, nvgpu_atomic64_t *v)
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{
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return atomic64_add_return(x, &v->atomic_var);
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}
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static inline long nvgpu_atomic64_add_unless_impl(nvgpu_atomic64_t *v, long a,
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long u)
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{
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return atomic64_add_unless(&v->atomic_var, a, u);
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}
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static inline void nvgpu_atomic64_inc_impl(nvgpu_atomic64_t *v)
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{
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atomic64_inc(&v->atomic_var);
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}
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static inline long nvgpu_atomic64_inc_return_impl(nvgpu_atomic64_t *v)
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{
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return atomic64_inc_return(&v->atomic_var);
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}
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static inline bool nvgpu_atomic64_inc_and_test_impl(nvgpu_atomic64_t *v)
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{
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return atomic64_inc_and_test(&v->atomic_var);
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}
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static inline void nvgpu_atomic64_dec_impl(nvgpu_atomic64_t *v)
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{
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atomic64_dec(&v->atomic_var);
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}
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static inline long nvgpu_atomic64_dec_return_impl(nvgpu_atomic64_t *v)
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{
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return atomic64_dec_return(&v->atomic_var);
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}
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static inline bool nvgpu_atomic64_dec_and_test_impl(nvgpu_atomic64_t *v)
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{
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return atomic64_dec_and_test(&v->atomic_var);
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}
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static inline long nvgpu_atomic64_xchg_impl(nvgpu_atomic64_t *v, long new)
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{
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return atomic64_xchg(&v->atomic_var, new);
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}
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static inline long nvgpu_atomic64_cmpxchg_impl(nvgpu_atomic64_t *v,
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long old, long new)
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{
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return atomic64_cmpxchg(&v->atomic_var, old, new);
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}
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static inline void nvgpu_atomic64_sub_impl(long x, nvgpu_atomic64_t *v)
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{
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atomic64_sub(x, &v->atomic_var);
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}
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static inline long nvgpu_atomic64_sub_return_impl(long x, nvgpu_atomic64_t *v)
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{
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return atomic64_sub_return(x, &v->atomic_var);
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}
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static inline bool nvgpu_atomic64_sub_and_test_impl(long x, nvgpu_atomic64_t *v)
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{
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return atomic64_sub_and_test(x, &v->atomic_var);
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}
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#endif /*__NVGPU_ATOMIC_LINUX_H__ */
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