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26406a070d
Xavier Chip Product POR was updated to 20G only. No more qual work happening for 16G. So we do not plan to support 16G. Now that we have a single speed left, remove the code added to support nvlink speed from VBIOS as it is redundant. JIRA NVGPU-2964 Change-Id: Icd71ebb8271240818e36d40bf73c60f0c5beb6bf Signed-off-by: tkudav <tkudav@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2284175 Tested-by: mobile promotions <svcmobile_promotions@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
57 lines
2.3 KiB
C
57 lines
2.3 KiB
C
/*
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* Copyright (c) 2019-2020, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#ifndef NVGPU_NVLINK_MINION_H
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#define NVGPU_NVLINK_MINION_H
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#include <nvgpu/types.h>
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struct gk20a;
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struct nvgpu_firmware;
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#define MINION_REG_RD32(g, off) nvgpu_readl(g, (g)->nvlink.minion_base + (off))
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#define MINION_REG_WR32(g, off, v) nvgpu_writel(g, (g)->nvlink.minion_base + (off), (v))
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enum nvgpu_nvlink_minion_dlcmd {
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NVGPU_NVLINK_MINION_DLCMD_INITPHY,
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NVGPU_NVLINK_MINION_DLCMD_INITLANEENABLE,
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NVGPU_NVLINK_MINION_DLCMD_INITDLPL,
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NVGPU_NVLINK_MINION_DLCMD_INITRXTERM,
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NVGPU_NVLINK_MINION_DLCMD_INITTL,
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NVGPU_NVLINK_MINION_DLCMD_LANEDISABLE,
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NVGPU_NVLINK_MINION_DLCMD_SETACMODE,
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NVGPU_NVLINK_MINION_DLCMD_LANESHUTDOWN,
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NVGPU_NVLINK_MINION_DLCMD_TXCLKSWITCH_PLL,
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NVGPU_NVLINK_MINION_DLCMD_INITPLL_1,
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NVGPU_NVLINK_MINION_DLCMD_TURING_INITDLPL_TO_CHIPA,
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NVGPU_NVLINK_MINION_DLCMD_TURING_RXDET,
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NVGPU_NVLINK_MINION_DLCMD__LAST,
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};
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u32 nvgpu_nvlink_minion_extract_word(struct nvgpu_firmware *fw, u32 idx);
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int nvgpu_nvlink_minion_load(struct gk20a *g);
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int nvgpu_nvlink_minion_load_ucode(struct gk20a *g,
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struct nvgpu_firmware *nvgpu_minion_fw);
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void nvgpu_nvlink_free_minion_used_mem(struct gk20a *g,
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struct nvgpu_firmware *nvgpu_minion_fw);
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#endif /* NVGPU_NVLINK_MINION_H */
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