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999eabbcd7
MISRA rule 10.1 doesn't allow the usage of non-boolean variables as booleans. Fix violations where a variable of type non-boolean is used as a boolean and changed few instances of BIT() to BIT32() or BIT64(). JIRA NVGPU-646 Change-Id: I100606a69717c12839aa9c35e7bf6c18749db56e Signed-off-by: Amulya <Amurthyreddy@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1809836 GVS: Gerrit_Virtual_Submit Tested-by: Amulya Murthyreddy <amurthyreddy@nvidia.com> Reviewed-by: Adeel Raza <araza@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
70 lines
2.5 KiB
C
70 lines
2.5 KiB
C
/*
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* Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#ifndef NVGPU_XVE_H
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#define NVGPU_XVE_H
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#include <nvgpu/types.h>
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#include <nvgpu/log2.h>
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#include <nvgpu/bitops.h>
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/*
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* For the available speeds bitmap.
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*/
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#define GPU_XVE_SPEED_2P5 BIT32(0)
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#define GPU_XVE_SPEED_5P0 BIT32(1)
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#define GPU_XVE_SPEED_8P0 BIT32(2)
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#define GPU_XVE_NR_SPEEDS 3U
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#define GPU_XVE_SPEED_MASK (GPU_XVE_SPEED_2P5 | \
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GPU_XVE_SPEED_5P0 | \
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GPU_XVE_SPEED_8P0)
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/*
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* The HW uses a 2 bit field where speed is defined by a number:
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*
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* NV_XVE_LINK_CONTROL_STATUS_LINK_SPEED_2P5 = 1
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* NV_XVE_LINK_CONTROL_STATUS_LINK_SPEED_5P0 = 2
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* NV_XVE_LINK_CONTROL_STATUS_LINK_SPEED_8P0 = 3
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*
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* This isn't ideal for a bitmap with available speeds. So the external
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* APIs think about speeds as a bit in a bitmap and this function converts
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* from those bits to the actual HW speed setting.
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*
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* @speed_bit must have only 1 bit set and must be one of the 3 available
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* HW speeds. Not all chips support all speeds so use available_speeds() to
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* determine what a given chip supports.
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*/
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static inline const char *xve_speed_to_str(u32 speed)
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{
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if ((speed == 0U) || !is_power_of_2(speed) ||
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(speed & GPU_XVE_SPEED_MASK) == 0U) {
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return "Unknown ???";
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}
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return (speed & GPU_XVE_SPEED_2P5) != 0U ? "Gen1" :
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(speed & GPU_XVE_SPEED_5P0) != 0U ? "Gen2" :
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(speed & GPU_XVE_SPEED_8P0) != 0U ? "Gen3" :
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"Unknown ???";
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}
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#endif /* NVGPU_XVE_H */
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