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6dd57c29b0
Move the gm206 HW headers to a new directory specially for them: include/nvgpu/hw/gm206 And change the code to include like so: #include <nvgpu/hw/gm206/hw_fb_gm206.h> This is part of the process to restructure the nvgpu driver. Bug 1799159 Change-Id: I90dc39e64e1b58ee9e87fbc26ad0d18c361e239c Signed-off-by: Alex Waterman <alexw@nvidia.com> Reviewed-on: http://git-master/r/1244792 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
94 lines
2.8 KiB
C
94 lines
2.8 KiB
C
/*
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* gm206 GR
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*
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* Copyright (c) 2011-2016, NVIDIA CORPORATION. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*/
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#include <linux/types.h>
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#include <linux/delay.h> /* for mdelay */
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#include <linux/io.h>
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#include <linux/tegra-fuse.h>
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#include <linux/vmalloc.h>
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#include "gk20a/gk20a.h"
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#include "gm20b/gr_gm20b.h"
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#include "gr_gm206.h"
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#include <nvgpu/hw/gm206/hw_fb_gm206.h>
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#include <nvgpu/hw/gm206/hw_gr_gm206.h>
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static void gr_gm206_init_gpc_mmu(struct gk20a *g)
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{
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u32 temp;
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gk20a_dbg_info("initialize gpc mmu");
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temp = gk20a_readl(g, fb_mmu_ctrl_r());
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temp &= gr_gpcs_pri_mmu_ctrl_vm_pg_size_m() |
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gr_gpcs_pri_mmu_ctrl_use_pdb_big_page_size_m() |
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gr_gpcs_pri_mmu_ctrl_use_full_comp_tag_line_m() |
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gr_gpcs_pri_mmu_ctrl_vol_fault_m() |
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gr_gpcs_pri_mmu_ctrl_comp_fault_m() |
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gr_gpcs_pri_mmu_ctrl_miss_gran_m() |
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gr_gpcs_pri_mmu_ctrl_cache_mode_m() |
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gr_gpcs_pri_mmu_ctrl_mmu_aperture_m() |
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gr_gpcs_pri_mmu_ctrl_mmu_vol_m() |
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gr_gpcs_pri_mmu_ctrl_mmu_disable_m();
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gk20a_writel(g, gr_gpcs_pri_mmu_ctrl_r(), temp);
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gk20a_writel(g, gr_gpcs_pri_mmu_pm_unit_mask_r(), 0);
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gk20a_writel(g, gr_gpcs_pri_mmu_pm_req_mask_r(), 0);
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gk20a_writel(g, gr_gpcs_pri_mmu_debug_ctrl_r(),
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gk20a_readl(g, fb_mmu_debug_ctrl_r()));
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gk20a_writel(g, gr_gpcs_pri_mmu_debug_wr_r(),
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gk20a_readl(g, fb_mmu_debug_wr_r()));
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gk20a_writel(g, gr_gpcs_pri_mmu_debug_rd_r(),
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gk20a_readl(g, fb_mmu_debug_rd_r()));
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gk20a_writel(g, gr_gpcs_mmu_num_active_ltcs_r(),
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gk20a_readl(g, fb_fbhub_num_active_ltcs_r()));
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/* TODO: num_active_ltcs2! */
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gk20a_writel(g, 0x50833c, gk20a_readl(g, 0x100804));
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}
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static void gr_gm206_bundle_cb_defaults(struct gk20a *g)
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{
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struct gr_gk20a *gr = &g->gr;
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gr->bundle_cb_default_size =
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gr_scc_bundle_cb_size_div_256b__prod_v();
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gr->min_gpm_fifo_depth =
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gr_pd_ab_dist_cfg2_state_limit_min_gpm_fifo_depths_v();
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gr->bundle_cb_token_limit =
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gr_pd_ab_dist_cfg2_token_limit_init_v();
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}
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static void gr_gm206_cb_size_default(struct gk20a *g)
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{
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struct gr_gk20a *gr = &g->gr;
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if (!gr->attrib_cb_default_size)
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gr->attrib_cb_default_size =
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gr_gpc0_ppc0_cbm_beta_cb_size_v_default_v();
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gr->alpha_cb_default_size =
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gr_gpc0_ppc0_cbm_alpha_cb_size_v_default_v();
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}
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void gm206_init_gr(struct gpu_ops *gops)
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{
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gm20b_init_gr(gops);
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gops->gr.init_gpc_mmu = gr_gm206_init_gpc_mmu;
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gops->gr.bundle_cb_defaults = gr_gm206_bundle_cb_defaults;
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gops->gr.cb_size_default = gr_gm206_cb_size_default;
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}
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