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268721975c
- nvgpu_pmu_reset() as pmu reset for all chips & removed gk20a_pmu_reset() & gp106_pmu_reset() along with dependent code. - Created ops to do PMU engine reset & to know the engine reset status - Removed pmu.reset ops & replaced with nvgpu_flcn_reset(pmu->flcn) - Moved sec2 reset to sec2_gp106 from pmu_gp106 & cleaned PMU code part of sec2. JIRA NVGPU-99 Change-Id: I7575e4ca2b34922d73d171f6a41bfcdc2f40dc96 Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-on: https://git-master/r/1507881 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
81 lines
2.9 KiB
C
81 lines
2.9 KiB
C
/*
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* drivers/video/tegra/host/gk20a/pmu_gk20a.h
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*
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* GK20A PMU (aka. gPMU outside gk20a context)
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*
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* Copyright (c) 2011-2017, NVIDIA CORPORATION. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program; if not, write to the Free Software Foundation, Inc.,
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* 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
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*/
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#ifndef __PMU_GK20A_H__
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#define __PMU_GK20A_H__
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#include <linux/version.h>
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#include <nvgpu/flcnif_cmn.h>
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#include <nvgpu/pmuif/nvgpu_gpmu_cmdif.h>
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#include <nvgpu/pmu.h>
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struct nvgpu_firmware;
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#define ZBC_MASK(i) (~(~(0) << ((i)+1)) & 0xfffe)
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bool gk20a_pmu_is_interrupted(struct nvgpu_pmu *pmu);
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void gk20a_pmu_isr(struct gk20a *g);
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u32 gk20a_pmu_pg_engines_list(struct gk20a *g);
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u32 gk20a_pmu_pg_feature_list(struct gk20a *g, u32 pg_engine_id);
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void gk20a_pmu_save_zbc(struct gk20a *g, u32 entries);
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void gk20a_pmu_init_perfmon_counter(struct gk20a *g);
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void gk20a_pmu_pg_idle_counter_config(struct gk20a *g, u32 pg_engine_id);
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int gk20a_pmu_mutex_acquire(struct nvgpu_pmu *pmu, u32 id, u32 *token);
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int gk20a_pmu_mutex_release(struct nvgpu_pmu *pmu, u32 id, u32 *token);
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int gk20a_pmu_queue_head(struct nvgpu_pmu *pmu, struct pmu_queue *queue,
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u32 *head, bool set);
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int gk20a_pmu_queue_tail(struct nvgpu_pmu *pmu, struct pmu_queue *queue,
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u32 *tail, bool set);
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void gk20a_pmu_msgq_tail(struct nvgpu_pmu *pmu, u32 *tail, bool set);
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u32 gk20a_pmu_read_idle_counter(struct gk20a *g, u32 counter_id);
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void gk20a_pmu_reset_idle_counter(struct gk20a *g, u32 counter_id);
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void gk20a_init_pmu_ops(struct gpu_ops *gops);
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void pmu_copy_to_dmem(struct nvgpu_pmu *pmu,
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u32 dst, u8 *src, u32 size, u8 port);
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int pmu_bootstrap(struct nvgpu_pmu *pmu);
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void pmu_dump_elpg_stats(struct nvgpu_pmu *pmu);
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void pmu_dump_falcon_stats(struct nvgpu_pmu *pmu);
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void pmu_enable_irq(struct nvgpu_pmu *pmu, bool enable);
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int pmu_wait_message_cond(struct nvgpu_pmu *pmu, u32 timeout_ms,
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u32 *var, u32 val);
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void pmu_handle_fecs_boot_acr_msg(struct gk20a *g, struct pmu_msg *msg,
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void *param, u32 handle, u32 status);
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void gk20a_pmu_elpg_statistics(struct gk20a *g, u32 pg_engine_id,
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struct pmu_pg_stats_data *pg_stat_data);
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bool gk20a_pmu_is_engine_in_reset(struct gk20a *g);
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int gk20a_pmu_engine_reset(struct gk20a *g, bool do_reset);
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int pmu_idle(struct nvgpu_pmu *pmu);
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bool nvgpu_find_hex_in_string(char *strings, struct gk20a *g, u32 *hex_pos);
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#endif /*__PMU_GK20A_H__*/
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