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f11cd6d4f3
New register generators generated correct kernel headers for mme_shadow_ram register and associated fields. Modified code to use this updated hw defs. JIRA NVGPU-3558 Change-Id: I2d1f4a4bd713abc16414208b2a4efccd114a6a59 Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/2167093 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Raghuram Kothakota <rkothakota@nvidia.com> Reviewed-by: Vinod Gopalakrishnakurup <vinodg@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>