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3e6779d554
MISRA rule 14.4 doesn't allow the usage of integer types as booleans in the controlling expression of an if statement or an iteration statement. Fix violations where the integer variables err, ret, status are used as booleans in the controlling expression of if and loop statements. JIRA NVGPU-1019 Change-Id: I36494e84ee6cd4a108e2a539f48f102e47e2f7f4 Signed-off-by: Amurthyreddy <amurthyreddy@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1926820 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
44 lines
1.7 KiB
C
44 lines
1.7 KiB
C
/*
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* general power device structures & definitions
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*
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* Copyright (c) 2016-2018, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#ifndef NVGPU_PMGR_H
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#define NVGPU_PMGR_H
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#include "pwrdev.h"
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#include "pwrmonitor.h"
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#include "pwrpolicy.h"
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struct pmgr_pmupstate {
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struct pwr_devices pmgr_deviceobjs;
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struct pmgr_pwr_monitor pmgr_monitorobjs;
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struct pmgr_pwr_policy pmgr_policyobjs;
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};
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int pmgr_domain_sw_setup(struct gk20a *g);
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int pmgr_domain_pmu_setup(struct gk20a *g);
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int pmgr_pwr_devices_get_current(struct gk20a *g, u32 *val);
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int pmgr_pwr_devices_get_voltage(struct gk20a *g, u32 *val);
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int pmgr_pwr_devices_get_power(struct gk20a *g, u32 *val);
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#endif /* NVGPU_PMGR_H */
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