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66a2511a36
Begin removing all of the myriad flag variables in struct gk20a and replace that with one API that checks for flags being enabled or disabled. The API is as follows: bool nvgpu_is_enabled(struct gk20a *g, int flag); bool __nvgpu_set_enabled(struct gk20a *g, int flag, bool state); These APIs allow many of the gk20a flags to be replaced by defines. This makes flag usage consistent and saves a small amount of memory in struct gk20a. Also it makes struct gk20a easier to read since there's less clutter scattered through out. JIRA NVGPU-84 Change-Id: I6525cecbe97c4e8379e5f53e29ef0b4dbd1a7fc2 Signed-off-by: Alex Waterman <alexw@nvidia.com> Reviewed-on: http://git-master/r/1488049 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
103 lines
3.3 KiB
C
103 lines
3.3 KiB
C
/*
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* GK20A priv ring
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*
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* Copyright (c) 2011-2017, NVIDIA CORPORATION. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include "gk20a.h"
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#include <nvgpu/log.h>
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#include <nvgpu/timers.h>
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#include <nvgpu/enabled.h>
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#include <nvgpu/hw/gk20a/hw_mc_gk20a.h>
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#include <nvgpu/hw/gk20a/hw_pri_ringmaster_gk20a.h>
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#include <nvgpu/hw/gk20a/hw_pri_ringstation_sys_gk20a.h>
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#include <nvgpu/hw/gk20a/hw_pri_ringstation_gpc_gk20a.h>
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void gk20a_enable_priv_ring(struct gk20a *g)
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{
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if (nvgpu_is_enabled(g, NVGPU_IS_FMODEL))
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return;
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if (g->ops.clock_gating.slcg_priring_load_gating_prod)
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g->ops.clock_gating.slcg_priring_load_gating_prod(g,
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g->slcg_enabled);
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gk20a_writel(g,pri_ringmaster_command_r(),
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0x4);
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gk20a_writel(g, pri_ringstation_sys_decode_config_r(),
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0x2);
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gk20a_readl(g, pri_ringstation_sys_decode_config_r());
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}
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void gk20a_priv_ring_isr(struct gk20a *g)
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{
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u32 status0, status1;
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u32 cmd;
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s32 retry = 100;
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u32 gpc;
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u32 gpc_stride = nvgpu_get_litter_value(g, GPU_LIT_GPC_STRIDE);
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if (nvgpu_is_enabled(g, NVGPU_IS_FMODEL))
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return;
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status0 = gk20a_readl(g, pri_ringmaster_intr_status0_r());
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status1 = gk20a_readl(g, pri_ringmaster_intr_status1_r());
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gk20a_dbg(gpu_dbg_intr, "ringmaster intr status0: 0x%08x,"
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"status1: 0x%08x", status0, status1);
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if (pri_ringmaster_intr_status0_gbl_write_error_sys_v(status0) != 0) {
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gk20a_dbg(gpu_dbg_intr, "SYS write error. ADR %08x WRDAT %08x INFO %08x, CODE %08x",
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gk20a_readl(g, pri_ringstation_sys_priv_error_adr_r()),
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gk20a_readl(g, pri_ringstation_sys_priv_error_wrdat_r()),
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gk20a_readl(g, pri_ringstation_sys_priv_error_info_r()),
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gk20a_readl(g, pri_ringstation_sys_priv_error_code_r()));
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}
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for (gpc = 0; gpc < g->gr.gpc_count; gpc++) {
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if (status1 & BIT(gpc)) {
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gk20a_dbg(gpu_dbg_intr, "GPC%u write error. ADR %08x WRDAT %08x INFO %08x, CODE %08x", gpc,
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gk20a_readl(g, pri_ringstation_gpc_gpc0_priv_error_adr_r() + gpc * gpc_stride),
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gk20a_readl(g, pri_ringstation_gpc_gpc0_priv_error_wrdat_r() + gpc * gpc_stride),
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gk20a_readl(g, pri_ringstation_gpc_gpc0_priv_error_info_r() + gpc * gpc_stride),
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gk20a_readl(g, pri_ringstation_gpc_gpc0_priv_error_code_r() + gpc * gpc_stride));
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}
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}
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cmd = gk20a_readl(g, pri_ringmaster_command_r());
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cmd = set_field(cmd, pri_ringmaster_command_cmd_m(),
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pri_ringmaster_command_cmd_ack_interrupt_f());
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gk20a_writel(g, pri_ringmaster_command_r(), cmd);
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do {
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cmd = pri_ringmaster_command_cmd_v(
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gk20a_readl(g, pri_ringmaster_command_r()));
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nvgpu_usleep_range(20, 40);
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} while (cmd != pri_ringmaster_command_cmd_no_cmd_v() && --retry);
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if (retry <= 0)
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nvgpu_warn(g, "priv ringmaster cmd ack too many retries");
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}
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void gk20a_init_priv_ring(struct gpu_ops *gops)
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{
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gops->priv_ring.isr = gk20a_priv_ring_isr;
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}
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