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git://nv-tegra.nvidia.com/linux-nvgpu.git
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e5824d8014
- update gp106 pg engine init/list/features HALs to support MS engine - Added defines & interface for lpwr tables read from vbios. - lpwr module which reads idx/gr/ms table from vbios to map rppg/mscg support with respective p-state - lpwr module public functions to control lpwr features enable/disable mscg/rppg & mclk-change request whenever change in mclk-change parameters - lpwr public functions to know rppg/mscg support for requested pstate, - added mutex t prevent PG transition while arbiter executes pstate transition - nvgpu_clk_arb_get_current_pstate() of clk arbiter to get current pstate JIRA DNVGPU-71 Change-Id: Ifcd640cc19ef630be1e2a9ba07ec84023d8202a0 Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-on: http://git-master/r/1247553 (cherry picked from commit 8a441dea2410e1b5196ef24e56a7768b6980e46b) Reviewed-on: http://git-master/r/1270989 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
93 lines
2.5 KiB
C
93 lines
2.5 KiB
C
/*
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* Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*/
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#ifndef _MSCG_H_
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#define _MSCG_H_
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#define MAX_SWASR_MCLK_FREQ_WITHOUT_WR_TRAINING_MAXWELL_MHZ 540
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#define NV_PMU_PG_PARAM_MCLK_CHANGE_MS_SWASR_ENABLED BIT(0x1)
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#define NV_PMU_PG_PARAM_MCLK_CHANGE_GDDR5_WR_TRAINING_ENABLED BIT(0x3)
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#define LPWR_ENTRY_COUNT_MAX 0x06
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#define LPWR_VBIOS_IDX_ENTRY_COUNT_MAX (LPWR_ENTRY_COUNT_MAX)
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#define LPWR_VBIOS_IDX_ENTRY_RSVD \
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(LPWR_VBIOS_IDX_ENTRY_COUNT_MAX - 1)
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#define LPWR_VBIOS_BASE_SAMPLING_PERIOD_DEFAULT (500)
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struct nvgpu_lpwr_bios_idx_entry {
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u8 pcie_idx;
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u8 gr_idx;
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u8 ms_idx;
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u8 di_idx;
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u8 gc6_idx;
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};
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struct nvgpu_lpwr_bios_idx_data {
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u16 base_sampling_period;
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struct nvgpu_lpwr_bios_idx_entry entry[LPWR_VBIOS_IDX_ENTRY_COUNT_MAX];
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};
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#define LPWR_VBIOS_MS_ENTRY_COUNT_MAX (LPWR_ENTRY_COUNT_MAX)
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struct nvgpu_lpwr_bios_ms_entry {
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bool ms_enabled;
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u32 feature_mask;
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u32 asr_efficiency_thresholdl;
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u16 dynamic_current_logic;
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u16 dynamic_current_sram;
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};
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struct nvgpu_lpwr_bios_ms_data {
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u8 default_entry_idx;
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u32 idle_threshold_us;
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struct nvgpu_lpwr_bios_ms_entry entry[LPWR_VBIOS_MS_ENTRY_COUNT_MAX];
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};
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#define LPWR_VBIOS_GR_ENTRY_COUNT_MAX (LPWR_ENTRY_COUNT_MAX)
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struct nvgpu_lpwr_bios_gr_entry {
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bool gr_enabled;
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u32 feature_mask;
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};
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struct nvgpu_lpwr_bios_gr_data {
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u8 default_entry_idx;
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u32 idle_threshold_us;
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u8 adaptive_gr_multiplier;
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struct nvgpu_lpwr_bios_gr_entry entry[LPWR_VBIOS_GR_ENTRY_COUNT_MAX];
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};
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struct nvgpu_lpwr_bios_data {
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struct nvgpu_lpwr_bios_idx_data idx;
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struct nvgpu_lpwr_bios_ms_data ms;
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struct nvgpu_lpwr_bios_gr_data gr;
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};
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struct obj_lwpr {
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struct nvgpu_lpwr_bios_data lwpr_bios_data;
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u32 mclk_change_cache;
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};
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u32 nvgpu_lpwr_pg_setup(struct gk20a *g);
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int nvgpu_lwpr_mclk_change(struct gk20a *g, u32 pstate);
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int nvgpu_lpwr_enable_pg(struct gk20a *g, bool pstate_lock);
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int nvgpu_lpwr_disable_pg(struct gk20a *g, bool pstate_lock);
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u32 nvgpu_lpwr_is_mscg_supported(struct gk20a *g, u32 pstate_num);
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u32 nvgpu_lpwr_is_rppg_supported(struct gk20a *g, u32 pstate_num);
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u32 nvgpu_lpwr_post_init(struct gk20a *g);
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#endif
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