mirror of
git://nv-tegra.nvidia.com/linux-nvgpu.git
synced 2025-12-22 17:36:20 +03:00
98 lines
3.3 KiB
C
98 lines
3.3 KiB
C
/*
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* Copyright (c) 2021, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#include <nvgpu/gk20a.h>
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#include <nvgpu/nvgpu_init.h>
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#include <nvgpu/nvgpu_err.h>
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#include <nvgpu/nvgpu_err_info.h>
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#include <nvgpu/cic.h>
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#include "cic_priv.h"
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void nvgpu_report_ctxsw_err(struct gk20a *g, u32 hw_unit, u32 err_id,
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void *data)
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{
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int err = 0;
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struct nvgpu_err_desc *err_desc = NULL;
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struct nvgpu_err_msg err_pkt;
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u32 inst = 0;
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struct ctxsw_err_info *err_info = (struct ctxsw_err_info *)data;
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if (g->ops.cic.report_err == NULL) {
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cic_dbg(g, "CIC does not support reporting error "
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"to safety services");
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return;
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}
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if (hw_unit != NVGPU_ERR_MODULE_FECS) {
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nvgpu_err(g, "invalid hw module (%u)", hw_unit);
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err = -EINVAL;
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goto handle_report_failure;
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}
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err = nvgpu_cic_get_err_desc(g, hw_unit, err_id, &err_desc);
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if (err != 0) {
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nvgpu_err(g, "Failed to get err_desc for"
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" err_id (%u) for hw module (%u)",
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err_id, hw_unit);
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goto handle_report_failure;
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}
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nvgpu_init_ctxsw_err_msg(&err_pkt);
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err_pkt.hw_unit_id = hw_unit;
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err_pkt.err_id = err_desc->error_id;
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err_pkt.is_critical = err_desc->is_critical;
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err_pkt.err_info.ctxsw_info.header.sub_unit_id = inst;
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err_pkt.err_info.ctxsw_info.curr_ctx = err_info->curr_ctx;
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err_pkt.err_info.ctxsw_info.chid = err_info->chid;
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err_pkt.err_info.ctxsw_info.ctxsw_status0 = err_info->ctxsw_status0;
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err_pkt.err_info.ctxsw_info.ctxsw_status1 = err_info->ctxsw_status1;
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err_pkt.err_info.ctxsw_info.mailbox_value = err_info->mailbox_value;
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err_pkt.err_desc = err_desc;
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err_pkt.err_size = nvgpu_safe_cast_u64_to_u8(
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sizeof(err_pkt.err_info.ctxsw_info));
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if (g->ops.cic.report_err != NULL) {
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err = g->ops.cic.report_err(g, (void *)&err_pkt,
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sizeof(err_pkt), err_desc->is_critical);
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if (err != 0) {
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nvgpu_err(g, "Failed to report CTXSW error: "
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"err_id=%u, mailbox_val=%u",
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err_id, err_info->mailbox_value);
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}
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}
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handle_report_failure:
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if (err != 0) {
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nvgpu_sw_quiesce(g);
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}
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}
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void nvgpu_inject_ctxsw_swerror(struct gk20a *g, u32 hw_unit,
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u32 err_index, u32 inst)
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{
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struct ctxsw_err_info err_info;
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(void)memset(&err_info, ERR_INJECT_TEST_PATTERN, sizeof(err_info));
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nvgpu_report_ctxsw_err(g, hw_unit, err_index, (void *)&err_info);
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}
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