mirror of
git://nv-tegra.nvidia.com/linux-nvgpu.git
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120 lines
3.7 KiB
C
120 lines
3.7 KiB
C
/*
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* Copyright (c) 2020, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#include <nvgpu/gk20a.h>
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#include <nvgpu/static_analysis.h>
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#include <nvgpu/string.h>
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#include <nvgpu/gmmu.h>
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u32 nvgpu_gmmu_default_big_page_size(void)
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{
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return U32(SZ_64K);
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}
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/*
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* MSS NVLINK HW settings are in force_snoop mode.
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* This will force all the GPU mappings to be coherent.
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* By default the mem aperture is set to sysmem_non_coherent and will use L2
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* atomics.
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* Change target pte aperture to sysmem_coherent if mem attribute requests for
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* platform atomics to use rmw atomic capability.
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*
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*/
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u32 nvgpu_gmmu_aperture_mask(struct gk20a *g,
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enum nvgpu_aperture mem_ap,
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bool platform_atomic_attr,
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u32 sysmem_mask,
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u32 sysmem_coh_mask,
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u32 vidmem_mask)
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{
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if (nvgpu_is_enabled(g, NVGPU_SUPPORT_PLATFORM_ATOMIC) &&
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platform_atomic_attr) {
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mem_ap = APERTURE_SYSMEM_COH;
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}
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return nvgpu_aperture_mask_raw(g, mem_ap,
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sysmem_mask,
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sysmem_coh_mask,
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vidmem_mask);
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}
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static char *map_attrs_to_str(char *dest, struct nvgpu_gmmu_attrs *attrs)
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{
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dest[0] = attrs->cacheable ? 'C' : '-';
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dest[1] = attrs->sparse ? 'S' : '-';
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dest[2] = attrs->priv ? 'P' : '-';
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dest[3] = attrs->valid ? 'V' : '-';
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dest[4] = attrs->platform_atomic ? 'A' : '-';
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dest[5] = '\0';
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return dest;
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}
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void nvgpu_pte_dbg_print(struct gk20a *g,
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struct nvgpu_gmmu_attrs *attrs,
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const char *vm_name, u32 pd_idx, u32 mmu_level_entry_size,
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u64 virt_addr, u64 phys_addr, u32 page_size, u32 *pte_w)
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{
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char attrs_str[6];
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char ctag_str[32] = "\0";
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const char *aperture_str = nvgpu_aperture_str(attrs->aperture);
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const char *perm_str = nvgpu_gmmu_perm_str(attrs->rw_flag);
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#ifdef CONFIG_NVGPU_COMPRESSION
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u64 ctag_tmp = attrs->ctag;
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u32 str_len = 0U;
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u32 ctag_num = 0U;
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/*
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* attrs->ctag is incremented to count current page size as well.
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* Subtract to get this page's ctag line number.
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*/
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if (ctag_tmp != 0ULL) {
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ctag_tmp = nvgpu_safe_sub_u64(ctag_tmp, page_size);
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}
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ctag_num = nvgpu_safe_cast_u64_to_u32(ctag_tmp /
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g->ops.fb.compression_page_size(g));
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(void)strcpy(ctag_str, "ctag=0x\0");
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str_len = (u32)strlen(ctag_str);
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(void)nvgpu_strnadd_u32(ctag_str + str_len, ctag_num,
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nvgpu_safe_sub_u32(31U, str_len), 16U);
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#endif
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(void)map_attrs_to_str(attrs_str, attrs);
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pte_dbg(g, attrs,
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"vm=%s "
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"PTE: i=%-4u size=%-2u | "
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"GPU %#-12llx phys %#-12llx "
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"pgsz: %3dkb perm=%-2s kind=%#02x APT=%-6s %-5s "
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"%s "
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"[0x%08x, 0x%08x]",
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vm_name,
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pd_idx, mmu_level_entry_size,
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virt_addr, phys_addr,
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page_size >> 10,
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perm_str,
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attrs->kind_v,
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aperture_str,
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attrs_str,
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ctag_str,
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pte_w[1], pte_w[0]);
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}
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