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57 lines
1.8 KiB
C
57 lines
1.8 KiB
C
/*
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* general thermal device structures & definitions
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*
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* Copyright (c) 2016-2020, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#ifndef NVGPU_THERM_THRMCHANNEL_H
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#define NVGPU_THERM_THRMCHANNEL_H
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#include <nvgpu/boardobjgrp_e32.h>
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#include <common/pmu/boardobj/boardobj.h>
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struct therm_channel {
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struct pmu_board_obj super;
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s16 scaling;
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s16 offset;
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s32 temp_min;
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s32 temp_max;
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};
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struct therm_channels {
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struct boardobjgrp_e32 super;
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};
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struct therm_channel_device {
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struct therm_channel super;
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u8 therm_dev_idx;
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u8 therm_dev_prov_idx;
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};
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struct therm_channel_get_status {
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struct pmu_board_obj super;
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u32 curr_temp;
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};
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int therm_channel_sw_setup(struct gk20a *g);
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int therm_channel_pmu_setup(struct gk20a *g);
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#endif /* NVGPU_THERM_THRMCHANNEL_H */
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