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ae44d384f3
MISRA Advisory Directive 4.5 states that identifiers in the same name space with overlapping visibility should be typographically unambiguous. The presence of both the roundup(x,y) and round_up(x,y) macros in the posix utils.h header incurs a violation of this rule. These macros were added to keep in sync with the linux kernel variants. However, there is a key distinction between how these two macros work in the linux kernel; roundup(x,y) can handle any y alignment while round_up(x,y) is intended to work only when y is a power-of-two. Passing a non-power-of-two alignment to round_up(x,y) results in an incorrect value being returned (silently). Because all current uses of roundup(x,y) and round_up(x,y) in nvgpu specify a y value that is a power-of-two and the underlying posix macro implementations assume as much, it is best to remove roundup(x,y) from nvgpu altogether to avoid any confusion. So this change converts all uses of roundup(x,y) to round_up(x,y). Jira NVGPU-3178 Change-Id: I0ee974d3e088fa704e251a38f6b7ada5a7600aec Signed-off-by: Scott Long <scottl@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/2271385 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com> Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com> Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
104 lines
3.2 KiB
C
104 lines
3.2 KiB
C
/*
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* GV11B FB
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*
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* Copyright (c) 2016-2020, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#include <nvgpu/dma.h>
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#include <nvgpu/log.h>
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#include <nvgpu/enabled.h>
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#include <nvgpu/gmmu.h>
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#include <nvgpu/barrier.h>
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#include <nvgpu/bug.h>
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#include <nvgpu/soc.h>
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#include <nvgpu/ptimer.h>
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#include <nvgpu/io.h>
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#include <nvgpu/utils.h>
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#include <nvgpu/timers.h>
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#include <nvgpu/fifo.h>
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#include <nvgpu/gk20a.h>
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#include <nvgpu/nvgpu_err.h>
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#include <nvgpu/ltc.h>
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#include <nvgpu/rc.h>
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#include <nvgpu/engines.h>
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#include "fb_gm20b.h"
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#include "fb_gp10b.h"
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#include "fb_gv11b.h"
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#include <nvgpu/hw/gv11b/hw_fb_gv11b.h>
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#ifdef CONFIG_NVGPU_COMPRESSION
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void gv11b_fb_cbc_configure(struct gk20a *g, struct nvgpu_cbc *cbc)
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{
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u32 compbit_base_post_divide;
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u64 compbit_base_post_multiply64;
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u64 compbit_store_iova;
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u64 compbit_base_post_divide64;
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#ifdef CONFIG_NVGPU_SIM
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if (nvgpu_is_enabled(g, NVGPU_IS_FMODEL)) {
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compbit_store_iova = nvgpu_mem_get_phys_addr(g,
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&cbc->compbit_store.mem);
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} else
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#endif
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{
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compbit_store_iova = nvgpu_mem_get_addr(g,
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&cbc->compbit_store.mem);
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}
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/* must be aligned to 64 KB */
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compbit_store_iova = round_up(compbit_store_iova, (u64)SZ_64K);
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compbit_base_post_divide64 = compbit_store_iova >>
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fb_mmu_cbc_base_address_alignment_shift_v();
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do_div(compbit_base_post_divide64, nvgpu_ltc_get_ltc_count(g));
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compbit_base_post_divide = u64_lo32(compbit_base_post_divide64);
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compbit_base_post_multiply64 = ((u64)compbit_base_post_divide *
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nvgpu_ltc_get_ltc_count(g))
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<< fb_mmu_cbc_base_address_alignment_shift_v();
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if (compbit_base_post_multiply64 < compbit_store_iova) {
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compbit_base_post_divide++;
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}
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if (g->ops.cbc.fix_config != NULL) {
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compbit_base_post_divide =
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g->ops.cbc.fix_config(g, compbit_base_post_divide);
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}
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nvgpu_writel(g, fb_mmu_cbc_base_r(),
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fb_mmu_cbc_base_address_f(compbit_base_post_divide));
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nvgpu_log(g, gpu_dbg_info | gpu_dbg_map_v | gpu_dbg_pte,
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"compbit base.pa: 0x%x,%08x cbc_base:0x%08x\n",
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(u32)(compbit_store_iova >> 32),
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(u32)(compbit_store_iova & U32_MAX),
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compbit_base_post_divide);
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nvgpu_log(g, gpu_dbg_fn, "cbc base %x",
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nvgpu_readl(g, fb_mmu_cbc_base_r()));
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cbc->compbit_store.base_hw = compbit_base_post_divide;
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}
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#endif
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