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359fc24aaf
Currently the vGPU engine management rewrites a lot of the common device agnostic engine management code. With the new top HAL parsing one device at a time, it is now more easily possible to tie the vGPU into the new common device framework by implementing the top HAL but with the vGPU engine list backend. This lets the vGPU inherit all the common engine and device management code. By doing so the vGPU HAL need only implement a trivial and simple HAL. This also gets us a step closer to merging all of the CE init code: logically it just iterates through all CE engines whatever they may be. The only reason this differs between chips is because of the swap from CE0-2 to LCEs in the Pascal generation. This could be abstracted by the unit code easily enough. Also, the pbdma_id for each engine has to be added to the device struct. Eventually this was going to happen anyway, since the device struct will soon replace the nvgpu_engine_info struct. It's a little bit of an abuse but might be worth it long term. If not, it should not be difficult to replace uses of dev->pbdma_id with a proper lookup of PBDMA ID based on the device info. JIRA NVGPU-5421 Change-Id: Ie8dcd3b0150184d58ca0f78940c2e7ca72994e64 Signed-off-by: Alex Waterman <alexw@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2351877 Tested-by: mobile promotions <svcmobile_promotions@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
111 lines
3.5 KiB
C
111 lines
3.5 KiB
C
/*
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* Copyright (c) 2015-2020, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#include <nvgpu/device.h>
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#include <nvgpu/engines.h>
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#include <nvgpu/log.h>
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#include <nvgpu/errno.h>
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#include <nvgpu/gk20a.h>
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#include <nvgpu/static_analysis.h>
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#include <nvgpu/hw/gp10b/hw_fifo_gp10b.h>
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#include "engines_gp10b.h"
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int gp10b_engine_init_ce_info(struct nvgpu_fifo *f)
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{
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struct gk20a *g = f->g;
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enum nvgpu_fifo_engine engine_enum;
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u32 i;
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u32 gr_runlist_id;
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u32 lce_num_entries = 0;
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bool found;
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gr_runlist_id = nvgpu_engine_get_gr_runlist_id(g);
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nvgpu_log_info(g, "gr_runlist_id: %d", gr_runlist_id);
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lce_num_entries = nvgpu_device_count(g, NVGPU_DEVTYPE_LCE);
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nvgpu_log_info(g, "lce_num_entries: %d", lce_num_entries);
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for (i = 0; i < lce_num_entries; i++) {
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const struct nvgpu_device *dev;
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struct nvgpu_device *dev_rw;
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struct nvgpu_engine_info *info;
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dev = nvgpu_device_get(g, NVGPU_DEVTYPE_LCE, i);
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if (dev == NULL) {
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nvgpu_err(g, "Failed to get LCE device %u", i);
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return -EINVAL;
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}
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dev_rw = (struct nvgpu_device *)dev;
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info = &g->fifo.engine_info[dev->engine_id];
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/*
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* vGPU consideration. Not present in older chips. See
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* nvgpu_engine_init_from_device_info() for more details in the
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* comments.
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*/
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if (g->ops.fifo.find_pbdma_for_runlist != NULL) {
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found = g->ops.fifo.find_pbdma_for_runlist(g,
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dev->runlist_id,
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&dev_rw->pbdma_id);
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if (!found) {
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nvgpu_err(g, "busted pbdma map");
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return -EINVAL;
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}
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}
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info->pbdma_id = dev->pbdma_id;
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engine_enum = nvgpu_engine_enum_from_dev(g, dev);
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/* GR and GR_COPY shares same runlist_id */
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if ((engine_enum == NVGPU_ENGINE_ASYNC_CE) &&
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(gr_runlist_id == dev->runlist_id)) {
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engine_enum = NVGPU_ENGINE_GRCE;
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}
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info->engine_enum = engine_enum;
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info->fault_id = dev->fault_id;
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info->intr_mask |= BIT32(dev->intr_id);
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info->reset_mask |= BIT32(dev->reset_id);
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info->runlist_id = dev->runlist_id;
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info->inst_id = dev->inst_id;
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info->pri_base = dev->pri_base;
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info->engine_id = dev->engine_id;
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/* engine_id starts from 0 to NV_HOST_NUM_ENGINES */
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f->active_engines_list[f->num_engines] = dev->engine_id;
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f->num_engines = nvgpu_safe_add_u32(f->num_engines, 1U);
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nvgpu_log_info(g, "gr info: engine_id %d runlist_id %d "
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"intr_id %d reset_id %d engine_type %d "
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"engine_enum %d inst_id %d",
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dev->engine_id,
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dev->runlist_id,
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dev->intr_id,
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dev->reset_id,
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dev->type,
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engine_enum,
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dev->inst_id);
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}
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return 0;
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}
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