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454cb1631b
Added new CE class(PASCAL_DMA_COPY_B) for gp106 and gp104. JIRA DNVGPU-25 Change-Id: I3c85e3ffdedf7594d41bf5c2fbebbf44addd1720 Signed-off-by: Lakshmanan M <lm@nvidia.com> Reviewed-on: http://git-master/r/1166709 Reviewed-by: Konsta Holtta <kholtta@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
113 lines
2.6 KiB
C
113 lines
2.6 KiB
C
/*
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* GP106 GPU GR
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*
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* Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*/
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#include "gk20a/gk20a.h" /* FERMI and MAXWELL classes defined here */
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#include "gk20a/gr_gk20a.h"
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#include "gm20b/gr_gm20b.h" /* for MAXWELL classes */
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#include "gp10b/gr_gp10b.h"
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#include "gr_gp106.h"
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#include "hw_gr_gp106.h"
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static bool gr_gp106_is_valid_class(struct gk20a *g, u32 class_num)
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{
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bool valid = false;
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switch (class_num) {
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case PASCAL_COMPUTE_A:
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case PASCAL_COMPUTE_B:
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case PASCAL_A:
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case PASCAL_B:
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case PASCAL_DMA_COPY_A:
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case PASCAL_DMA_COPY_B:
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valid = true;
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break;
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case MAXWELL_COMPUTE_B:
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case MAXWELL_B:
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case FERMI_TWOD_A:
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case KEPLER_DMA_COPY_A:
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case MAXWELL_DMA_COPY_A:
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valid = true;
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break;
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default:
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break;
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}
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gk20a_dbg_info("class=0x%x valid=%d", class_num, valid);
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return valid;
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}
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static u32 gr_gp106_pagepool_default_size(struct gk20a *g)
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{
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return gr_scc_pagepool_total_pages_hwmax_value_v();
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}
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static int gr_gp106_handle_sw_method(struct gk20a *g, u32 addr,
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u32 class_num, u32 offset, u32 data)
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{
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gk20a_dbg_fn("");
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if (class_num == PASCAL_COMPUTE_B) {
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switch (offset << 2) {
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case NVC0C0_SET_SHADER_EXCEPTIONS:
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gk20a_gr_set_shader_exceptions(g, data);
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break;
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default:
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goto fail;
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}
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}
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if (class_num == PASCAL_B) {
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switch (offset << 2) {
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case NVC097_SET_SHADER_EXCEPTIONS:
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gk20a_gr_set_shader_exceptions(g, data);
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break;
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case NVC097_SET_CIRCULAR_BUFFER_SIZE:
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g->ops.gr.set_circular_buffer_size(g, data);
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break;
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case NVC097_SET_ALPHA_CIRCULAR_BUFFER_SIZE:
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g->ops.gr.set_alpha_circular_buffer_size(g, data);
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break;
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default:
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goto fail;
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}
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}
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return 0;
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fail:
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return -EINVAL;
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}
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static void gr_gp106_cb_size_default(struct gk20a *g)
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{
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struct gr_gk20a *gr = &g->gr;
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if (!gr->attrib_cb_default_size)
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gr->attrib_cb_default_size = 0x800;
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gr->alpha_cb_default_size =
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gr_gpc0_ppc0_cbm_alpha_cb_size_v_default_v();
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}
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void gp106_init_gr(struct gpu_ops *gops)
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{
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gp10b_init_gr(gops);
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gops->gr.is_valid_class = gr_gp106_is_valid_class;
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gops->gr.pagepool_default_size = gr_gp106_pagepool_default_size;
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gops->gr.handle_sw_method = gr_gp106_handle_sw_method;
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gops->gr.cb_size_default = gr_gp106_cb_size_default;
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}
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