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bb51cf9ec6
Bug 200066741 As we are just getting out of reset and this reg is not written before, so we dont stand the risk of loosing any data Change-Id: Ifc1bcaa3c224038e4e2a47882a4523f7633cb660 Signed-off-by: Supriya <ssharatkumar@nvidia.com> Reviewed-on: http://git-master/r/715652 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
98 lines
2.7 KiB
C
98 lines
2.7 KiB
C
/*
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* GK20A priv ring
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*
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* Copyright (c) 2011-2014, NVIDIA CORPORATION. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <linux/delay.h> /* for mdelay */
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#include "gk20a.h"
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#include "hw_mc_gk20a.h"
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#include "hw_pri_ringmaster_gk20a.h"
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#include "hw_pri_ringstation_sys_gk20a.h"
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#include "hw_trim_gk20a.h"
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void gk20a_reset_priv_ring(struct gk20a *g)
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{
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u32 data = 0;
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if (tegra_platform_is_linsim())
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return;
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/* Skipping read and then writeback to this reg, as we are just getting
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* out of reset, and before this call, the reg is not written to*/
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data = set_field(data,
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trim_sys_gpc2clk_out_bypdiv_m(),
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trim_sys_gpc2clk_out_bypdiv_f(0));
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gk20a_writel(g, trim_sys_gpc2clk_out_r(), data);
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gk20a_reset(g, mc_enable_priv_ring_enabled_f());
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if (g->ops.clock_gating.slcg_priring_load_gating_prod)
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g->ops.clock_gating.slcg_priring_load_gating_prod(g,
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g->slcg_enabled);
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gk20a_writel(g,pri_ringmaster_command_r(),
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0x4);
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gk20a_writel(g, pri_ringstation_sys_decode_config_r(),
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0x2);
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gk20a_readl(g, pri_ringstation_sys_decode_config_r());
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}
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void gk20a_priv_ring_isr(struct gk20a *g)
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{
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u32 status0, status1;
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u32 cmd;
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s32 retry = 100;
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if (tegra_platform_is_linsim())
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return;
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status0 = gk20a_readl(g, pri_ringmaster_intr_status0_r());
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status1 = gk20a_readl(g, pri_ringmaster_intr_status1_r());
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gk20a_dbg_info("ringmaster intr status0: 0x%08x,"
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"status1: 0x%08x", status0, status1);
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if (status0 & (0x1 | 0x2 | 0x4)) {
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gk20a_reset_priv_ring(g);
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}
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cmd = gk20a_readl(g, pri_ringmaster_command_r());
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cmd = set_field(cmd, pri_ringmaster_command_cmd_m(),
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pri_ringmaster_command_cmd_ack_interrupt_f());
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gk20a_writel(g, pri_ringmaster_command_r(), cmd);
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do {
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cmd = pri_ringmaster_command_cmd_v(
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gk20a_readl(g, pri_ringmaster_command_r()));
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usleep_range(20, 40);
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} while (cmd != pri_ringmaster_command_cmd_no_cmd_v() && --retry);
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if (retry <= 0)
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gk20a_warn(dev_from_gk20a(g),
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"priv ringmaster cmd ack too many retries");
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status0 = gk20a_readl(g, pri_ringmaster_intr_status0_r());
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status1 = gk20a_readl(g, pri_ringmaster_intr_status1_r());
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gk20a_dbg_info("ringmaster intr status0: 0x%08x,"
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" status1: 0x%08x", status0, status1);
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}
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