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The use of the _THIS_IP_ macro in nvgpu introduces two separate MISRA Rule 11.6 violations. The first is when when the label address (which gcc generates as a void *) is cast to an unsigned long and the second is when that unsigned long is cast back to a void * in the timer and kmem code that track the value. Skipping the intermediate use of unsigned long eliminates these violations. To do this, references to _THIS_IP_ are replaced with a new (compliant) _NVGPU_GET_IP_ macro. JIRA NVGPU-895 : MISRA Rule 11.6 violations Change-Id: I5ea999d8e2b467257fa190b485fa971adcbd0a2b Signed-off-by: Scott Long <scottl@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1774531 Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Adeel Raza <araza@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
59 lines
1.7 KiB
C
59 lines
1.7 KiB
C
/*
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* Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#ifndef NVGPU_UTILS_H
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#define NVGPU_UTILS_H
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#include <nvgpu/types.h>
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static inline u32 u64_hi32(u64 n)
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{
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return (u32)((n >> 32) & ~(u32)0);
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}
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static inline u32 u64_lo32(u64 n)
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{
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return (u32)(n & ~(u32)0);
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}
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static inline u64 hi32_lo32_to_u64(u32 hi, u32 lo)
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{
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return (((u64)hi) << 32) | (u64)lo;
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}
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static inline u32 set_field(u32 val, u32 mask, u32 field)
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{
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return ((val & ~mask) | field);
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}
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static inline u32 get_field(u32 reg, u32 mask)
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{
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return (reg & mask);
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}
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/*
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* MISRA Rule 11.6 compliant IP address generator.
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*/
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#define _NVGPU_GET_IP_ ({ __label__ __here; __here: &&__here; })
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#endif /* NVGPU_UTILS_H */
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