mirror of
git://nv-tegra.nvidia.com/linux-nvgpu.git
synced 2025-12-24 02:22:34 +03:00
f55fd5dc8c
This patch introduces following relationships among various nvgpu objects to support multiple address spaces with subcontexts. IOCTLs setting the relationships are shown in the braces. nvgpu_tsg 1<---->n nvgpu_tsg_subctx (TSG_BIND_CHANNEL_EX) nvgpu_tsg 1<---->n nvgpu_gr_ctx_mappings (ALLOC_OBJ_CTX) nvgpu_tsg_subctx 1<---->1 nvgpu_gr_subctx (ALLOC_OBJ_CTX) nvgpu_tsg_subctx 1<---->n nvgpu_channel (TSG_BIND_CHANNEL_EX) nvgpu_gr_ctx_mappings 1<---->n nvgpu_gr_subctx (ALLOC_OBJ_CTX) nvgpu_gr_ctx_mappings 1<---->1 vm_gk20a (ALLOC_OBJ_CTX) On unbinding the channel, objects are deleted according to dependencies. Without subcontexts, gr_ctx buffers mappings are maintained in the struct nvgpu_gr_ctx. For subcontexts, they are maintained in the struct nvgpu_gr_subctx. Preemption buffer with index NVGPU_GR_CTX_PREEMPT_CTXSW and PM buffer with index NVGPU_GR_CTX_PM_CTX are to be mapped in all subcontexts when they are programmed from respective ioctls. Global GR context buffers are to be programmed only for VEID0. Based on the channel object class the state is patched in the patch buffer in every ALLOC_OBJ_CTX call unlike setting it for only first channel like before. PM and preemptions buffers programming is protected under TSG ctx_init_lock. tsg->vm is now removed. VM reference for gr_ctx buffers mappings is managed through gr_ctx or gr_subctx mappings object. For vGPU, gr_subctx and mappings objects are created to reference VMs for the gr_ctx lifetime. The functions nvgpu_tsg_subctx_alloc_gr_subctx and nvgpu_tsg_- subctx_setup_subctx_header sets up the subcontext struct header for native driver. The function nvgpu_tsg_subctx_alloc_gr_subctx is called from vgpu to manage the gr ctx mapping references. free_subctx is now done when unbinding channel considering references to the subcontext by other channels. It will unmap the buffers in native driver case. It will just release the VM reference in vgpu case. Note that TEGRA_VGPU_CMD_FREE_CTX_HEADER ioctl is not called by vgpu any longer as it would be taken care by native driver. Bug 3677982 Change-Id: Ia439b251ff452a49f8514498832e24d04db86d2f Signed-off-by: Sagar Kamble <skamble@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2718760 Reviewed-by: Scott Long <scottl@nvidia.com> Reviewed-by: Ankur Kishore <ankkishore@nvidia.com> GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
184 lines
6.3 KiB
C
184 lines
6.3 KiB
C
/*
|
|
* Copyright (c) 2022, NVIDIA CORPORATION. All rights reserved.
|
|
*
|
|
* Permission is hereby granted, free of charge, to any person obtaining a
|
|
* copy of this software and associated documentation files (the "Software"),
|
|
* to deal in the Software without restriction, including without limitation
|
|
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
|
* and/or sell copies of the Software, and to permit persons to whom the
|
|
* Software is furnished to do so, subject to the following conditions:
|
|
*
|
|
* The above copyright notice and this permission notice shall be included in
|
|
* all copies or substantial portions of the Software.
|
|
*
|
|
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
|
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
|
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
|
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
|
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
|
|
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
|
|
* DEALINGS IN THE SOFTWARE.
|
|
*/
|
|
#ifndef NVGPU_TSG_SUBCTX_H
|
|
#define NVGPU_TSG_SUBCTX_H
|
|
|
|
#include <nvgpu/types.h>
|
|
|
|
struct gk20a;
|
|
struct nvgpu_tsg;
|
|
struct nvgpu_tsg_subctx;
|
|
struct nvgpu_channel;
|
|
/**
|
|
* @brief Bind a channel to the TSG subcontext.
|
|
*
|
|
* @param tsg [in] Pointer to TSG struct.
|
|
* @param ch [in] Pointer to Channel struct.
|
|
*
|
|
* - Loop through the #subctx_list in #tsg to check if the subctx
|
|
* exists for the provided channel.
|
|
* - If it exists, validate the channel VM with subctx VM.
|
|
* - If validated, add the channel to the subctx #ch_list and exit.
|
|
* - Else allocate and initialize new subctx structure.
|
|
* - Add the channel to the subctx #ch_list and add subctx to the
|
|
* TSG #subctx_list.
|
|
*
|
|
* @return 0 for successful bind or if subctx support is disabled,
|
|
* < 0 for failure.
|
|
* @retval -EINVAL if channel VM doesn't match with subctx VM for provided
|
|
* subctx_id.
|
|
* @retval -ENOMEM if subctx allocation fails.
|
|
*/
|
|
int nvgpu_tsg_subctx_bind_channel(struct nvgpu_tsg *tsg,
|
|
struct nvgpu_channel *ch);
|
|
|
|
/**
|
|
* @brief Unbind a channel from the TSG subcontext.
|
|
*
|
|
* @param tsg [in] Pointer to TSG struct.
|
|
* @param ch [in] Pointer to Channel struct.
|
|
*
|
|
* - Validate that #subctx is allocated for the channel #ch.
|
|
* - Remove the channel from the subctx #ch_list.
|
|
* - If the subctx #ch_list is empty
|
|
* - Invoke g->ops.gr.setup.free_subctx to free the GR subcontext
|
|
* struct (and GR subcontext mappings struct).
|
|
* - Remove the subctx from the TSG #subctx_list.
|
|
* - Free the subctx memory. If this was the only active channel
|
|
* in the TSG this function will delete the objects in the
|
|
* sequence: mappings -> gr_subctx -> tsg_subctx
|
|
*/
|
|
void nvgpu_tsg_subctx_unbind_channel(struct nvgpu_tsg *tsg,
|
|
struct nvgpu_channel *ch);
|
|
|
|
/**
|
|
* @brief Allocate GR subcontext for a TSG subcontext.
|
|
*
|
|
* @param g [in] Pointer to gk20a struct.
|
|
* @param ch [in] Pointer to Channel struct.
|
|
*
|
|
* - Check if TSG subctx is allocated for the channel.
|
|
* - If not allocated, return error.
|
|
* - If allocated, and if GR subcontext is not allocated call
|
|
* #nvgpu_gr_subctx_alloc.
|
|
*
|
|
* @return 0 for successful allocation, < 0 for failure.
|
|
*/
|
|
int nvgpu_tsg_subctx_alloc_gr_subctx(struct gk20a *g, struct nvgpu_channel *ch);
|
|
|
|
/**
|
|
* @brief Allocate and map GR subcontext header for a TSG subcontext.
|
|
*
|
|
* @param g [in] Pointer to gk20a struct.
|
|
* @param ch [in] Pointer to Channel struct.
|
|
*
|
|
* - Check if TSG and GR subctx is allocated for the channel.
|
|
* - If not allocated, return error.
|
|
* - If allocated, setup subcontext header by calling
|
|
* #nvgpu_gr_subctx_setup_header.
|
|
*
|
|
* @return 0 for successful allocation, < 0 for failure.
|
|
*/
|
|
int nvgpu_tsg_subctx_setup_subctx_header(struct gk20a *g,
|
|
struct nvgpu_channel *ch);
|
|
|
|
/**
|
|
* @brief Get GR subcontext for a TSG subcontext.
|
|
*
|
|
* @param tsg_subctx [in] Pointer to TSG Subcontext struct.
|
|
*
|
|
* - Return #gr_subctx from #nvgpu_tsg_subctx.
|
|
*/
|
|
struct nvgpu_gr_subctx *nvgpu_tsg_subctx_get_gr_subctx(
|
|
struct nvgpu_tsg_subctx *tsg_subctx);
|
|
|
|
/**
|
|
* @brief Get id of a TSG subcontext.
|
|
*
|
|
* @param tsg_subctx [in] Pointer to TSG Subcontext struct.
|
|
*
|
|
* - Return #subctx_id from #nvgpu_tsg_subctx.
|
|
*/
|
|
u32 nvgpu_tsg_subctx_get_id(struct nvgpu_tsg_subctx *tsg_subctx);
|
|
|
|
/**
|
|
* @brief Allocate or get the mappings struct for the TSG subcontext.
|
|
*
|
|
* @param g [in] Pointer to GPU driver struct.
|
|
* @param tsg [in] Pointer to TSG struct.
|
|
* @param ch [in] Pointer to Channel struct.
|
|
*
|
|
* This function allocates the mappings struct for subcontext corresponding
|
|
* to given Channel's VM if not available already else returns the same.
|
|
* It adds the gr_subctx corresponding to the channel the mapping object's
|
|
* subctx_list.
|
|
*
|
|
* @return mappings struct in case of success, null in case of failure.
|
|
*/
|
|
struct nvgpu_gr_ctx_mappings *nvgpu_tsg_subctx_alloc_or_get_mappings(
|
|
struct gk20a *g,
|
|
struct nvgpu_tsg *tsg,
|
|
struct nvgpu_channel *ch);
|
|
|
|
#ifdef CONFIG_NVGPU_GFXP
|
|
/**
|
|
* @brief Program preemption buffer virtual addresses for all subcontexts.
|
|
*
|
|
* @param tsg_subctx [in] Pointer to TSG subcontext struct.
|
|
*
|
|
* - Checks if VEID0 mappings are available.
|
|
* - If available, program the preemption buffer virtual addresses
|
|
* (VEID0 VA and VA in subcontext VM) for all GR subcontexts'
|
|
* headers.
|
|
*/
|
|
void nvgpu_tsg_subctxs_set_preemption_buffer_va(
|
|
struct nvgpu_tsg_subctx *tsg_subctx);
|
|
|
|
/**
|
|
* @brief Clear preemption buffer virtual addresses for all subcontexts.
|
|
*
|
|
* @param tsg_subctx [in] Pointer to TSG subcontext struct.
|
|
*
|
|
* - Program the preemption buffer virtual addresses
|
|
* (VEID0 VA and VA in subcontext VM) for all GR subcontexts'
|
|
* headers to 0.
|
|
*/
|
|
void nvgpu_tsg_subctxs_clear_preemption_buffer_va(
|
|
struct nvgpu_tsg_subctx *tsg_subctx);
|
|
#endif /* CONFIG_NVGPU_GFXP */
|
|
|
|
#ifdef CONFIG_NVGPU_DEBUGGER
|
|
/**
|
|
* @brief Program PM buffer virtual addresses for all subcontexts.
|
|
*
|
|
* @param tsg [in] Pointer to TSG struct.
|
|
* @param set_pm_ctx_gpu_va [in] Indicates if PM ctx buffer GPU VA
|
|
* is to be programmed.
|
|
*
|
|
* - Program the PM buffer virtual address for all GR subcontexts' headers.
|
|
*/
|
|
void nvgpu_tsg_subctxs_set_pm_buffer_va(struct nvgpu_tsg *tsg,
|
|
bool set_pm_ctx_gpu_va);
|
|
#endif /* CONFIG_NVGPU_DEBUGGER */
|
|
|
|
#endif /* NVGPU_TSG_SUBCTX_H */
|