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Statically initialized nvgpu_posix_io_reg_space structures are used in test_fifo_setup_gv11b_reg_space to initialize register spaces. If fifo, TSG and channel unit tests run concurrently, the same register space structure can be registered multiple times for different GPU contexts. This results in list corruption or use of freed memory. Use allocated register spaces instead. Jira NVGPU-3943 Change-Id: I74c080f336e32149d2a378e2b15d37a2bd60ff71 Signed-off-by: Thomas Fleury <tfleury@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/2204062 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Debarshi Dutta <ddutta@nvidia.com> Reviewed-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-by: Bibek Basu <bbasu@nvidia.com>