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f95cb5f4f8
In order to maintain separate mappings of GR TSG and global context
buffers for different subcontexts, we need to separate the memory
struct and the mapping struct for the buffers. This patch moves
the mappings of all GR ctx buffers to new structure
nvgpu_gr_ctx_mappings.
This will be instantiated per subcontext in the upcoming patches.
Summary of changes:
1. Various context buffers were allocated and mapped separately.
All TSG context buffers are now stored in gr_ctx->mem[] array
since allocation and mapping is unified for them.
2. Mapping/unmapping and querying the GPU VA of the context
buffers is now handled in ctx_mappings unit. Structure
nvgpu_gr_ctx_mappings in nvgpu_gr_ctx holds the maps.
On ALLOC_OBJ_CTX this struct is instantiated and deleted
on free_gr_ctx.
3. Introduce mapping flags for TSG and global context buffers.
This is to map different buffers with different caching
attribute. Map all buffers as cacheable except
PRIV_ACCESS_MAP, RTV_CIRCULAR_BUFFER, FECS_TRACE, GR CTX
and PATCH ctx buffers. Map all buffers as privileged.
4. Wherever VM or GPU VA is passed in the obj_ctx allocation
functions, they are now replaced by nvgpu_gr_ctx_mappings.
5. free_gr_ctx API need not accept the VM as mappings struct
will hold the VM. mappings struct will be kept in gr_ctx.
6. Move preemption buffers allocation logic out of
nvgpu_gr_obj_ctx_set_graphics_preemption_mode.
7. set_preemption_mode and gr_gk20a_update_hwpm_ctxsw_mode
functions need update to ensure buffers are allocated
and mapped.
8. Keep the unit tests and documentation updated.
With these changes there is clear seggregation of allocation and
mapping of GR context buffers. This will simplify further change
to add multiple address spaces support. With multiple address
spaces in a TSG, subcontexts created after first subcontext
just need to map the buffers.
Bug 3677982
Change-Id: I3cd5f1311dd85aad1cf547da8fa45293fb7a7cb3
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2712222
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
164 lines
3.8 KiB
C
164 lines
3.8 KiB
C
/*
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* Copyright (c) 2019-2022, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#ifndef NVGPU_GR_CTX_PRIV_H
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#define NVGPU_GR_CTX_PRIV_H
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struct nvgpu_mem;
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/**
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* Patch context buffer descriptor structure.
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*
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* Pointer to this structure is maintained in #nvgpu_gr_ctx structure.
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*/
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struct patch_desc {
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/**
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* Count of entries written into patch context buffer.
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*/
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u32 data_count;
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};
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#ifdef CONFIG_NVGPU_GRAPHICS
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struct zcull_ctx_desc {
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u64 gpu_va;
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u32 ctx_sw_mode;
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};
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#endif
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#ifdef CONFIG_NVGPU_DEBUGGER
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struct pm_ctx_desc {
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u32 pm_mode;
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bool mapped;
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};
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#endif
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/**
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* GR context descriptor structure.
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*
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* This structure stores various properties of all GR context buffers.
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*/
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struct nvgpu_gr_ctx_desc {
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/**
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* Array to store all GR context buffer sizes.
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*/
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u32 size[NVGPU_GR_CTX_COUNT];
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#ifdef CONFIG_NVGPU_GRAPHICS
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bool force_preemption_gfxp;
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#endif
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#ifdef CONFIG_NVGPU_CILP
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bool force_preemption_cilp;
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#endif
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#ifdef CONFIG_DEBUG_FS
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bool dump_ctxsw_stats_on_channel_close;
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#endif
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};
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/**
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* Graphics context buffer structure.
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*
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* This structure stores all the properties of a graphics context
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* buffer. One graphics context is allocated per GPU Time Slice
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* Group (TSG).
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*/
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struct nvgpu_gr_ctx {
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/**
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* Context ID read from graphics context buffer.
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*/
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u32 ctx_id;
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/**
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* Flag to indicate if above context ID is valid or not.
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*/
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bool ctx_id_valid;
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/**
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* Array to store all GR context buffers.
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*/
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struct nvgpu_mem mem[NVGPU_GR_CTX_COUNT];
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/**
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* Cacheability flags for mapping the context buffers.
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*/
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u32 mapping_flags[NVGPU_GR_CTX_COUNT];
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/**
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* Pointer to structure that holds GPU mapping of context buffers.
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* These mappings will exist for the lifetime of TSG when the
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* subcontexts are not enabled.
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*/
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struct nvgpu_gr_ctx_mappings *mappings;
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/**
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* Patch context buffer descriptor struct.
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*/
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struct patch_desc patch_ctx;
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#ifdef CONFIG_NVGPU_GRAPHICS
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struct zcull_ctx_desc zcull_ctx;
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#endif
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#ifdef CONFIG_NVGPU_DEBUGGER
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struct pm_ctx_desc pm_ctx;
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#endif
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/**
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* Graphics preemption mode of the graphics context.
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*/
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u32 graphics_preempt_mode;
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/**
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* Compute preemption mode of the graphics context.
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*/
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u32 compute_preempt_mode;
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#ifdef CONFIG_NVGPU_NON_FUSA
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bool golden_img_loaded;
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#endif
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#ifdef CONFIG_NVGPU_CILP
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bool cilp_preempt_pending;
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#endif
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#ifdef CONFIG_NVGPU_DEBUGGER
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bool boosted_ctx;
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#endif
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/**
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* TSG identifier corresponding to the graphics context.
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*/
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u32 tsgid;
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#ifdef CONFIG_NVGPU_SM_DIVERSITY
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/** SM diversity configuration offset.
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* It is valid only if NVGPU_SUPPORT_SM_DIVERSITY support is true.
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* else input param is just ignored.
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* A valid offset starts from 0 to
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* (#gk20a.max_sm_diversity_config_count - 1).
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*/
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u32 sm_diversity_config;
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#endif
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};
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#endif /* NVGPU_GR_CTX_PRIV_H */
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