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f95cb5f4f8
In order to maintain separate mappings of GR TSG and global context
buffers for different subcontexts, we need to separate the memory
struct and the mapping struct for the buffers. This patch moves
the mappings of all GR ctx buffers to new structure
nvgpu_gr_ctx_mappings.
This will be instantiated per subcontext in the upcoming patches.
Summary of changes:
1. Various context buffers were allocated and mapped separately.
All TSG context buffers are now stored in gr_ctx->mem[] array
since allocation and mapping is unified for them.
2. Mapping/unmapping and querying the GPU VA of the context
buffers is now handled in ctx_mappings unit. Structure
nvgpu_gr_ctx_mappings in nvgpu_gr_ctx holds the maps.
On ALLOC_OBJ_CTX this struct is instantiated and deleted
on free_gr_ctx.
3. Introduce mapping flags for TSG and global context buffers.
This is to map different buffers with different caching
attribute. Map all buffers as cacheable except
PRIV_ACCESS_MAP, RTV_CIRCULAR_BUFFER, FECS_TRACE, GR CTX
and PATCH ctx buffers. Map all buffers as privileged.
4. Wherever VM or GPU VA is passed in the obj_ctx allocation
functions, they are now replaced by nvgpu_gr_ctx_mappings.
5. free_gr_ctx API need not accept the VM as mappings struct
will hold the VM. mappings struct will be kept in gr_ctx.
6. Move preemption buffers allocation logic out of
nvgpu_gr_obj_ctx_set_graphics_preemption_mode.
7. set_preemption_mode and gr_gk20a_update_hwpm_ctxsw_mode
functions need update to ensure buffers are allocated
and mapped.
8. Keep the unit tests and documentation updated.
With these changes there is clear seggregation of allocation and
mapping of GR context buffers. This will simplify further change
to add multiple address spaces support. With multiple address
spaces in a TSG, subcontexts created after first subcontext
just need to map the buffers.
Bug 3677982
Change-Id: I3cd5f1311dd85aad1cf547da8fa45293fb7a7cb3
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2712222
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
252 lines
9.2 KiB
C
252 lines
9.2 KiB
C
/*
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* Copyright (c) 2019-2022, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#ifndef UNIT_NVGPU_GR_SETUP_H
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#define UNIT_NVGPU_GR_SETUP_H
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#include <nvgpu/types.h>
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struct gk20a;
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struct unit_module;
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/** @addtogroup SWUTS-gr-setup
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* @{
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*
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* Software Unit Test Specification for common.gr.setup
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*/
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/**
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* Test specification for: test_gr_setup_alloc_obj_ctx.
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*
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* Description: This test helps to verify common.gr object context creation.
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*
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* Test Type: Feature, Boundary Value
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*
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* Equivalence classes:
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* Variable: class_num
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* - Valid : {0 - U32_MAX}
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* Range of "class_num" variable for nvgpu-rm is
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* 0xC3C0U (VOLTA_COMPUTE_A), 0xC3B5U (VOLTA_DMA_COPY_A),
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* 0xC36FU (VOLTA_CHANNEL_GPFIFO_A).
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* class_num range check is done in common.class unit.
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* Variable: flags
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* - Valid : {0 - U32_MAX}
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*
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* Targets: nvgpu_gr_setup_alloc_obj_ctx,
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* nvgpu_gr_obj_ctx_alloc,
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* nvgpu_gr_ctx_get_ctx_mem,
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* nvgpu_gr_ctx_set_tsgid,
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* nvgpu_gr_ctx_get_tsgid,
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* nvgpu_gr_ctx_mappings_get_global_ctx_va,
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* gops_gr_setup.alloc_obj_ctx,
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* nvgpu_gr_ctx_load_golden_ctx_image,
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* gm20b_ctxsw_prog_set_patch_addr,
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* gv11b_gr_init_commit_global_attrib_cb,
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* gm20b_gr_init_commit_global_attrib_cb,
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* gv11b_gr_init_commit_global_timeslice,
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* gv11b_gr_init_restore_stats_counter_bundle_data,
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* gv11b_gr_init_commit_cbes_reserve,
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* gv11b_gr_init_fe_go_idle_timeout,
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* gm20b_gr_init_override_context_reset,
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* gm20b_gr_init_pipe_mode_override,
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* gp10b_gr_init_commit_global_bundle_cb,
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* gm20b_gr_falcon_set_current_ctx_invalid,
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* gm20b_gr_falcon_get_fecs_current_ctx_data
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*
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* Input: #test_gr_init_setup_ready must have been executed successfully.
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*
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* Steps:
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* - Use stub functions for hals that use timeout and requires register update
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* within timeout loop.
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* - g->ops.mm.cache.l2_flush.
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* - g->ops.gr.init.fe_pwr_mode_force_on.
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* - g->ops.gr.init.wait_idle.
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* - g->ops.gr.falcon.ctrl_ctxsw.
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* - Set default golden image size.
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* - Allocate and bind channel and tsg.
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* - Start BVEC testing for variable class_num.
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* class_num is tested for range in common.class. In common.gr, stub out
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* the common.class HALs to perform independent range testing. Before
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* stubbing, save the valid initialization values for common.class HALs.
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* - Call g->ops.gr.setup.alloc_obj_ctx with input class_num at boundary
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* values - min boundary(0), max boundary(U32_MAX) and once with value
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* in valid range. g->ops.gr.setup.alloc_obj_ctx value should return
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* 0 as all class_num values are valid from common.gr perspective.
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* End BVEC testing for variable class_num by restoring the stubbed
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* common.class HALs.
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* - Start BVEC testing for variable flags.
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* - Call g->ops.gr.setup.alloc_obj_ctx with input variable flags at boundary
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* values - min boundary(0), max boundary(U32_MAX) and once with value
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* in valid range. g->ops.gr.setup.alloc_obj_ctx value should return
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* 0 as all flags values are valid from common.gr perspective.
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* End BVEC testing for variable flags.
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* - Call g->ops.gr.setup.alloc_obj_ctx with valid class_num -
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* VOLTA_DMA_COPY_A and VOLTA_COMPUTE_A.
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*
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* Output: Returns PASS if the steps above were executed successfully. FAIL
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* otherwise.
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*/
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int test_gr_setup_alloc_obj_ctx(struct unit_module *m,
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struct gk20a *g, void *args);
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/**
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* Test specification for: test_gr_setup_set_preemption_mode.
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*
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* Description: This test helps to verify set_preemption_mode.
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*
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* Test Type: Feature, Safety
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*
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* Targets: nvgpu_gr_setup_set_preemption_mode,
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* nvgpu_gr_obj_ctx_set_ctxsw_preemption_mode,
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* nvgpu_gr_ctx_check_valid_preemption_mode,
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* nvgpu_gr_obj_ctx_update_ctxsw_preemption_mode,
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* nvgpu_gr_ctx_get_compute_preemption_mode,
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* nvgpu_gr_ctx_set_preemption_modes,
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* nvgpu_gr_ctx_patch_write_begin,
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* nvgpu_gr_ctx_patch_write_end,
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* gp10b_gr_init_commit_global_cb_manager,
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* nvgpu_gr_ctx_patch_write,
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* gm20b_ctxsw_prog_get_patch_count,
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* gm20b_ctxsw_prog_set_patch_count,
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* gops_gr_init.get_default_preemption_modes,
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* gp10b_gr_init_get_default_preemption_modes,
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* gops_gr_setup.set_preemption_mode,
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* gp10b_ctxsw_prog_set_compute_preemption_mode_cta,
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* gops_gr_init.get_supported__preemption_modes,
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* gp10b_gr_init_get_supported_preemption_modes
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*
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* Input: #test_gr_init_setup_ready and #test_gr_setup_alloc_obj_ctx
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* must have been executed successfully.
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*
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* Steps:
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* - Call g->ops.gr.setup.set_preemption_mode
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*
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* Output: Returns PASS if the steps above were executed successfully. FAIL
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* otherwise.
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*/
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int test_gr_setup_set_preemption_mode(struct unit_module *m,
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struct gk20a *g, void *args);
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/**
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* Test specification for: test_gr_setup_free_obj_ctx.
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*
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* Description: Helps to verify common.gr object context cleanup.
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*
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* Test Type: Feature
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*
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* Targets: nvgpu_gr_setup_free_subctx,
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* nvgpu_gr_setup_free_gr_ctx,
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* gops_gr_setup.free_gr_ctx,
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* gops_gr_setup.free_subctx
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*
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* Input: #test_gr_init_setup_ready and #test_gr_setup_alloc_obj_ctx
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* must have been executed successfully.
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*
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* Steps:
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* - Call nvgpu_tsg_unbind_channel.
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* - Call nvgpu_channel_close.
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* - Call nvgpu_tsg_release.
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*
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* Output: Returns PASS if the steps above were executed successfully. FAIL
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* otherwise.
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*/
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int test_gr_setup_free_obj_ctx(struct unit_module *m,
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struct gk20a *g, void *args);
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/**
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* Test specification for: test_gr_setup_preemption_mode_errors.
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*
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* Description: Helps to verify error paths in
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* gops_gr_setup.set_preemption_mode call.
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*
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* Test Type: Error injection, Boundary value
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*
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* Equivalence classes:
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* Variable : graphics_preempt_mode
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* - Valid : {0}
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* - Invalid : {1 - U32_MAX}
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* Variable : compute_preempt_mode
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* - Valid : {0,2}
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* - Invalid : {3 - U32_MAX}
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*
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*
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* Targets: nvgpu_gr_setup_set_preemption_mode,
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* nvgpu_gr_obj_ctx_set_ctxsw_preemption_mode
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*
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* Input: #test_gr_init_setup_ready and #test_gr_setup_alloc_obj_ctx
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* must have been executed successfully.
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*
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* Steps:
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* - Verify various combinations of compute and graphics modes.
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* - Verify the error path by failing #nvgpu_preempt_channel.
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* - Verify the error path for NVGPU_INVALID_TSG_ID as ch->tsgid.
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* - Verify the error path for invalid ch->obj_class.
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*
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* Output: Returns PASS if the steps above were executed successfully. FAIL
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* otherwise.
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*/
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int test_gr_setup_preemption_mode_errors(struct unit_module *m,
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struct gk20a *g, void *args);
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/**
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* Test specification for: test_gr_setup_alloc_obj_ctx_error_injections.
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*
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* Description: Helps to verify error paths in
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* gops_gr_setup.alloc_obj_ctx call.
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*
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* Test Type: Error injection, Boundary values
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*
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* Targets: nvgpu_gr_setup_alloc_obj_ctx,
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* nvgpu_gr_subctx_alloc, nvgpu_gr_obj_ctx_alloc,
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* nvgpu_gr_obj_ctx_alloc_golden_ctx_image,
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* nvgpu_gr_obj_ctx_get_golden_image_size,
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* nvgpu_gr_obj_ctx_commit_global_ctx_buffers,
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* nvgpu_gr_ctx_set_patch_ctx_data_count,
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* nvgpu_gr_setup_free_subctx, nvgpu_gr_setup_free_gr_ctx,
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* gm20b_ctxsw_prog_hw_get_fecs_header_size
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*
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* Input: #test_gr_init_setup_ready must have been executed successfully.
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*
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* Steps:
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* - Negative Tests for Setup alloc failures
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* - Test-1 using invalid tsg, classobj and classnum.
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* - Test-2 error injection in subctx allocation call.
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* - Test-3 fail nvgpu_gr_obj_ctx_alloc by setting zero image size.
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* - Test-4 and Test-8 fail nvgpu_gr_obj_ctx_alloc_golden_ctx_image
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* by failing ctrl_ctsw.
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* - Test-5 Fail L2 flush for branch coverage.
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* - Test-6 Fake setup_free call for NULL checking.
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*
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* - Positive Tests
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* - Test-7 nvgpu_gr_setup_alloc_obj_ctx pass without TSG subcontexts.
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*
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* Output: Returns PASS if the steps above were executed successfully. FAIL
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* otherwise.
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*/
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int test_gr_setup_alloc_obj_ctx_error_injections(struct unit_module *m,
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struct gk20a *g, void *args);
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#endif /* UNIT_NVGPU_GR_SETUP_H */
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/**
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* @}
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*/
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