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ffed5095db
Add fifo sub-unit to common.fifo to handle init/deinit code and global support functions. Split init into: - nvgpu_channel_setup_sw - nvgpu_tsg_setup_sw - nvgpu_fifo_setup_sw - nvgpu_runlist_setup_sw - nvgpu_engine_setup_sw - nvgpu_userd_setup_sw - nvgpu_pbdma_setup_sw Split de-init into - nvgpu_channel_cleanup_sw - nvgpu_tsg_cleanup_sw - nvgpu_fifo_cleanup_sw - nvgpu_runlist_cleanup_sw - nvgpu_engine_cleanup_sw - nvgpu_userd_cleanup_sw - nvgpu_pbdma_cleanup_sw Added the following HALs - runlist.length_max - fifo.init_pbdma_info - fifo.userd_entry_size Last 2 HALs should be moved resp. to pbdma and userd sub-units, when available. Added vgpu implementation of above hals - vgpu_runlist_length_max - vgpu_userd_entry_size - vgpu_channel_count Use hals in vgpu_fifo_setup_sw. Jira NVGPU-1306 Change-Id: I954f56be724eee280d7b5f171b1790d33c810470 Signed-off-by: Thomas Fleury <tfleury@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/2029620 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
103 lines
2.8 KiB
C
103 lines
2.8 KiB
C
/*
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* Copyright (c) 2017-2019, NVIDIA CORPORATION. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef NVGPU_LINUX_CHANNEL_H
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#define NVGPU_LINUX_CHANNEL_H
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#include <linux/workqueue.h>
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#include <linux/dma-buf.h>
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#include <nvgpu/types.h>
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struct channel_gk20a;
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struct nvgpu_gpfifo;
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struct nvgpu_submit_gpfifo_args;
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struct nvgpu_channel_fence;
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struct gk20a_fence;
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struct fifo_profile_gk20a;
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struct nvgpu_os_linux;
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struct sync_fence;
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struct sync_timeline;
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struct nvgpu_channel_completion_cb {
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/*
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* Signal channel owner via a callback, if set, in job cleanup with
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* schedule_work. Means that something finished on the channel (perhaps
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* more than one job).
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*/
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void (*fn)(struct channel_gk20a *, void *);
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void *user_data;
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/* Make access to the two above atomic */
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struct nvgpu_spinlock lock;
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/* Per-channel async work task, cannot reschedule itself */
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struct work_struct work;
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};
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struct nvgpu_error_notifier {
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struct dma_buf *dmabuf;
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void *vaddr;
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struct nvgpu_notification *notification;
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struct nvgpu_mutex mutex;
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};
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/*
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* This struct contains fence_related data.
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* e.g. sync_timeline for sync_fences.
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*/
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struct nvgpu_os_fence_framework {
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struct sync_timeline *timeline;
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};
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struct nvgpu_usermode_bufs_linux {
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/*
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* Common low level info of these is stored in nvgpu_mems in
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* channel_gk20a; these hold lifetimes for the actual dmabuf and its
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* dma mapping.
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*/
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struct nvgpu_usermode_buf_linux {
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struct dma_buf *dmabuf;
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struct dma_buf_attachment *attachment;
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struct sg_table *sgt;
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} gpfifo, userd;
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};
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struct nvgpu_channel_linux {
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struct channel_gk20a *ch;
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struct nvgpu_os_fence_framework fence_framework;
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struct nvgpu_channel_completion_cb completion_cb;
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struct nvgpu_error_notifier error_notifier;
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struct dma_buf *cyclestate_buffer_handler;
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struct nvgpu_usermode_bufs_linux usermode;
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};
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u32 nvgpu_submit_gpfifo_user_flags_to_common_flags(u32 user_flags);
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int nvgpu_channel_init_support_linux(struct nvgpu_os_linux *l);
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void nvgpu_channel_remove_support_linux(struct nvgpu_os_linux *l);
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struct channel_gk20a *gk20a_open_new_channel_with_cb(struct gk20a *g,
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void (*update_fn)(struct channel_gk20a *, void *),
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void *update_fn_data,
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int runlist_id,
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bool is_privileged_channel);
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#endif
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