mirror of
git://nv-tegra.nvidia.com/linux-nvgpu.git
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f9cac0c64d
Remove all nvgpu_next files and move the code into corresponding nvgpu files. Merge nvgpu-next-*.yaml into nvgpu-.yaml files. Jira NVGPU-4771 Change-Id: I595311be3c7bbb4f6314811e68712ff01763801e Signed-off-by: Antony Clince Alex <aalex@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2547557 Reviewed-by: svc_kernel_abi <svc_kernel_abi@nvidia.com> Reviewed-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> GVS: Gerrit_Virtual_Submit Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
143 lines
3.9 KiB
C
143 lines
3.9 KiB
C
/*
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* Copyright (c) 2019-2021, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#ifndef ACR_BOOTSTRAP_H
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#define ACR_BOOTSTRAP_H
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#include "nvgpu_acr_interface.h"
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struct gk20a;
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struct nvgpu_acr;
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struct hs_acr;
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struct flcn_acr_region_prop_v0 {
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u32 start_addr;
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u32 end_addr;
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u32 region_id;
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u32 read_mask;
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u32 write_mask;
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u32 client_mask;
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};
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struct flcn_acr_regions_v0 {
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u32 no_regions;
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struct flcn_acr_region_prop_v0 region_props[NVGPU_FLCN_ACR_MAX_REGIONS];
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};
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struct flcn_acr_desc_v0 {
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union {
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u32 reserved_dmem[(LSF_BOOTSTRAP_OWNER_RESERVED_DMEM_SIZE/4)];
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u32 signatures[4];
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} ucode_reserved_space;
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/*Always 1st*/
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u32 wpr_region_id;
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u32 wpr_offset;
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u32 mmu_mem_range;
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struct flcn_acr_regions_v0 regions;
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u32 nonwpr_ucode_blob_size;
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u64 nonwpr_ucode_blob_start;
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};
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struct bin_hdr {
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/* 0x10de */
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u32 bin_magic;
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/* versioning of bin format */
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u32 bin_ver;
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/* Entire image size including this header */
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u32 bin_size;
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/*
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* Header offset of executable binary metadata,
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* start @ offset- 0x100 *
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*/
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u32 header_offset;
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/*
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* Start of executable binary data, start @
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* offset- 0x200
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*/
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u32 data_offset;
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/* Size of executable binary */
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u32 data_size;
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};
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struct acr_fw_header {
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u32 sig_dbg_offset;
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u32 sig_dbg_size;
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u32 sig_prod_offset;
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u32 sig_prod_size;
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u32 patch_loc;
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u32 patch_sig;
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u32 hdr_offset; /* This header points to acr_ucode_header_t210_load */
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u32 hdr_size; /* Size of above header */
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};
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/* ACR Falcon descriptor's */
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struct hs_acr {
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#define ACR_DEFAULT 0U
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#define ACR_AHESASC_NON_FUSA 1U
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#define ACR_ASB_NON_FUSA 2U
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#define ACR_AHESASC_FUSA 3U
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#define ACR_ASB_FUSA 4U
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u32 acr_type;
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/* ACR ucode */
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const char *acr_fw_name;
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const char *acr_code_name;
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const char *acr_data_name;
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const char *acr_manifest_name;
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struct nvgpu_firmware *code_fw;
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struct nvgpu_firmware *data_fw;
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struct nvgpu_firmware *manifest_fw;
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struct nvgpu_firmware *acr_fw;
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union{
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struct flcn_acr_desc_v0 *acr_dmem_desc_v0;
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struct flcn_acr_desc *acr_dmem_desc;
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};
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#if defined(CONFIG_NVGPU_NON_FUSA)
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struct nvgpu_mem acr_falcon2_sysmem_desc;
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struct flcn2_acr_desc acr_sysmem_desc;
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struct nvgpu_mem ls_pmu_desc;
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#endif
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/* Falcon used to execute ACR ucode */
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struct nvgpu_falcon *acr_flcn;
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void (*report_acr_engine_bus_err_status)(struct gk20a *g,
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u32 bar0_status, u32 error_type);
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int (*acr_engine_bus_err_status)(struct gk20a *g, u32 *bar0_status,
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u32 *error_type);
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bool (*acr_validate_mem_integrity)(struct gk20a *g);
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};
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int nvgpu_acr_wait_for_completion(struct gk20a *g, struct hs_acr *acr_desc,
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u32 timeout);
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int nvgpu_acr_bootstrap_hs_ucode(struct gk20a *g, struct nvgpu_acr *acr,
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struct hs_acr *acr_desc);
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#if defined(CONFIG_NVGPU_FALCON_NON_FUSA) && defined(CONFIG_NVGPU_HAL_NON_FUSA)
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int nvgpu_acr_bootstrap_hs_ucode_riscv(struct gk20a *g, struct nvgpu_acr *acr);
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#endif
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#endif /* ACR_BOOTSTRAP_H */
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