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3e43f92f21
Mass copy ga10b & ga100 sources from nvgpu-next repo. TOP COMMIT-ID: 98f530e6924c844a1bf46816933a7fe015f3cce1 Jira NVGPU-4771 Change-Id: Ibf7102e9208133f8ef3bd3a98381138d5396d831 Signed-off-by: Sagar Kadamati <skadamati@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2524817 Tested-by: mobile promotions <svcmobile_promotions@nvidia.com> Reviewed-by: svc_kernel_abi <svc_kernel_abi@nvidia.com> Reviewed-by: Debarshi Dutta <ddutta@nvidia.com> Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> Reviewed-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> GVS: Gerrit_Virtual_Submit
60 lines
1.9 KiB
C
60 lines
1.9 KiB
C
/*
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* Copyright (c) 2020, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#include <nvgpu/gk20a.h>
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#include <nvgpu/falcon.h>
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#include "common/acr/acr_priv.h"
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#include "common/acr/acr_sw_tu104.h"
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#include "acr_sw_ga100.h"
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static u32* ga100_get_versioned_sig(struct gk20a *g, struct nvgpu_acr *acr,
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u32 *sig, u32 *sig_size)
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{
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u32 ucode_version = 0U;
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u32 sig_size_words = 0U;
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u32 sig_idx = 0;
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nvgpu_log_fn(g, " ");
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g->ops.fuse.read_ucode_version(g, FALCON_ID_SEC2, &ucode_version);
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*sig_size = *sig_size/acr->num_of_sig;
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sig_idx = (!ucode_version) ? 1U : 0U;
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sig_size_words = *sig_size/4U;
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sig = sig + nvgpu_safe_mult_u32(sig_idx, sig_size_words);
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return sig;
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}
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void nvgpu_next_dgpu_acr_sw_init(struct gk20a *g, struct nvgpu_acr *acr)
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{
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nvgpu_log_fn(g, " ");
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acr->num_of_sig = 2U;
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nvgpu_tu104_acr_sw_init(g, acr);
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acr->get_versioned_sig = ga100_get_versioned_sig;
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}
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