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fa1b18c171
gv11b needs tsg release callback to release CE method buffer. Bug 2022929 Change-Id: I32e27a5fa49eb61b9c2fc72ea32034191a9be48e Signed-off-by: Richard Zhao <rizhao@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1611631 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Thomas Fleury <tfleury@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Aparna Das <aparnad@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
61 lines
2.3 KiB
C
61 lines
2.3 KiB
C
/*
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* Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef _FIFO_VGPU_H_
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#define _FIFO_VGPU_H_
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#include <nvgpu/types.h>
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struct gk20a;
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struct channel_gk20a;
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struct fifo_gk20a;
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struct tsg_gk20a;
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int vgpu_init_fifo_setup_hw(struct gk20a *g);
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void vgpu_channel_bind(struct channel_gk20a *ch);
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void vgpu_channel_unbind(struct channel_gk20a *ch);
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int vgpu_channel_alloc_inst(struct gk20a *g, struct channel_gk20a *ch);
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void vgpu_channel_free_inst(struct gk20a *g, struct channel_gk20a *ch);
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void vgpu_channel_enable(struct channel_gk20a *ch);
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void vgpu_channel_disable(struct channel_gk20a *ch);
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int vgpu_channel_setup_ramfc(struct channel_gk20a *ch, u64 gpfifo_base,
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u32 gpfifo_entries,
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unsigned long acquire_timeout, u32 flags);
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int vgpu_fifo_init_engine_info(struct fifo_gk20a *f);
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int vgpu_fifo_preempt_channel(struct gk20a *g, u32 chid);
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int vgpu_fifo_preempt_tsg(struct gk20a *g, u32 tsgid);
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int vgpu_fifo_update_runlist(struct gk20a *g, u32 runlist_id,
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u32 chid, bool add, bool wait_for_finish);
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int vgpu_fifo_wait_engine_idle(struct gk20a *g);
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int vgpu_fifo_set_runlist_interleave(struct gk20a *g,
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u32 id,
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bool is_tsg,
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u32 runlist_id,
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u32 new_level);
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int vgpu_channel_set_timeslice(struct channel_gk20a *ch, u32 timeslice);
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int vgpu_fifo_force_reset_ch(struct channel_gk20a *ch,
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u32 err_code, bool verbose);
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u32 vgpu_fifo_default_timeslice_us(struct gk20a *g);
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int vgpu_tsg_open(struct tsg_gk20a *tsg);
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void vgpu_tsg_release(struct tsg_gk20a *tsg);
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int vgpu_tsg_bind_channel(struct tsg_gk20a *tsg,
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struct channel_gk20a *ch);
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int vgpu_tsg_unbind_channel(struct channel_gk20a *ch);
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int vgpu_tsg_set_timeslice(struct tsg_gk20a *tsg, u32 timeslice);
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int vgpu_enable_tsg(struct tsg_gk20a *tsg);
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#endif
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