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7f79d647d6
We currently set "aggressive_destroy" flag to destroy sync object statically and for each sync object Move this flag to per-platform structure so that it can be set per-platform for all the sync objects Also, set the default value of this flag as "false" and set it to "true" once we have more than 64 channels in use Bug 200141116 Change-Id: I1bc271df4f468a4087a06a27c7289ee0ec3ef29c Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: http://git-master/r/822041 (cherry picked from commit 98741e7e88066648f4f14490c76b61dbff745103) Reviewed-on: http://git-master/r/835800 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
239 lines
6.8 KiB
C
239 lines
6.8 KiB
C
/*
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* drivers/video/tegra/host/gk20a/soc/platform_gk20a.h
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*
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* GK20A Platform (SoC) Interface
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*
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* Copyright (c) 2014-2015, NVIDIA CORPORATION. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*/
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#ifndef _GK20A_PLATFORM_H_
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#define _GK20A_PLATFORM_H_
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#include <linux/platform_device.h>
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#include <linux/pm_domain.h>
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#include <linux/dma-attrs.h>
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struct gk20a;
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struct channel_gk20a;
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struct gr_ctx_buffer_desc;
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struct gk20a_scale_profile;
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struct secure_page_buffer {
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void (*destroy)(struct platform_device *, struct secure_page_buffer *);
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size_t size;
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u64 iova;
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struct dma_attrs attrs;
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};
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struct gk20a_platform {
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#ifdef CONFIG_TEGRA_GK20A
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u32 syncpt_base;
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#endif
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/* Populated by the gk20a driver before probing the platform. */
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struct gk20a *g;
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/* Should be populated at probe. */
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bool can_railgate;
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/* Should be populated at probe. */
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bool has_syncpoints;
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/* flag to set sync destroy aggressiveness */
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bool aggressive_sync_destroy;
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/* Should be populated by probe. */
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struct dentry *debugfs;
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struct dentry *debugfs_alias;
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/* Clock configuration is stored here. Platform probe is responsible
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* for filling this data. */
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struct clk *clk[3];
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int num_clks;
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/* Reset control for device */
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struct reset_control *reset_control;
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/* Delay before rail gated */
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int railgate_delay;
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/* Delay before clock gated */
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int clockgate_delay;
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/* Second Level Clock Gating: true = enable false = disable */
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bool enable_slcg;
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/* Block Level Clock Gating: true = enable flase = disable */
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bool enable_blcg;
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/* Engine Level Clock Gating: true = enable flase = disable */
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bool enable_elcg;
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/* Engine Level Power Gating: true = enable flase = disable */
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bool enable_elpg;
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/* Adaptative ELPG: true = enable flase = disable */
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bool enable_aelpg;
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/* Timeout for per-channel watchdog (in mS) */
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u32 ch_wdt_timeout_ms;
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/* Enable SMMU bypass by default */
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bool bypass_smmu;
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/* Disable big page support */
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bool disable_bigpage;
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/*
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* gk20a_do_idle() API can take GPU either into rail gate or CAR reset
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* This flag can be used to force CAR reset case instead of rail gate
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*/
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bool force_reset_in_do_idle;
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/* Default big page size 64K or 128K */
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u32 default_big_page_size;
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/* Initialize the platform interface of the gk20a driver.
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*
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* The platform implementation of this function must
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* - set the power and clocks of the gk20a device to a known
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* state, and
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* - populate the gk20a_platform structure (a pointer to the
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* structure can be obtained by calling gk20a_get_platform).
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*
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* After this function is finished, the driver will initialise
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* pm runtime and genpd based on the platform configuration.
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*/
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int (*probe)(struct platform_device *dev);
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/* Second stage initialisation - called once all power management
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* initialisations are done.
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*/
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int (*late_probe)(struct platform_device *dev);
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/* Remove device after power management has been done
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*/
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int (*remove)(struct platform_device *dev);
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/* Poweron platform dependencies */
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int (*busy)(struct platform_device *dev);
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/* Powerdown platform dependencies */
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void (*idle)(struct platform_device *dev);
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/* This function is called to allocate secure memory (memory that the
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* CPU cannot see). The function should fill the context buffer
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* descriptor (especially fields destroy, sgt, size).
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*/
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int (*secure_alloc)(struct platform_device *dev,
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struct gr_ctx_buffer_desc *desc,
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size_t size);
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/* Function to allocate a secure buffer of PAGE_SIZE at probe time.
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* This is also helpful to trigger secure memory resizing
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* while GPU is off
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*/
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int (*secure_page_alloc)(struct platform_device *dev);
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struct secure_page_buffer secure_buffer;
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bool secure_alloc_ready;
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/* Device is going to be suspended */
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int (*suspend)(struct device *);
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/* Called to turn off the device */
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int (*railgate)(struct platform_device *dev);
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/* Called to turn on the device */
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int (*unrailgate)(struct platform_device *dev);
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struct mutex railgate_lock;
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/* Called to check state of device */
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bool (*is_railgated)(struct platform_device *dev);
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/* get supported frequency list */
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int (*get_clk_freqs)(struct platform_device *pdev,
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unsigned long **freqs, int *num_freqs);
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/* clk related supported functions */
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unsigned long (*clk_get_rate)(struct platform_device *pdev);
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long (*clk_round_rate)(struct platform_device *pdev,
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unsigned long rate);
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int (*clk_set_rate)(struct platform_device *pdev,
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unsigned long rate);
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/* Postscale callback is called after frequency change */
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void (*postscale)(struct platform_device *pdev,
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unsigned long freq);
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/* Pre callback is called before frequency change */
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void (*prescale)(struct platform_device *pdev);
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/* Devfreq governor name. If scaling is enabled, we request
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* this governor to be used in scaling */
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const char *devfreq_governor;
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/* Quality of service id. If this is set, the scaling routines
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* will register a callback to id. Each time we receive a new value,
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* the postscale callback gets called. */
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int qos_id;
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/* Called as part of debug dump. If the gpu gets hung, this function
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* is responsible for delivering all necessary debug data of other
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* hw units which may interact with the gpu without direct supervision
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* of the CPU.
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*/
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void (*dump_platform_dependencies)(struct platform_device *dev);
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/* Callbacks to assert/deassert GPU reset */
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int (*reset_assert)(struct platform_device *pdev);
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int (*reset_deassert)(struct platform_device *pdev);
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struct clk *clk_reset;
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struct dvfs_rail *gpu_rail;
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bool virtual_dev;
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#ifdef CONFIG_TEGRA_GR_VIRTUALIZATION
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u64 virt_handle;
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struct task_struct *intr_handler;
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#endif
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/* source frequency for ptimer in hz */
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u32 ptimer_src_freq;
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bool has_cde;
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};
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static inline struct gk20a_platform *gk20a_get_platform(
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struct platform_device *dev)
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{
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return (struct gk20a_platform *)platform_get_drvdata(dev);
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}
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extern struct gk20a_platform gk20a_generic_platform;
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#ifdef CONFIG_TEGRA_GK20A
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extern struct gk20a_platform gk20a_tegra_platform;
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extern struct gk20a_platform gm20b_tegra_platform;
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#ifdef CONFIG_TEGRA_GR_VIRTUALIZATION
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extern struct gk20a_platform vgpu_tegra_platform;
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#endif
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#endif
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static inline bool gk20a_platform_has_syncpoints(struct platform_device *dev)
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{
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struct gk20a_platform *p = gk20a_get_platform(dev);
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return p->has_syncpoints;
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}
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int gk20a_tegra_busy(struct platform_device *dev);
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void gk20a_tegra_idle(struct platform_device *dev);
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void gk20a_tegra_debug_dump(struct platform_device *pdev);
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#endif
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