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fbf219d8ba
-Renamed ACR structs for FUSA, ACR FUSA code has struct names ending with _v1 & ACR non-FUSA with _v0, removed _v1 for FUSA code to keep struct without any versioning for doxygen. -Renamed acr_blob_construct_v1.c/h to acr_blob_construct.c/h JIRA NVGPU-2516 Change-Id: Id2d5e48e8169ce59371c2b08d04c5a65ba94c685 Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/2218265 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
235 lines
6.7 KiB
C
235 lines
6.7 KiB
C
/*
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* Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#ifndef ACR_BLOB_CONSTRUCT_H
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#define ACR_BLOB_CONSTRUCT_H
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#include <nvgpu/falcon.h>
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#include <nvgpu/flcnif_cmn.h>
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#include "acr_falcon_bl.h"
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/*
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* Light Secure WPR Content Alignments
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*/
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#define LSF_WPR_HEADER_ALIGNMENT (256U)
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#define LSF_SUB_WPR_HEADER_ALIGNMENT (256U)
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#define LSF_LSB_HEADER_ALIGNMENT (256U)
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#define LSF_BL_DATA_ALIGNMENT (256U)
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#define LSF_BL_DATA_SIZE_ALIGNMENT (256U)
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#define LSF_BL_CODE_SIZE_ALIGNMENT (256U)
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#define LSF_DATA_SIZE_ALIGNMENT (256U)
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#define LSF_CODE_SIZE_ALIGNMENT (256U)
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#define LSF_UCODE_DATA_ALIGNMENT 4096U
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/*
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* Maximum WPR Header size
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*/
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#define LSF_WPR_HEADERS_TOTAL_SIZE_MAX \
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(ALIGN_UP(((u32)sizeof(struct lsf_wpr_header) * FALCON_ID_END), \
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LSF_WPR_HEADER_ALIGNMENT))
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#define LSF_LSB_HEADER_TOTAL_SIZE_MAX (\
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ALIGN_UP(sizeof(struct lsf_lsb_header), LSF_LSB_HEADER_ALIGNMENT))
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#ifdef CONFIG_NVGPU_DGPU
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/* Maximum SUB WPR header size */
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#define LSF_SUB_WPR_HEADERS_TOTAL_SIZE_MAX (ALIGN_UP( \
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(sizeof(struct lsf_shared_sub_wpr_header) * \
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LSF_SHARED_DATA_SUB_WPR_USE_CASE_ID_MAX), \
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LSF_SUB_WPR_HEADER_ALIGNMENT))
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/* MMU excepts sub_wpr sizes in units of 4K */
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#define SUB_WPR_SIZE_ALIGNMENT (4096U)
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/* Defined for 1MB alignment */
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#define SHIFT_4KB (12U)
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/* shared sub_wpr use case IDs */
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enum {
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LSF_SHARED_DATA_SUB_WPR_USE_CASE_ID_FRTS_VBIOS_TABLES = 1,
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LSF_SHARED_DATA_SUB_WPR_USE_CASE_ID_PLAYREADY_SHARED_DATA = 2
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};
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#define LSF_SHARED_DATA_SUB_WPR_USE_CASE_ID_MAX \
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LSF_SHARED_DATA_SUB_WPR_USE_CASE_ID_PLAYREADY_SHARED_DATA
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#define LSF_SHARED_DATA_SUB_WPR_USE_CASE_ID_INVALID (0xFFFFFFFFU)
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#define MAX_SUPPORTED_SHARED_SUB_WPR_USE_CASES \
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LSF_SHARED_DATA_SUB_WPR_USE_CASE_ID_MAX
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/* Static sizes of shared subWPRs */
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/* Minimum granularity supported is 4K */
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/* 1MB in 4K */
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#define LSF_SHARED_DATA_SUB_WPR_FRTS_VBIOS_TABLES_SIZE_IN_4K (0x100U)
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/* 4K */
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#define LSF_SHARED_DATA_SUB_WPR_PLAYREADY_SHARED_DATA_SIZE_IN_4K (0x1U)
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#endif
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/*Light Secure Bootstrap header related defines*/
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#define NV_FLCN_ACR_LSF_FLAG_LOAD_CODE_AT_0_FALSE 0U
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#define NV_FLCN_ACR_LSF_FLAG_LOAD_CODE_AT_0_TRUE BIT32(0)
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#define NV_FLCN_ACR_LSF_FLAG_DMACTL_REQ_CTX_FALSE 0U
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#define NV_FLCN_ACR_LSF_FLAG_DMACTL_REQ_CTX_TRUE BIT32(2)
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#define NV_FLCN_ACR_LSF_FLAG_FORCE_PRIV_LOAD_TRUE BIT32(3)
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#define NV_FLCN_ACR_LSF_FLAG_FORCE_PRIV_LOAD_FALSE 0U
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/*
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* Image Status Defines
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*/
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#define LSF_IMAGE_STATUS_NONE (0U)
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#define LSF_IMAGE_STATUS_COPY (1U)
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#define LSF_IMAGE_STATUS_VALIDATION_CODE_FAILED (2U)
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#define LSF_IMAGE_STATUS_VALIDATION_DATA_FAILED (3U)
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#define LSF_IMAGE_STATUS_VALIDATION_DONE (4U)
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#define LSF_IMAGE_STATUS_VALIDATION_SKIPPED (5U)
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#define LSF_IMAGE_STATUS_BOOTSTRAP_READY (6U)
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struct lsf_wpr_header {
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u32 falcon_id;
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u32 lsb_offset;
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u32 bootstrap_owner;
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u32 lazy_bootstrap;
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u32 bin_version;
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u32 status;
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};
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struct lsf_ucode_desc {
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u8 prd_keys[2][16];
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u8 dbg_keys[2][16];
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u32 b_prd_present;
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u32 b_dbg_present;
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u32 falcon_id;
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u32 bsupports_versioning;
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u32 version;
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u32 dep_map_count;
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u8 dep_map[FALCON_ID_END * 2 * 4];
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u8 kdf[16];
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};
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struct lsf_lsb_header {
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struct lsf_ucode_desc signature;
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u32 ucode_off;
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u32 ucode_size;
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u32 data_size;
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u32 bl_code_size;
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u32 bl_imem_off;
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u32 bl_data_off;
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u32 bl_data_size;
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u32 app_code_off;
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u32 app_code_size;
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u32 app_data_off;
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u32 app_data_size;
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u32 flags;
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};
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#define UCODE_NB_MAX_DATE_LENGTH 64U
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struct ls_falcon_ucode_desc {
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u32 descriptor_size;
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u32 image_size;
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u32 tools_version;
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u32 app_version;
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char date[UCODE_NB_MAX_DATE_LENGTH];
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u32 bootloader_start_offset;
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u32 bootloader_size;
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u32 bootloader_imem_offset;
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u32 bootloader_entry_point;
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u32 app_start_offset;
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u32 app_size;
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u32 app_imem_offset;
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u32 app_imem_entry;
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u32 app_dmem_offset;
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u32 app_resident_code_offset;
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u32 app_resident_code_size;
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u32 app_resident_data_offset;
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u32 app_resident_data_size;
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u32 nb_imem_overlays;
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u32 nb_dmem_overlays;
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struct {u32 start; u32 size; } load_ovl[64];
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u32 compressed;
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};
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struct flcn_ucode_img {
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u32 *data;
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struct ls_falcon_ucode_desc *desc;
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u32 data_size;
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struct lsf_ucode_desc *lsf_desc;
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};
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struct lsfm_managed_ucode_img {
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struct lsfm_managed_ucode_img *next;
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struct lsf_wpr_header wpr_header;
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struct lsf_lsb_header lsb_header;
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struct flcn_bl_dmem_desc bl_gen_desc;
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u32 bl_gen_desc_size;
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u32 full_ucode_size;
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struct flcn_ucode_img ucode_img;
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};
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#ifdef CONFIG_NVGPU_DGPU
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/*
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* LSF shared SubWpr Header
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*
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* use_case_id - Shared SubWpr use case ID (updated by nvgpu)
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* start_addr - start address of subWpr (updated by nvgpu)
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* size_4K - size of subWpr in 4K (updated by nvgpu)
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*/
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struct lsf_shared_sub_wpr_header {
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u32 use_case_id;
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u32 start_addr;
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u32 size_4K;
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};
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/*
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* LSFM SUB WPRs struct
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* pnext : Next entry in the list, NULL if last
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* sub_wpr_header : SubWpr Header struct
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*/
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struct lsfm_sub_wpr {
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struct lsfm_sub_wpr *pnext;
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struct lsf_shared_sub_wpr_header sub_wpr_header;
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};
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#endif
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struct ls_flcn_mgr {
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u16 managed_flcn_cnt;
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u32 wpr_size;
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struct lsfm_managed_ucode_img *ucode_img_list;
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#ifdef CONFIG_NVGPU_DGPU
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u16 managed_sub_wpr_count;
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struct lsfm_sub_wpr *psub_wpr_list;
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#endif
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};
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int nvgpu_acr_prepare_ucode_blob(struct gk20a *g);
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#ifdef CONFIG_NVGPU_LS_PMU
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int nvgpu_acr_lsf_pmu_ucode_details(struct gk20a *g, void *lsf_ucode_img);
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#endif
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int nvgpu_acr_lsf_fecs_ucode_details(struct gk20a *g, void *lsf_ucode_img);
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int nvgpu_acr_lsf_gpccs_ucode_details(struct gk20a *g, void *lsf_ucode_img);
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#ifdef CONFIG_NVGPU_DGPU
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int nvgpu_acr_lsf_sec2_ucode_details(struct gk20a *g, void *lsf_ucode_img);
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#endif
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#endif /* ACR_BLOB_CONSTRUCT_H */
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