Files
linux-nvgpu/drivers/gpu/nvgpu/gk20a/mc_gk20a.h
Terje Bergstrom fc724baa4b gpu: nvgpu: Add MC HAL is_intr1_pending
Add MC HAL is_intr1_pending. At the same time introduce nvgpu_unit
that is passed as parameter to is_intr1_pending. The API is passed
contents of intr1 register and an engine number, and returns true
if there's an interrupt pending for the engine.

JIRA NVGPU-26

Change-Id: I8e6363dd78572f8e41dbab2b258036ed168b6f75
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/1497870
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2017-06-07 20:06:55 -07:00

37 lines
1.4 KiB
C

/*
* Copyright (c) 2014-2017, NVIDIA CORPORATION. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*/
#ifndef MC_GK20A_H
#define MC_GK20A_H
struct gk20a;
void gk20a_init_mc(struct gpu_ops *gops);
void mc_gk20a_intr_enable(struct gk20a *g);
void mc_gk20a_intr_unit_config(struct gk20a *g, bool enable,
bool is_stalling, u32 mask);
void mc_gk20a_isr_stall(struct gk20a *g);
u32 mc_gk20a_intr_stall(struct gk20a *g);
void mc_gk20a_intr_stall_pause(struct gk20a *g);
void mc_gk20a_intr_stall_resume(struct gk20a *g);
irqreturn_t mc_gk20a_isr_nonstall(struct gk20a *g);
irqreturn_t mc_gk20a_intr_thread_stall(struct gk20a *g);
void mc_gk20a_intr_thread_nonstall(struct gk20a *g, u32 intr);
void mc_gk20a_nonstall_cb(struct work_struct *work);
void gk20a_mc_enable(struct gk20a *g, u32 units);
void gk20a_mc_disable(struct gk20a *g, u32 units);
void gk20a_mc_reset(struct gk20a *g, u32 units);
u32 gk20a_mc_boot_0(struct gk20a *g, u32 *arch, u32 *impl, u32 *rev);
bool mc_gk20a_is_intr1_pending(struct gk20a *g,
enum nvgpu_unit unit, u32 mc_intr_1);
#endif