mirror of
git://nv-tegra.nvidia.com/linux-nvgpu.git
synced 2025-12-24 10:34:43 +03:00
e5824d8014
- update gp106 pg engine init/list/features HALs to support MS engine - Added defines & interface for lpwr tables read from vbios. - lpwr module which reads idx/gr/ms table from vbios to map rppg/mscg support with respective p-state - lpwr module public functions to control lpwr features enable/disable mscg/rppg & mclk-change request whenever change in mclk-change parameters - lpwr public functions to know rppg/mscg support for requested pstate, - added mutex t prevent PG transition while arbiter executes pstate transition - nvgpu_clk_arb_get_current_pstate() of clk arbiter to get current pstate JIRA DNVGPU-71 Change-Id: Ifcd640cc19ef630be1e2a9ba07ec84023d8202a0 Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-on: http://git-master/r/1247553 (cherry picked from commit 8a441dea2410e1b5196ef24e56a7768b6980e46b) Reviewed-on: http://git-master/r/1270989 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
67 lines
2.8 KiB
C
67 lines
2.8 KiB
C
/*
|
|
* Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved.
|
|
*
|
|
* This program is free software; you can redistribute it and/or modify it
|
|
* under the terms and conditions of the GNU General Public License,
|
|
* version 2, as published by the Free Software Foundation.
|
|
*
|
|
* This program is distributed in the hope it will be useful, but WITHOUT
|
|
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
|
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
|
* more details.
|
|
*/
|
|
#ifndef _PERF_H_
|
|
#define _PERF_H_
|
|
|
|
#include "vfe_equ.h"
|
|
#include "vfe_var.h"
|
|
#include "pstate/pstate.h"
|
|
#include "gk20a/gk20a.h"
|
|
#include "volt/volt.h"
|
|
#include "lpwr/lpwr.h"
|
|
|
|
#define CTRL_PERF_VFE_VAR_TYPE_INVALID 0x00
|
|
#define CTRL_PERF_VFE_VAR_TYPE_DERIVED 0x01
|
|
#define CTRL_PERF_VFE_VAR_TYPE_DERIVED_PRODUCT 0x02
|
|
#define CTRL_PERF_VFE_VAR_TYPE_DERIVED_SUM 0x03
|
|
#define CTRL_PERF_VFE_VAR_TYPE_SINGLE 0x04
|
|
#define CTRL_PERF_VFE_VAR_TYPE_SINGLE_FREQUENCY 0x05
|
|
#define CTRL_PERF_VFE_VAR_TYPE_SINGLE_SENSED 0x06
|
|
#define CTRL_PERF_VFE_VAR_TYPE_SINGLE_SENSED_FUSE 0x07
|
|
#define CTRL_PERF_VFE_VAR_TYPE_SINGLE_SENSED_TEMP 0x08
|
|
#define CTRL_PERF_VFE_VAR_TYPE_SINGLE_VOLTAGE 0x09
|
|
|
|
#define CTRL_PERF_VFE_VAR_SINGLE_OVERRIDE_TYPE_NONE 0x00
|
|
#define CTRL_PERF_VFE_VAR_SINGLE_OVERRIDE_TYPE_VALUE 0x01
|
|
#define CTRL_PERF_VFE_VAR_SINGLE_OVERRIDE_TYPE_OFFSET 0x02
|
|
#define CTRL_PERF_VFE_VAR_SINGLE_OVERRIDE_TYPE_SCALE 0x03
|
|
|
|
#define CTRL_PERF_VFE_EQU_TYPE_INVALID 0x00
|
|
#define CTRL_PERF_VFE_EQU_TYPE_COMPARE 0x01
|
|
#define CTRL_PERF_VFE_EQU_TYPE_MINMAX 0x02
|
|
#define CTRL_PERF_VFE_EQU_TYPE_QUADRATIC 0x03
|
|
|
|
#define CTRL_PERF_VFE_EQU_OUTPUT_TYPE_UNITLESS 0x00
|
|
#define CTRL_PERF_VFE_EQU_OUTPUT_TYPE_FREQ_MHZ 0x01
|
|
#define CTRL_PERF_VFE_EQU_OUTPUT_TYPE_VOLT_UV 0x02
|
|
#define CTRL_PERF_VFE_EQU_OUTPUT_TYPE_VF_GAIN 0x03
|
|
#define CTRL_PERF_VFE_EQU_OUTPUT_TYPE_VOLT_DELTA_UV 0x04
|
|
|
|
#define CTRL_PERF_VFE_EQU_QUADRATIC_COEFF_COUNT 0x03
|
|
|
|
#define CTRL_PERF_VFE_EQU_COMPARE_FUNCTION_EQUAL 0x00
|
|
#define CTRL_PERF_VFE_EQU_COMPARE_FUNCTION_GREATER_EQ 0x01
|
|
#define CTRL_PERF_VFE_EQU_COMPARE_FUNCTION_GREATER 0x02
|
|
|
|
struct perf_pmupstate {
|
|
struct vfe_vars vfe_varobjs;
|
|
struct vfe_equs vfe_equobjs;
|
|
struct pstates pstatesobjs;
|
|
struct obj_volt volt;
|
|
struct obj_lwpr lpwr;
|
|
};
|
|
|
|
u32 perf_pmu_vfe_load(struct gk20a *g);
|
|
|
|
#endif
|