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80d03f34f7
Background: In Hypervisor mode dGPU device is configured in pass through mode for the Guest (QNX/Linux). GMMU programming is handled by the guest which converts a mapped buffer's GVA into SGLes in IPA (Intermediate/Guest Physical address) which is then translated into PA (Acutual Physical address) and programs the GMMU PTEes with correct GVA to PA mapping. Incase of the vgpu this work is delegated to the RM server which takes care of the GMMU programming and IPA to PA conversion. Problem: The current GMMU mapping logic in the guest assumes that PA range is continuous over a given IPA range. Hence, it doesn't account for holes being present in the PA range. But this is not the case, a continous IPA range can be mapped to dis-contiguous PA ranges. In this situation the mapping logic sets up GMMU PTEes ignoring the holes in physical memory and creates GVA => PA mapping which intrudes into the PA ranges which are reserved. This results in memory being corrupted. This change takes into account holes being present in a given PA range and for a given IPA range it also identifies the discontiguous PA ranges and sets up the PTE's appropriately. Bug 200451447 Jira VQRM-5069 Change-Id: I354d984f6c44482e4576a173fce1e90ab52283ac Signed-off-by: aalex <aalex@nvidia.com> Signed-off-by: Antony Clince Alex <aalex@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1850972 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
130 lines
3.5 KiB
C
130 lines
3.5 KiB
C
/*
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* Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*/
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#include <soc/tegra/chip-id.h>
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#include <soc/tegra/fuse.h>
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#include <soc/tegra/tegra_bpmp.h>
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#ifdef CONFIG_TEGRA_HV_MANAGER
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#include <soc/tegra/virt/syscalls.h>
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#endif
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#include <nvgpu/soc.h>
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#include "os_linux.h"
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#include "platform_gk20a.h"
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bool nvgpu_platform_is_silicon(struct gk20a *g)
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{
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return tegra_platform_is_silicon();
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}
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bool nvgpu_platform_is_simulation(struct gk20a *g)
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{
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return tegra_platform_is_vdk();
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}
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bool nvgpu_platform_is_fpga(struct gk20a *g)
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{
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return tegra_platform_is_fpga();
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}
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bool nvgpu_is_hypervisor_mode(struct gk20a *g)
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{
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return is_tegra_hypervisor_mode();
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}
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bool nvgpu_is_bpmp_running(struct gk20a *g)
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{
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return tegra_bpmp_running();
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}
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bool nvgpu_is_soc_t194_a01(struct gk20a *g)
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{
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return ((tegra_get_chip_id() == TEGRA194 &&
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tegra_chip_get_revision() == TEGRA194_REVISION_A01) ?
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true : false);
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}
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#ifdef CONFIG_TEGRA_HV_MANAGER
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/* When nvlink is enabled on dGPU, we need to use physical memory addresses.
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* There is no SMMU translation. However, the device initially enumerates as a
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* PCIe device. As such, when allocation memory for this PCIe device, the DMA
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* framework ends up allocating memory using SMMU (if enabled in device tree).
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* As a result, when we switch to nvlink, we need to use underlying physical
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* addresses, even if memory mappings exist in SMMU.
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* In addition, when stage-2 SMMU translation is enabled (for instance when HV
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* is enabled), the addresses we get from dma_alloc are IPAs. We need to
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* convert them to PA.
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*/
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static u64 nvgpu_tegra_hv_ipa_pa(struct gk20a *g, u64 ipa, u64 *pa_len)
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{
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struct device *dev = dev_from_gk20a(g);
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struct gk20a_platform *platform = gk20a_get_platform(dev);
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struct hyp_ipa_pa_info info;
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int err;
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u64 pa = 0ULL;
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err = hyp_read_ipa_pa_info(&info, platform->vmid, ipa);
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if (err < 0) {
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/* WAR for bug 2096877
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* hyp_read_ipa_pa_info only looks up RAM mappings.
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* assume one to one IPA:PA mapping for syncpt aperture
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*/
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u64 start = g->syncpt_unit_base;
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u64 end = g->syncpt_unit_base + g->syncpt_unit_size;
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if ((ipa >= start) && (ipa < end)) {
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pa = ipa;
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nvgpu_log(g, gpu_dbg_map_v,
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"ipa=%llx vmid=%d -> pa=%llx (SYNCPT)\n",
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ipa, platform->vmid, pa);
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} else {
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nvgpu_err(g, "ipa=%llx translation failed vmid=%u err=%d",
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ipa, platform->vmid, err);
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}
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} else {
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pa = info.base + info.offset;
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if (pa_len != NULL) {
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/*
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* Update the size of physical memory chunk after the
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* specified offset.
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*/
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*pa_len = info.size - info.offset;
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}
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nvgpu_log(g, gpu_dbg_map_v,
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"ipa=%llx vmid=%d -> pa=%llx "
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"base=%llx offset=%llx size=%llx\n",
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ipa, platform->vmid, pa, info.base,
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info.offset, info.size);
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}
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return pa;
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}
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#endif
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int nvgpu_init_soc_vars(struct gk20a *g)
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{
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#ifdef CONFIG_TEGRA_HV_MANAGER
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struct device *dev = dev_from_gk20a(g);
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struct gk20a_platform *platform = gk20a_get_platform(dev);
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int err;
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if (nvgpu_is_hypervisor_mode(g)) {
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err = hyp_read_gid(&platform->vmid);
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if (err) {
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nvgpu_err(g, "failed to read vmid");
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return err;
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}
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platform->phys_addr = nvgpu_tegra_hv_ipa_pa;
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}
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#endif
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return 0;
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}
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