diff --git a/commitFile.txt b/commitFile.txt index 3c4f573..6ba1361 100644 --- a/commitFile.txt +++ b/commitFile.txt @@ -70,7 +70,7 @@ bd2e4a6102432d4ac1faf92b5d3db29e9e3cfafc - src/nvidia-modeset/src/nvkms-utils.c fd64ffbcc1efd446fb3352ceaa8bd4221b23a1d2 - src/nvidia-modeset/src/nvkms-modeset.c 3e723edf2a0a2f4f93032feb4aeaaf7fd0acddfa - src/nvidia-modeset/src/g_nvkms-evo-states.c 2fabe1c14116a2b07f24d01710394ee84a6e3914 - src/nvidia-modeset/src/nvkms-3dvision.c -488724910d9a3bf530303a4fa0889983d11ce5c0 - src/nvidia-modeset/src/nvkms-hdmi.c +eb99e694dc088194091e33ed73c01b745c3b939e - src/nvidia-modeset/src/nvkms-hdmi.c 761c8540278a1ffb9fe4aa0adb1b4ee95524787a - src/nvidia-modeset/src/nvkms-hal.c 54b41301663dc9fdc45d24c7a43ad4a980821f9d - src/nvidia-modeset/src/nvkms-attributes.c 3261fd9a1eb14f7f3fb0917757b1e2704d4abbd2 - src/nvidia-modeset/src/nvkms-hw-states.c @@ -85,13 +85,13 @@ f754a27436fd1e1fa103de6110224c21ad7ea9f4 - src/nvidia-modeset/src/nvkms-pow.c 9a8746ee4a4e772b8ac13f06dc0de8a250fdb4c7 - src/nvidia-modeset/src/nvkms-ctxdma.c 403e6dbff0a607c2aecf3204c56633bd7b612ae2 - src/nvidia-modeset/src/nvkms-stereo.c da726d20eea99a96af4c10aace88f419e8ee2a34 - src/nvidia-modeset/src/nvkms-event.c -b890da1d428f30483d6f69e662218f19c074d011 - src/nvidia-modeset/src/nvkms-evo3.c +96296baa35ea2367f1fd6ee2c99fa0107c126849 - src/nvidia-modeset/src/nvkms-evo3.c c799d52bdc792efc377fb5cd307b0eb445c44d6a - src/nvidia-modeset/src/nvkms-cursor2.c b7232f4b4b8f0d4c395c241c451fc17b6ab84d7f - src/nvidia-modeset/src/nvkms-evo.c 6f2eb25d57d2dc3c1e5db869cfbdf556878d3332 - src/nvidia-modeset/src/nvkms-console-restore.c 94e9c19b7b6a5e56fd46b0885e7dd6fe698fe2df - src/nvidia-modeset/src/nvkms-prealloc.c bf1b007fceaa1c38771f9e7d1130f9c0c3eddd80 - src/nvidia-modeset/src/nvkms-lut.c -e13960662d872f84dd77f36f778aee0521b4ff54 - src/nvidia-modeset/src/nvkms-modepool.c +933829ff39c6d1fe41bd82a5af177f5059b4b69e - src/nvidia-modeset/src/nvkms-modepool.c b13bd89b5ac60ceab56e9c2398cf7668375ab7ad - src/nvidia-modeset/src/nvkms-flip.c 9fea40b7b55d6ebf3f73b5d469751c873ffbe7c0 - src/nvidia-modeset/src/nvkms-dma.c df59641109db4529eed62cf156b1815a3e67ba05 - src/nvidia-modeset/src/nvkms-vrr.c @@ -646,7 +646,7 @@ eefa27872e4acde78a18211b8ab51bc5436b6cfe - src/nvidia/generated/g_nv_debug_dump_ 3b08d4bb1612bb193cd2f26229b119cc43284879 - src/nvidia/generated/g_rs_server_nvoc.h 73a37ad59b9b13b61eb944748b6c2ba3cad7b630 - src/nvidia/generated/g_traceable_nvoc.h 19d73b04597bca6d3a7dd82d327e6cbf4a591a65 - src/nvidia/generated/g_eng_state_nvoc.c -0eb34617fea0cc6843d317ba7cea287483e39703 - src/nvidia/generated/rmconfig.h +d2a8f1901d17c711f0f40dc32289ede7d9b440c7 - src/nvidia/generated/rmconfig.h 17c69e14076324c230bbe68b55141089c1f4d10e - src/nvidia/generated/g_os_desc_mem_nvoc.h 1268ee54592c8ae1078b72bfaff882549efbcd3c - src/nvidia/generated/g_disp_capabilities_nvoc.c bdb198b18c700dc396f73191a8e696d106a1f716 - src/nvidia/generated/g_resource_nvoc.h @@ -664,7 +664,7 @@ a97bf85ce6681aae086e0415aecaebf0208bfebb - src/nvidia/generated/g_tmr_nvoc.h 31270057a91fcd2dc7dbf1abed9e3f67d8db1787 - src/nvidia/generated/g_rmconfig_private.h e181d568b36f4d6e717d6d26c7bbe4b4ed968f4f - src/nvidia/generated/g_gpu_mgmt_api_nvoc.c 3b0e038829647cfe0d8807579db33416a420d1d2 - src/nvidia/generated/g_chips2halspec.h -4302502637f5c4146cb963801258444f2d8173e1 - src/nvidia/generated/g_allclasses.h +bc3759a264528b7ab329e6813cdf37aeedf86279 - src/nvidia/generated/g_allclasses.h 61cb019a28b25479d65022226623be2d20f32429 - src/nvidia/generated/g_nv_name_released.h 7f89931ecb53fb0b88da1be5489fe50e3d7897c3 - src/nvidia/generated/g_resserv_nvoc.h ac3965eea078f1998c3a3041f14212578682e599 - src/nvidia/generated/g_vaspace_nvoc.c @@ -673,19 +673,20 @@ a44899c21c77899b3b8deb7b2613b16841bbf397 - src/nvidia/generated/g_gpu_mgr_nvoc.c 67df2bc381609f290f173ea73f3e8125ac073888 - src/nvidia/generated/g_gpu_mgmt_api_nvoc.h 0e15fddc0426c42f3d22e5cb5609b5193adb7145 - src/nvidia/generated/g_standard_mem_nvoc.h 0a6b27d74e5e4ba872d77bfd369ddb5772abd8f8 - src/nvidia/generated/g_event_buffer_nvoc.h -9934a21ca6169499e471a2fc000c3eaee348391e - src/nvidia/generated/g_resource_fwd_decls_nvoc.h +a4213261e7f2ae0014f7056c33ab04bacf07c9de - src/nvidia/generated/g_resource_fwd_decls_nvoc.h aac0c7df733e179f2a5906ab66b302a5bee82cbe - src/nvidia/generated/g_gpu_db_nvoc.h 47ced25e3252d402b9a5c30115705d16651ab460 - src/nvidia/generated/g_object_nvoc.h 81f915ae199df67c1884bfc18f3d23f20941af6a - src/nvidia/generated/g_dce_client_nvoc.c c8d6ddc934e0c4ae3fd2d2dc81d0d1a91c8b8d52 - src/nvidia/generated/g_disp_inst_mem_nvoc.h b30dc7b4114007f7649e18a7be2d829a3752447a - src/nvidia/generated/g_mem_nvoc.c 33932ed2752329a63bcafd88f00e69203c3621c0 - src/nvidia/generated/g_gpu_mgr_nvoc.h -2156c006acf83494e55de3d5604e9234f73b2867 - src/nvidia/generated/g_eng_desc_nvoc.h +c0750d49486dcf1718083d5deaef16c718b9a909 - src/nvidia/generated/g_eng_desc_nvoc.h 6742231d4f59cc03ed822b80fb3995d1821de488 - src/nvidia/generated/g_standard_mem_nvoc.c a42b32adb0533fafb2de6b127c7e1939029cdeb5 - src/nvidia/generated/g_system_nvoc.c a044b01f708a5690f1796579904539791e24d5a3 - src/nvidia/generated/g_hda_codec_api_nvoc.h ddc0ac4e1d8b8aef15e147f1f85f8df37c196763 - src/nvidia/generated/g_hal_register.h fc7f913eab7ef26b877606e0593928784c3121ec - src/nvidia/generated/g_device_nvoc.c +4a99aba1b2a7bd0d5fb8ef6de414e14858d068ba - src/nvidia/generated/g_console_mem_nvoc.c 261e6dfca63b12cb12e97a2f0c4447a3954dbe0a - src/nvidia/generated/g_rpc-structures.h 8db5b2345278ce409562ca35754447d353dd54d7 - src/nvidia/generated/g_rs_resource_nvoc.h ad695d35b837b970b8f50a280d400ffed5067c0f - src/nvidia/generated/g_os_desc_mem_nvoc.c @@ -711,13 +712,16 @@ d47bc1508583e02dc8234efce85fb7803dbd3d97 - src/nvidia/generated/g_hypervisor_nvo af86a67a1c33acc193efa6dba8bc46ebe5dbb5eb - src/nvidia/generated/g_gpu_class_list.c aac848bd48955659eb5e07fcac70e6fe3c3a137a - src/nvidia/generated/g_hal_nvoc.c 1ca8ad4d9216aef1df145358c48e7ca533927e25 - src/nvidia/generated/g_objtmr_nvoc.c +f5ad33480e2b73c6ff2bfd586e027f19318a597c - src/nvidia/generated/g_disp_console_mem_nvoc.h b35821f54f7ec965edd25a60e58d7639cd19df19 - src/nvidia/generated/g_hal_archimpl.h 97ce053e6b047ecd0803a7571d061516de9d95ff - src/nvidia/generated/g_hal_mgr_nvoc.c 87510f9f25364673fedfd1d820aedc85852ef5df - src/nvidia/generated/g_rpc-message-header.h 906af83650985c58b63fe3e1f24b75b5ac62d90d - src/nvidia/generated/g_gpu_nvoc.c 431796f7485743a0848883a204676424b4a3b65f - src/nvidia/generated/g_hal.h 44bcd3503d90703a33a7bb9c75b41111d092c5f8 - src/nvidia/generated/g_client_resource_nvoc.c +a4d3356c085ac066331092ca8abc714eae503abc - src/nvidia/generated/g_disp_console_mem_nvoc.c 142a5e1b07a3bbe2952b27f4a65a133f5a100dc3 - src/nvidia/generated/g_prereq_tracker_nvoc.c +24fe74bdc3aa966907752a24a7d6bff2c74abd4f - src/nvidia/generated/g_console_mem_nvoc.h 3c7d16d75ef53c09d7076c55976e71fd17a3f483 - src/nvidia/generated/g_subdevice_nvoc.h 7c698deeb69b4e92af3c7c4e6fc6274b75dab05c - src/nvidia/generated/g_disp_channel_nvoc.c 9b0d4695e84ec959790dd553944cb44685c5c251 - src/nvidia/generated/g_event_nvoc.h @@ -727,7 +731,7 @@ b459db8ccf299f7bda0fa9fa18ef1e3aeb2996eb - src/nvidia/generated/g_gpu_user_share 170a42c047d0085873a48db0d83d59feb8dc327f - src/nvidia/generated/g_binary_api_nvoc.c 47f006ce959471f8ecd2a7b05d83d854610a521b - src/nvidia/generated/g_system_mem_nvoc.c b9f25e208f5ea6f566dbd9cbcaaa30cd0786c31b - src/nvidia/generated/g_client_nvoc.h -31ee3939e0830f960aeb854827af0aace0dddb93 - src/nvidia/generated/g_kern_disp_nvoc.h +c5021789fed61a37794ade5a3632a8eb37c0c27f - src/nvidia/generated/g_kern_disp_nvoc.h eb95c379eec668bfd697bcd4977d4f18da0b56bb - src/nvidia/generated/g_device_nvoc.h 1d66bab50a7d39faa2b0fec469a4512d2c7610d5 - src/nvidia/generated/g_rmconfig_util.c a1bfb789c1e23bac2b7a31255b7d738e40a290f2 - src/nvidia/generated/g_mem_nvoc.h @@ -764,7 +768,7 @@ d960a819d29d7e968eaab0e7a29897426b7ba646 - src/nvidia/generated/g_io_vaspace_nvo 37d1e3dd86e6409b8e461f90386e013194c9e4d1 - src/nvidia/src/kernel/gpu_mgr/gpu_mgmt_api.c d5d8ff429d3bda7103bafcb2dca94678efc8ddd8 - src/nvidia/src/kernel/gpu_mgr/gpu_group.c 4e1be780ac696a61f056933e5550040a2d42c6bd - src/nvidia/src/kernel/gpu/gpu_device_mapping.c -381cbcd5c362e5c5563806bfff2fb60eec80eda2 - src/nvidia/src/kernel/gpu/gpu.c +04405af0ee123eb4491b8333aa4018950ea65935 - src/nvidia/src/kernel/gpu/gpu.c cb9af9dcd3931eb62bfdb4872c4e3001ff9def26 - src/nvidia/src/kernel/gpu/gpu_rmapi.c bfcdb98c6541f95c3a37aaa25e9ca51ec2a0b9c1 - src/nvidia/src/kernel/gpu/eng_state.c 6fa4ba2da905692cd39ec09054f2bd6621aa2a7a - src/nvidia/src/kernel/gpu/gpu_resource_desc.c @@ -792,13 +796,14 @@ ba49fc89b1a453aca3a79f51d3250c7c0a667327 - src/nvidia/src/kernel/gpu/subdevice/s 8ce824bfdb06f08567a29ee5e175106c32611182 - src/nvidia/src/kernel/gpu/disp/disp_channel.c 6437dd659a38c62cd81fb59f229bd94e59f37e71 - src/nvidia/src/kernel/gpu/disp/disp_sf_user.c c3d94d9a49e1c0dffd8987d9b007a9cef91be561 - src/nvidia/src/kernel/gpu/disp/disp_object_kern_ctrl_minimal.c -4b783bc279ea35c4b7e101a668d136f1a12d9030 - src/nvidia/src/kernel/gpu/disp/kern_disp.c +e5ae629f9b7d4346624da085edde80fda18c679d - src/nvidia/src/kernel/gpu/disp/kern_disp.c 681499b2c86582cd110ede079d757c5797c4b458 - src/nvidia/src/kernel/gpu/disp/disp_common_kern_ctrl_minimal.c 1533c870f3e6521f180eb967f7144a62a727d125 - src/nvidia/src/kernel/gpu/disp/disp_objs.c ceb516c8064e1df2d18897f98f5c8ea58e907973 - src/nvidia/src/kernel/gpu/disp/disp_capabilities.c 84fdcdf90d9a656a572774fb8330f7a1fa9f59e2 - src/nvidia/src/kernel/gpu/disp/inst_mem/disp_inst_mem.c 629566bf98be863b12e6dc6aab53d8f5ea13988c - src/nvidia/src/kernel/gpu/disp/inst_mem/arch/v03/disp_inst_mem_0300.c 0156d5407cf877b8f5c79823d3c83ead54b6385c - src/nvidia/src/kernel/gpu/disp/head/kernel_head.c +d9ecaa221da6120a6149292cc1ab9ff50caca3fa - src/nvidia/src/kernel/gpu/disp/console_mem/disp_console_mem.c 8a418dce9fbeb99d5d6e175ed8c88811866f3450 - src/nvidia/src/kernel/gpu/disp/arch/v04/kern_disp_0402.c e7f143390807f3f4d4bf6586068378a9f5a75d57 - src/nvidia/src/kernel/gpu/disp/arch/v03/kern_disp_0300.c 611098328a114b66c6dcea4a8ea710887db006c4 - src/nvidia/src/kernel/gpu/arch/t23x/kern_gpu_t234d.c @@ -844,7 +849,7 @@ b4dc306ae4d4f8850571e2fbbed0114d63f1ba93 - src/nvidia/src/kernel/rmapi/entry_poi f04faaeeeda2d799207fd7e0877a2bb6d5363c13 - src/nvidia/src/kernel/rmapi/mapping.c b001f31a373973b7a4568c411e261aa8f7487441 - src/nvidia/src/kernel/rmapi/alloc_free.c d6b3b8ac45ede7530028848749820d2cbe0f5d55 - src/nvidia/src/kernel/rmapi/resource_desc.h -ea7b6b816ca16af62c0b2040b8a76c6c10a16053 - src/nvidia/src/kernel/rmapi/resource_list.h +996a104e06ba0a173eba0099f2c02ff0b085e23d - src/nvidia/src/kernel/rmapi/resource_list.h b28d140f1bfe0aac770127e8391400d44d5582e3 - src/nvidia/src/kernel/rmapi/rmapi_finn.c 682977753c878ccee6279e539cf11bee2b548752 - src/nvidia/src/kernel/rmapi/resource_desc.c 9b1453ed00d80034a0d2e3e918d31dbe939177b0 - src/nvidia/src/kernel/rmapi/rmapi_utils.c @@ -853,6 +858,7 @@ c4eeb6d566366ab2b9532f109632d4e14539332c - src/nvidia/src/kernel/rmapi/entry_poi a14b8d9a6e029d8a5c571283b520645a562b5c2c - src/nvidia/src/kernel/mem_mgr/vaspace.c 5b9048e62581a3fbb0227d1a46c4ee8d8397bf5b - src/nvidia/src/kernel/mem_mgr/mem_mgr_internal.h 623dad3ec0172ed7b3818caece0db5687d587ff3 - src/nvidia/src/kernel/mem_mgr/os_desc_mem.c +c53834dec3041617296e4d124647b363455e1264 - src/nvidia/src/kernel/mem_mgr/console_mem.c 38b2ed45dc7d7d7172f6d0fd2be31b43e49e41d5 - src/nvidia/src/kernel/mem_mgr/virt_mem_mgr.c ed8316b9cbfe13336af1f8e4cd0b492a21af44b9 - src/nvidia/src/kernel/mem_mgr/syncpoint_mem.c e75d8a0eb4c22e11ececd24a43ad034bb76f12ce - src/nvidia/src/kernel/mem_mgr/standard_mem.c @@ -916,14 +922,15 @@ ae7d5cb2c57beeea12724e09d957e233a71c12a1 - src/nvidia/arch/nvalloc/unix/include/ de6913c5e5092a417530ac9f818497824eab7946 - src/nvidia/arch/nvalloc/unix/include/os-interface.h ddfedb3b81feb09ea9daadf1a7f63f6309ee6e3b - src/nvidia/arch/nvalloc/unix/include/rmobjexportimport.h a28937330829b4f27a9da5e2c3776ceb293b6085 - src/nvidia/arch/nvalloc/unix/src/os-hypervisor-stubs.c +ff839a6e0535caf19fb52ec24d33f7368aada796 - src/nvidia/arch/nvalloc/unix/src/unix_console.c 6ca29f3d6b38fb5d05ff222cd1b79ade811a74b2 - src/nvidia/arch/nvalloc/unix/src/osunix.c 8f725a01c2a29658580936a87bdd33308030a332 - src/nvidia/arch/nvalloc/unix/src/os.c -866073d8caaa58055268aa5b3548eec6e1168d04 - src/nvidia/arch/nvalloc/unix/src/exports-stubs.c +16e1482d8a9287bc2fd3da28dd62066e4e3ff92b - src/nvidia/arch/nvalloc/unix/src/exports-stubs.c 63edc719390a814eb70290e709634d133ad198cc - src/nvidia/arch/nvalloc/unix/src/osmemdesc.c 690927567b5344c8030e2c52d91f824bb94e956c - src/nvidia/arch/nvalloc/unix/src/registry.c eccfc4f261fd8531254eb2961120073aac9847db - src/nvidia/arch/nvalloc/unix/src/rmobjexportimport.c 4971626589ae66cc273ad11b80f0ab875fb39c05 - src/nvidia/arch/nvalloc/unix/src/osapi.c -68d80083483bf4976d6d83153a3880e5949e0824 - src/nvidia/arch/nvalloc/unix/src/osinit.c +15920addb99f39201a7a7cc9c4e7a9e22c13d118 - src/nvidia/arch/nvalloc/unix/src/osinit.c 69d2719c759456a22ccc4de470e5d15cf0c3d26c - src/nvidia/arch/nvalloc/unix/src/escape.c b5b409625fde1b640e4e93276e35248f0fccfa4c - src/nvidia/arch/nvalloc/unix/src/gcc_helper.c 11c6d988bccbdf49ac241d77e6363c7843a0191f - src/nvidia/arch/nvalloc/unix/src/power-management-tegra.c @@ -965,6 +972,7 @@ b39826404d84e0850aa3385691d8dde6e30d70d4 - src/nvidia/inc/kernel/gpu/disp/disp_s 5179f01acf7e9e251552dc17c0dcd84f7d341d82 - src/nvidia/inc/kernel/gpu/disp/inst_mem/disp_inst_mem.h f758ea5f9cbd23a678290ef0b8d98d470e3499e0 - src/nvidia/inc/kernel/gpu/disp/vblank_callback/vblank.h 9a33a37c6cea9bad513aa14c942c689f28f7c0d8 - src/nvidia/inc/kernel/gpu/disp/head/kernel_head.h +57388b52df54a785b2d7118774df5433603adb24 - src/nvidia/inc/kernel/gpu/disp/console_mem/disp_console_mem.h 7b7cf3b6459711065d1b849bf5acaea10b6400ca - src/nvidia/inc/kernel/gpu/intr/intr_common.h 889ba18a43cc2b5c5e970a90ddcb770ce873b785 - src/nvidia/inc/kernel/gpu/mem_mgr/mem_desc.h c2957c7f40cc454ba12fd954397fcea5d95ccae5 - src/nvidia/inc/kernel/gpu/mem_mgr/rm_page_size.h @@ -1017,6 +1025,7 @@ d15991bc770c5ab41fe746995294c5213efa056b - src/nvidia/inc/kernel/mem_mgr/io_vasp 02d6a37ef1bb057604cb98a905fa02429f200c96 - src/nvidia/inc/kernel/mem_mgr/mem.h 5ae08b2077506cbc41e40e1b3672e615ce9d910f - src/nvidia/inc/kernel/mem_mgr/vaspace.h 4c386104eaead66c66df11258c3f1182b46e96ee - src/nvidia/inc/kernel/mem_mgr/syncpoint_mem.h +7ea2f63fba8468fb30c9d2fa014a99dfbb440518 - src/nvidia/inc/kernel/mem_mgr/console_mem.h 2d4afabd63699feec3aea5e89601db009fc51a08 - src/nvidia/inc/kernel/mem_mgr/standard_mem.h 1a08e83fd6f0a072d6887c60c529e29211bcd007 - src/nvidia/inc/kernel/mem_mgr/os_desc_mem.h 5fd1da24ae8263c43dc5dada4702564b6f0ca3d9 - src/nvidia/inc/os/dce_rm_client_ipc.h @@ -1081,9 +1090,9 @@ e35ff9733ea7fbffe0641399ccb0fd92a492e30d - src/nvidia/inc/libraries/nvoc/runtime 1b28bd0ee2e560ca2854a73a3ee5fb1cf713d013 - src/nvidia/inc/libraries/nvoc/utility.h 3919368b5b4cdd72d7da49801232048b5e786845 - src/nvidia/inc/libraries/nvoc/prelude.h 0b1508742a1c5a04b6c3a4be1b48b506f4180848 - kernel-open/dkms.conf -f0c0779173705b8642836f8c4e2743ea4e2b1898 - kernel-open/Kbuild +4dc2e90b02ea481ef1fecb2e22551354bf8615ca - kernel-open/Kbuild 4f4410c3c8db46e5a98d7a35f7d909a49de6cb43 - kernel-open/Makefile -dad08b7e40e26dc53dc7938ecbed2991117a8fe4 - kernel-open/conftest.sh +6a9b31e3d157dea5790b05752f5521d2870f88bc - kernel-open/conftest.sh 646e6b03521587cc1a02617afd697183e5d1a83a - kernel-open/nvidia-modeset/nv-kthread-q.c 2ea1436104463c5e3d177e8574c3b4298976d37e - kernel-open/nvidia-modeset/nvkms-ioctl.h 7dbe6f8405e47c1380c6151c7c7d12b0b02ef7f4 - kernel-open/nvidia-modeset/nvidia-modeset.Kbuild @@ -1112,7 +1121,7 @@ e1144f5bd643d24f67b7577c16c687294cb50d39 - kernel-open/common/inc/rm-gpu-ops.h 4a97d807a225d792544578f8112c9a3f90cc38f6 - kernel-open/common/inc/nvstatuscodes.h d51449fa2fd19748007f2e98f0233c92b45f9572 - kernel-open/common/inc/nvkms-api-types.h 880e45b68b19fdb91ac94991f0e6d7fc3b406b1f - kernel-open/common/inc/nv-pci-types.h -bf4fdaa93deed0b110d5ca954a1f9678ffaabc6e - kernel-open/common/inc/nv-platform.h +e6c1a783642af932b1ed8e35810c768de492c070 - kernel-open/common/inc/nv-platform.h 3a26838c4edd3525daa68ac6fc7b06842dc6fc07 - kernel-open/common/inc/nv-gpu-info.h 3f7b20e27e6576ee1f2f0557d269697a0b8af7ec - kernel-open/common/inc/nv-firmware-registry.h 5cf4b517c9bd8f14593c1a6450078a774a39dd08 - kernel-open/common/inc/nv-hypervisor.h @@ -1149,7 +1158,7 @@ cda75171ca7d8bf920aab6d56ef9aadec16fd15d - kernel-open/common/inc/os/nv_memory_t 86443277db67b64c70260e5668bb4140bc90165c - kernel-open/nvidia/nv-clk.c ef8fd76c55625aeaa71c9b789c4cf519ef6116b2 - kernel-open/nvidia/libspdm_hkdf.c 4c64885083621f5f313a7dee72e14eee8abed2a0 - kernel-open/nvidia/nvidia-sources.Kbuild -7f7c904b1f3daaecc31a5e34842717ceca639a9f - kernel-open/nvidia/nv-platform.c +bdd4cf90dc9719e421b536811fc3802029a7a45a - kernel-open/nvidia/nv-platform.c e5cd40b060a69cf71220c910e9428d7f261892f7 - kernel-open/nvidia/internal_crypt_lib.h 646e6b03521587cc1a02617afd697183e5d1a83a - kernel-open/nvidia/nv-kthread-q.c 4e5a330fa40dab218821976ac1b530c649d48994 - kernel-open/nvidia/libspdm_ecc.c @@ -1158,7 +1167,7 @@ e5cd40b060a69cf71220c910e9428d7f261892f7 - kernel-open/nvidia/internal_crypt_lib ab04c42e0e8e7f48f1a7074885278bbb6006d65f - kernel-open/nvidia/nv-bpmp.c 95ae148b016e4111122c2d9f8f004b53e78998f3 - kernel-open/nvidia/nv-memdbg.c fbae5663e3c278d8206d07ec6446ca4c2781795f - kernel-open/nvidia/nv-ibmnpu.h -ec3055aa73c6c65b601ea040989f0b638a847e86 - kernel-open/nvidia/os-interface.c +e1f18e92457844913b9b6613d2f6dca73fc233c3 - kernel-open/nvidia/os-interface.c dd819a875c584bc469082fcf519779ea00b1d952 - kernel-open/nvidia/libspdm_aead_aes_gcm.c 980556d84bc56e819955b9338a43a9d970dba11d - kernel-open/nvidia/nv_gpu_ops.h 4eee7319202366822e17d29ecec9f662c075e7ac - kernel-open/nvidia/nv-rsync.c @@ -1174,7 +1183,7 @@ dc39c4ee87f4dc5f5ccc179a98e07ddb82bb8bce - kernel-open/nvidia/nv-modeset-interfa cf98395acb4430a7c105218f7a4b5f7e810b39cf - kernel-open/nvidia/os-registry.c 7b1bd10726481626dd51f4eebb693794561c20f6 - kernel-open/nvidia/nv-host1x.c 1a98a2aaf386cd3d03b4b5513d6a511c60f71c2c - kernel-open/nvidia/nv-reg.h -6af73d13ef5a2862156b0cfcbd1f79fb64341636 - kernel-open/nvidia/nv.c +e7a9eb87524d092f9785e35806ef03d96aa3aff7 - kernel-open/nvidia/nv.c 37654472e65659be229b5e35c6f25c0724929511 - kernel-open/nvidia/nv-frontend.c d9221522e02e18b037b8929fbc075dc3c1e58654 - kernel-open/nvidia/nv-pci-table.c 94344ec0af21bd9c7c7ab912f7bd3a8668a3e0aa - kernel-open/nvidia/os-pci.c @@ -1207,7 +1216,7 @@ d68af9144d3d487308e73d0a52f4474f8047d6ca - kernel-open/nvidia/nv-gpio.c e0a37b715684ae0f434327e4ce1b5832caf7ea4e - kernel-open/nvidia/nv-nano-timer.c 3b27e4eaa97bd6fa71f1a075b50af69b1ec16454 - kernel-open/nvidia/libspdm_ec.c fc22bea3040ae178492cb9c7a62f1d0012b1c113 - kernel-open/nvidia/nv-procfs.c -a46f27be57870c7669f3e43fffb7e1fdaff5a3d6 - kernel-open/nvidia/nvidia.Kbuild +e3806f50e77b4d6e854c4e84631a1d5fc0f4b710 - kernel-open/nvidia/nvidia.Kbuild 6060392eec4e707ac61ebca3995b6a966eba7fc1 - kernel-open/nvidia/nv-p2p.h 642c3a7d10b263ab9a63073f83ad843566927b58 - kernel-open/nvidia/libspdm_hmac_sha.c 8f87a475c202458948025d1521968677fc11dd50 - kernel-open/nvidia/nv-msi.c diff --git a/kernel-open/Kbuild b/kernel-open/Kbuild index 774a16f..2470c70 100644 --- a/kernel-open/Kbuild +++ b/kernel-open/Kbuild @@ -290,6 +290,7 @@ NV_HEADER_PRESENCE_TESTS = \ linux/of_platform.h \ linux/of_device.h \ linux/of_gpio.h \ + linux/of_clk.h \ linux/gpio.h \ linux/gpio/consumer.h \ linux/interconnect.h \ diff --git a/kernel-open/common/inc/nv-platform.h b/kernel-open/common/inc/nv-platform.h index 69d1332..63e6ba9 100644 --- a/kernel-open/common/inc/nv-platform.h +++ b/kernel-open/common/inc/nv-platform.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2019-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2019-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -35,6 +35,6 @@ int nv_platform_count_devices(void); int nv_soc_register_irqs(nv_state_t *nv); void nv_soc_free_irqs(nv_state_t *nv); -int nv_remove_conflicting_framebuffers(void); +int nv_disable_simplefb_clocks(void); #endif diff --git a/kernel-open/conftest.sh b/kernel-open/conftest.sh index 63d2cd4..c8fc35a 100755 --- a/kernel-open/conftest.sh +++ b/kernel-open/conftest.sh @@ -1652,6 +1652,22 @@ compile_test() { fi ;; + of_clk_get_parent_count) + # + # Determine if the of_clk_get_parent_count function is present. + # + CODE=" + #if defined(NV_LINUX_OF_CLK_H_PRESENT) + #include + #endif + void conftest_of_clk_get_parent_count(void) + { + of_clk_get_parent_count(); + } + " + compile_check_conftest "$CODE" "NV_OF_CLK_GET_PARENT_COUNT_PRESENT" "" "functions" + ;; + of_node_to_nid) # # Determine if of_node_to_nid is present @@ -6443,22 +6459,6 @@ compile_test() { compile_check_conftest "$CODE" "NV_DRM_APERTURE_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS_HAS_DRIVER_ARG" "" "types" ;; - remove_conflicting_framebuffers) - # - # Determine if remove_conflicting_framebuffers function is present. - # - # Added by commit 06415c5 ("fbmem, drm/nouveau: kick firmware framebuffers as soon as possible") - # in v2.6.35-rc1 (2010-05-18) - # - CODE=" - #include - void conftest_remove_conflicting_framebuffers(void) { - remove_conflicting_framebuffers(); - }" - - compile_check_conftest "$CODE" "NV_REMOVE_CONFLICTING_FRAMEBUFFERS_PRESENT" "" "functions" - ;; - crypto) # # Determine if we support various crypto functions. diff --git a/kernel-open/nvidia/nv-platform.c b/kernel-open/nvidia/nv-platform.c index fc85f20..a5193e6 100644 --- a/kernel-open/nvidia/nv-platform.c +++ b/kernel-open/nvidia/nv-platform.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2019-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2019-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -1386,7 +1386,7 @@ NvBool nv_get_hdcp_enabled(nv_state_t *nv) return NV_FALSE; } -int nv_remove_conflicting_framebuffers(void) +int nv_disable_simplefb_clocks(void) { int status = 0; @@ -1399,8 +1399,38 @@ int nv_remove_conflicting_framebuffers(void) { if (!registered_fb[i]) continue; -#if defined(NV_REMOVE_CONFLICTING_FRAMEBUFFERS_PRESENT) - status = remove_conflicting_framebuffers(registered_fb[i]->apertures, nv_platform_driver.driver.name, false); + +#if defined(CONFIG_OF) && defined(CONFIG_COMMON_CLK) + struct clk *clock; + struct device_node *np = NULL; + unsigned int clk_count = 0; + int j; + + np = of_find_node_by_name(NULL, "framebuffer"); + if ((np != NULL) && of_device_is_available(np)) + { +#if defined(NV_LINUX_OF_CLK_H_PRESENT) && defined(NV_OF_CLK_GET_PARENT_COUNT_PRESENT) + clk_count = of_clk_get_parent_count(np); + for (j = 0; j < clk_count; j++) + { + clock = of_clk_get(np, j); + if (IS_ERR(clock)) + { + nv_printf(NV_DBG_ERRORS, "clock %d not found %ld\n", j, PTR_ERR(clock)); + continue; + } + else + { + if (__clk_is_enabled(clock)) + { + clk_disable_unprepare(clock); + } + clk_put(clock); + } + } +#endif + } + of_node_put(np); #endif } } diff --git a/kernel-open/nvidia/nv.c b/kernel-open/nvidia/nv.c index 915ce5b..ccddd6c 100644 --- a/kernel-open/nvidia/nv.c +++ b/kernel-open/nvidia/nv.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 1999-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 1999-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -1255,11 +1255,11 @@ static int nv_start_device(nv_state_t *nv, nvidia_stack_t *sp) goto failed; } - rc = nv_remove_conflicting_framebuffers(); + rc = nv_disable_simplefb_clocks(); if (rc) { NV_DEV_PRINTF(NV_DBG_ERRORS, nv, - "nv_remove_conflicting_framebuffers failed, status %d\n", + "nv_disable_simplefb_clocks failed, status %d\n", rc); goto failed; } diff --git a/kernel-open/nvidia/nvidia.Kbuild b/kernel-open/nvidia/nvidia.Kbuild index d3f7793..aa07ce3 100644 --- a/kernel-open/nvidia/nvidia.Kbuild +++ b/kernel-open/nvidia/nvidia.Kbuild @@ -196,7 +196,7 @@ NV_CONFTEST_FUNCTION_COMPILE_TESTS += devm_clk_bulk_get_all NV_CONFTEST_FUNCTION_COMPILE_TESTS += get_task_ioprio NV_CONFTEST_FUNCTION_COMPILE_TESTS += mdev_set_iommu_device NV_CONFTEST_FUNCTION_COMPILE_TESTS += offline_and_remove_memory -NV_CONFTEST_FUNCTION_COMPILE_TESTS += remove_conflicting_framebuffers +NV_CONFTEST_FUNCTION_COMPILE_TESTS += of_clk_get_parent_count NV_CONFTEST_SYMBOL_COMPILE_TESTS += is_export_symbol_gpl_of_node_to_nid NV_CONFTEST_SYMBOL_COMPILE_TESTS += is_export_symbol_gpl_sme_active diff --git a/kernel-open/nvidia/os-interface.c b/kernel-open/nvidia/os-interface.c index 5003ad4..c5007b4 100644 --- a/kernel-open/nvidia/os-interface.c +++ b/kernel-open/nvidia/os-interface.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 1999-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 1999-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -1218,9 +1218,6 @@ void NV_API_CALL os_get_screen_info( if (!registered_fb[i]) continue; - /* Make sure base address is mapped to GPU BAR */ - if ((registered_fb[i]->fix.smem_start == consoleBar1Address) || - (registered_fb[i]->fix.smem_start == consoleBar2Address)) { *pPhysicalAddress = registered_fb[i]->fix.smem_start; *pFbWidth = registered_fb[i]->var.xres; diff --git a/push_info.txt b/push_info.txt index b12c12c..a4ae2f7 100644 --- a/push_info.txt +++ b/push_info.txt @@ -1 +1 @@ -rel-36_eng_2024-03-14 +rel-36_eng_2024-04-04 diff --git a/src/nvidia-modeset/src/nvkms-evo3.c b/src/nvidia-modeset/src/nvkms-evo3.c index b9c7468..1652d19 100644 --- a/src/nvidia-modeset/src/nvkms-evo3.c +++ b/src/nvidia-modeset/src/nvkms-evo3.c @@ -8094,7 +8094,11 @@ NVEvoHAL nvEvoC6 = { TRUE, /* supportsVblankSyncObjects */ FALSE, /* requiresScalingTapsInBothDimensions */ TRUE, /* supportsMergeMode */ - TRUE, /* supportsHDMI10BPC */ + // XXX HDMI TODO: Enable 10bpc support in Bug 4590142 + // HDMI RGB 10bpc support is not fully working on rel-36 yet for Tegra SOC + // resulting in issues with specific monitors. Hence disabling it temporarily + // until it is fully enabled along with HDR support in above tracking bug. + FALSE, /* supportsHDMI10BPC */ NV_EVO3_SUPPORTED_DITHERING_MODES, /* supportedDitheringModes */ sizeof(NVC372_CTRL_IS_MODE_POSSIBLE_PARAMS), /* impStructSize */ NV_EVO_SCALER_2TAPS, /* minScalerTaps */ diff --git a/src/nvidia-modeset/src/nvkms-hdmi.c b/src/nvidia-modeset/src/nvkms-hdmi.c index 5e0d161..a7acd20 100644 --- a/src/nvidia-modeset/src/nvkms-hdmi.c +++ b/src/nvidia-modeset/src/nvkms-hdmi.c @@ -561,6 +561,10 @@ SendHDMIVendorSpecificInfoFrame(const NVDispEvoRec *pDispEvo, NVT_VENDOR_SPECIFIC_INFOFRAME vendorInfoFrame; NVT_STATUS status; + if (!vendorCtrl.Enable) { + return; + } + status = NvTiming_ConstructVendorSpecificInfoframe(pEdidInfo, &vendorCtrl, &vendorInfoFrame); diff --git a/src/nvidia-modeset/src/nvkms-modepool.c b/src/nvidia-modeset/src/nvkms-modepool.c index 4a3db5e..5c67719 100644 --- a/src/nvidia-modeset/src/nvkms-modepool.c +++ b/src/nvidia-modeset/src/nvkms-modepool.c @@ -1994,6 +1994,7 @@ static NvBool ConstructModeTimingsMetaData( // Currently hardcoded to send infoframe necessary for HDMI 1.4a 4kx2k extended modes. if (NVT_GET_TIMING_STATUS_TYPE(timing.etc.status) == NVT_TYPE_HDMI_EXT) { pVendorInfoFrameCtrl->Enable = 1; + pVendorInfoFrameCtrl->HDMIRevision = 14; pVendorInfoFrameCtrl->HDMIFormat = NVT_HDMI_VS_BYTE4_HDMI_VID_FMT_EXT; pVendorInfoFrameCtrl->HDMI_VIC = NVT_GET_TIMING_STATUS_SEQ(timing.etc.status); pVendorInfoFrameCtrl->ThreeDStruc = NVT_HDMI_VS_BYTE5_HDMI_3DS_NA; @@ -2001,7 +2002,9 @@ static NvBool ConstructModeTimingsMetaData( pVendorInfoFrameCtrl->MetadataPresent = 0; pVendorInfoFrameCtrl->MetadataType = NVT_HDMI_VS_BYTE_OPT2_HDMI_METADATA_TYPE_NA; } else { - pVendorInfoFrameCtrl->Enable = 0; + pVendorInfoFrameCtrl->Enable = 1; + pVendorInfoFrameCtrl->HDMIRevision = 14; + pVendorInfoFrameCtrl->HDMIFormat = NVT_HDMI_VS_BYTE4_HDMI_VID_FMT_NONE; } } } diff --git a/src/nvidia/arch/nvalloc/unix/src/exports-stubs.c b/src/nvidia/arch/nvalloc/unix/src/exports-stubs.c index 3dd0bfa..117264e 100644 --- a/src/nvidia/arch/nvalloc/unix/src/exports-stubs.c +++ b/src/nvidia/arch/nvalloc/unix/src/exports-stubs.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2020-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2020-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -239,12 +239,6 @@ deviceCtrlCmdOsUnixVTSwitch_IMPL return NV_OK; } -NV_STATUS deviceCtrlCmdOsUnixVTGetFBInfo_IMPL(Device *pDevice, - NV0080_CTRL_OS_UNIX_VT_GET_FB_INFO_PARAMS *pParams) -{ - return NV_OK; -} - NV_STATUS NV_API_CALL rm_save_low_res_mode( nvidia_stack_t *sp, nv_state_t *pNv diff --git a/src/nvidia/arch/nvalloc/unix/src/osinit.c b/src/nvidia/arch/nvalloc/unix/src/osinit.c index 4fef29a..2c43dd8 100644 --- a/src/nvidia/arch/nvalloc/unix/src/osinit.c +++ b/src/nvidia/arch/nvalloc/unix/src/osinit.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 1999-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 1999-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -45,6 +45,7 @@ #include #include "nverror.h" #include +#include #include #include @@ -603,6 +604,36 @@ osInitNvMapping( } } +static void +RmTegraSetConsolePreservationParams(OBJGPU *pGpu) +{ + nv_state_t *nv = NV_GET_NV_STATE(pGpu); + NvU64 fbBaseAddress = 0; + NvU64 fbConsoleSize = 0; + + if (!gpuFuseSupportsDisplay_HAL(pGpu)) + { + return; + } + + // + // Check the OS layer for any video memory used by a console + // driver that should be reserved. + // + fbConsoleSize = rm_get_uefi_console_size(nv, &fbBaseAddress); + + if (fbConsoleSize == 0) + { + NV_PRINTF(LEVEL_INFO, "No Frame Buffer Present\n"); + return; + } + + KernelDisplay *pKernelDisplay = GPU_GET_KERNEL_DISPLAY(pGpu); + DisplayConsoleMemory *pConsoleMem = KERNEL_DISPLAY_GET_CONSOLE_MEM(pKernelDisplay); + + consolememSetMemory(pGpu, pConsoleMem, fbBaseAddress, fbConsoleSize); +} + static NV_STATUS RmInitDeviceDma( nv_state_t *nv @@ -1249,6 +1280,7 @@ NvBool RmInitAdapter( pOS = SYS_GET_OS(pSys); + RmTegraSetConsolePreservationParams(pGpu); RmInitAcpiMethods(pOS, pSys, pGpu); if (IS_GSP_CLIENT(pGpu) && IsT234DorBetter(pGpu)) diff --git a/src/nvidia/arch/nvalloc/unix/src/unix_console.c b/src/nvidia/arch/nvalloc/unix/src/unix_console.c new file mode 100644 index 0000000..a26ee7a --- /dev/null +++ b/src/nvidia/arch/nvalloc/unix/src/unix_console.c @@ -0,0 +1,142 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2021-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +static NvBool +RmDisplayConsoleMemDescPresent +( + OBJGPU *pGpu +) +{ + NvBool bPresent = NV_FALSE; + + KernelDisplay *pKernelDisplay = GPU_GET_KERNEL_DISPLAY(pGpu); + DisplayConsoleMemory *pConsoleMem = KERNEL_DISPLAY_GET_CONSOLE_MEM(pKernelDisplay); + + if (consolememGetMemDesc(pGpu, pConsoleMem) != NULL) + { + bPresent = NV_TRUE; + } + + return bPresent; +} + +NV_STATUS deviceCtrlCmdOsUnixVTGetFBInfo_IMPL +( + Device *pDevice, + NV0080_CTRL_OS_UNIX_VT_GET_FB_INFO_PARAMS *pParams +) +{ + OBJGPU *pGpu = GPU_RES_GET_GPU(pDevice); + NvBool bContinue = NV_TRUE; + + if (rmGpuLocksAcquire(GPUS_LOCK_FLAGS_NONE, RM_LOCK_MODULES_FB) == NV_OK) + { + // See if the console is on one of the subdevices of this device. + portMemSet(pParams, 0, sizeof(*pParams)); + + SLI_LOOP_START(SLI_LOOP_FLAGS_NONE) + + nv_state_t *nv = NV_GET_NV_STATE(pGpu); + + if (RmDisplayConsoleMemDescPresent(pGpu) && bContinue) + { + NvU64 baseAddr; + NvU32 width, height, depth, pitch; + + // There should only be one. + NV_ASSERT(pParams->width == 0); + + pParams->subDeviceInstance = gpumgrGetSubDeviceInstanceFromGpu(pGpu); + + // Console is either mapped to BAR1 or BAR2 + 16 MB + os_get_screen_info(&baseAddr, &width, &height, &depth, &pitch, + nv->bars[NV_GPU_BAR_INDEX_FB].cpu_address, + nv->bars[NV_GPU_BAR_INDEX_IMEM].cpu_address + 0x1000000); + + pParams->width = (NvU16)width; + pParams->height = (NvU16)height; + pParams->depth = (NvU16)depth; + pParams->pitch = (NvU16)pitch; + + if (baseAddr != 0) + { + bContinue = NV_FALSE; + } + } + + SLI_LOOP_END + + rmGpuLocksRelease(GPUS_LOCK_FLAGS_NONE, NULL); + } + else + { + NV_PRINTF(LEVEL_INFO,"%s: Failed to acquire GPU lock", __FUNCTION__); + } + + return NV_OK; +} + + +void +dispdeviceFillVgaSavedDisplayState +( + OBJGPU *pGpu, + NvU64 vgaAddr, + NvU8 vgaMemType, + NvBool vgaValid, + NvU64 workspaceAddr, + NvU8 workspaceMemType, + NvBool workspaceValid, + NvBool baseValid, + NvBool workspaceBaseValid +) +{ + nv_state_t *nv = NV_GET_NV_STATE(pGpu); + nv_priv_t *nvp = NV_GET_NV_PRIV(nv); + NvBool use_vbios = NV_PRIMARY_VGA(nv) && RmGpuHasIOSpaceEnabled(nv); + + if (use_vbios) + { + nvp->vga.base.addr = vgaAddr; + nvp->vga.base.memTarget = vgaMemType; + nvp->vga.base.valid = vgaValid; + nvp->vga.baseValid = baseValid; + + nvp->vga.workspaceBase.addr = workspaceAddr; + nvp->vga.workspaceBase.memTarget = workspaceMemType; + nvp->vga.workspaceBase.valid = workspaceValid; + nvp->vga.workspaceBaseValid = workspaceBaseValid; + } +} + diff --git a/src/nvidia/generated/g_allclasses.h b/src/nvidia/generated/g_allclasses.h index 2e0d3b1..737c536 100644 --- a/src/nvidia/generated/g_allclasses.h +++ b/src/nvidia/generated/g_allclasses.h @@ -45,6 +45,7 @@ #include // NV01_MEMORY_SYSTEM #include // NV01_MEMORY_SYNCPOINT #include // NV01_MEMORY_SYSTEM_OS_DESCRIPTOR +#include // NV01_MEMORY_FRAMEBUFFER_CONSOLE #include // IO_VASPACE_A #include // NV01_EVENT #include // NV01_EVENT_KERNEL_CALLBACK @@ -129,6 +130,10 @@ #define NV01_MEMORY_SYSTEM_OS_DESCRIPTOR (0x00000071) #endif +#ifndef NV01_MEMORY_FRAMEBUFFER_CONSOLE +#define NV01_MEMORY_FRAMEBUFFER_CONSOLE (0x00000076) +#endif + #ifndef IO_VASPACE_A #define IO_VASPACE_A (0x000000f2) #endif diff --git a/src/nvidia/generated/g_console_mem_nvoc.c b/src/nvidia/generated/g_console_mem_nvoc.c new file mode 100644 index 0000000..ed96fb0 --- /dev/null +++ b/src/nvidia/generated/g_console_mem_nvoc.c @@ -0,0 +1,356 @@ +#define NVOC_CONSOLE_MEM_H_PRIVATE_ACCESS_ALLOWED +#include "nvoc/runtime.h" +#include "nvoc/rtti.h" +#include "nvtypes.h" +#include "nvport/nvport.h" +#include "nvport/inline/util_valist.h" +#include "utils/nvassert.h" +#include "g_console_mem_nvoc.h" + +#ifdef DEBUG +char __nvoc_class_id_uniqueness_check_0xaac69e = 1; +#endif + +extern const struct NVOC_CLASS_DEF __nvoc_class_def_ConsoleMemory; + +extern const struct NVOC_CLASS_DEF __nvoc_class_def_Object; + +extern const struct NVOC_CLASS_DEF __nvoc_class_def_RsResource; + +extern const struct NVOC_CLASS_DEF __nvoc_class_def_RmResourceCommon; + +extern const struct NVOC_CLASS_DEF __nvoc_class_def_RmResource; + +extern const struct NVOC_CLASS_DEF __nvoc_class_def_Memory; + +void __nvoc_init_ConsoleMemory(ConsoleMemory*); +void __nvoc_init_funcTable_ConsoleMemory(ConsoleMemory*); +NV_STATUS __nvoc_ctor_ConsoleMemory(ConsoleMemory*, CALL_CONTEXT * arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL * arg_pParams); +void __nvoc_init_dataField_ConsoleMemory(ConsoleMemory*); +void __nvoc_dtor_ConsoleMemory(ConsoleMemory*); +extern const struct NVOC_EXPORT_INFO __nvoc_export_info_ConsoleMemory; + +static const struct NVOC_RTTI __nvoc_rtti_ConsoleMemory_ConsoleMemory = { + /*pClassDef=*/ &__nvoc_class_def_ConsoleMemory, + /*dtor=*/ (NVOC_DYNAMIC_DTOR) &__nvoc_dtor_ConsoleMemory, + /*offset=*/ 0, +}; + +static const struct NVOC_RTTI __nvoc_rtti_ConsoleMemory_Object = { + /*pClassDef=*/ &__nvoc_class_def_Object, + /*dtor=*/ &__nvoc_destructFromBase, + /*offset=*/ NV_OFFSETOF(ConsoleMemory, __nvoc_base_Memory.__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object), +}; + +static const struct NVOC_RTTI __nvoc_rtti_ConsoleMemory_RsResource = { + /*pClassDef=*/ &__nvoc_class_def_RsResource, + /*dtor=*/ &__nvoc_destructFromBase, + /*offset=*/ NV_OFFSETOF(ConsoleMemory, __nvoc_base_Memory.__nvoc_base_RmResource.__nvoc_base_RsResource), +}; + +static const struct NVOC_RTTI __nvoc_rtti_ConsoleMemory_RmResourceCommon = { + /*pClassDef=*/ &__nvoc_class_def_RmResourceCommon, + /*dtor=*/ &__nvoc_destructFromBase, + /*offset=*/ NV_OFFSETOF(ConsoleMemory, __nvoc_base_Memory.__nvoc_base_RmResource.__nvoc_base_RmResourceCommon), +}; + +static const struct NVOC_RTTI __nvoc_rtti_ConsoleMemory_RmResource = { + /*pClassDef=*/ &__nvoc_class_def_RmResource, + /*dtor=*/ &__nvoc_destructFromBase, + /*offset=*/ NV_OFFSETOF(ConsoleMemory, __nvoc_base_Memory.__nvoc_base_RmResource), +}; + +static const struct NVOC_RTTI __nvoc_rtti_ConsoleMemory_Memory = { + /*pClassDef=*/ &__nvoc_class_def_Memory, + /*dtor=*/ &__nvoc_destructFromBase, + /*offset=*/ NV_OFFSETOF(ConsoleMemory, __nvoc_base_Memory), +}; + +static const struct NVOC_CASTINFO __nvoc_castinfo_ConsoleMemory = { + /*numRelatives=*/ 6, + /*relatives=*/ { + &__nvoc_rtti_ConsoleMemory_ConsoleMemory, + &__nvoc_rtti_ConsoleMemory_Memory, + &__nvoc_rtti_ConsoleMemory_RmResource, + &__nvoc_rtti_ConsoleMemory_RmResourceCommon, + &__nvoc_rtti_ConsoleMemory_RsResource, + &__nvoc_rtti_ConsoleMemory_Object, + }, +}; + +const struct NVOC_CLASS_DEF __nvoc_class_def_ConsoleMemory = +{ + /*classInfo=*/ { + /*size=*/ sizeof(ConsoleMemory), + /*classId=*/ classId(ConsoleMemory), + /*providerId=*/ &__nvoc_rtti_provider, +#if NV_PRINTF_STRINGS_ALLOWED + /*name=*/ "ConsoleMemory", +#endif + }, + /*objCreatefn=*/ (NVOC_DYNAMIC_OBJ_CREATE) &__nvoc_objCreateDynamic_ConsoleMemory, + /*pCastInfo=*/ &__nvoc_castinfo_ConsoleMemory, + /*pExportInfo=*/ &__nvoc_export_info_ConsoleMemory +}; + +static NvBool __nvoc_thunk_ConsoleMemory_resCanCopy(struct RsResource *pConsoleMemory) { + return conmemCanCopy((struct ConsoleMemory *)(((unsigned char *)pConsoleMemory) - __nvoc_rtti_ConsoleMemory_RsResource.offset)); +} + +static NV_STATUS __nvoc_thunk_Memory_conmemCheckMemInterUnmap(struct ConsoleMemory *pMemory, NvBool bSubdeviceHandleProvided) { + return memCheckMemInterUnmap((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_ConsoleMemory_Memory.offset), bSubdeviceHandleProvided); +} + +static NvBool __nvoc_thunk_RmResource_conmemShareCallback(struct ConsoleMemory *pResource, struct RsClient *pInvokingClient, struct RsResourceRef *pParentRef, RS_SHARE_POLICY *pSharePolicy) { + return rmresShareCallback((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_ConsoleMemory_RmResource.offset), pInvokingClient, pParentRef, pSharePolicy); +} + +static NV_STATUS __nvoc_thunk_RsResource_conmemMapTo(struct ConsoleMemory *pResource, RS_RES_MAP_TO_PARAMS *pParams) { + return resMapTo((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_ConsoleMemory_RsResource.offset), pParams); +} + +static NV_STATUS __nvoc_thunk_Memory_conmemGetMapAddrSpace(struct ConsoleMemory *pMemory, CALL_CONTEXT *pCallContext, NvU32 mapFlags, NV_ADDRESS_SPACE *pAddrSpace) { + return memGetMapAddrSpace((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_ConsoleMemory_Memory.offset), pCallContext, mapFlags, pAddrSpace); +} + +static NvU32 __nvoc_thunk_RsResource_conmemGetRefCount(struct ConsoleMemory *pResource) { + return resGetRefCount((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_ConsoleMemory_RsResource.offset)); +} + +static void __nvoc_thunk_RsResource_conmemAddAdditionalDependants(struct RsClient *pClient, struct ConsoleMemory *pResource, RsResourceRef *pReference) { + resAddAdditionalDependants(pClient, (struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_ConsoleMemory_RsResource.offset), pReference); +} + +static NV_STATUS __nvoc_thunk_RmResource_conmemControl_Prologue(struct ConsoleMemory *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return rmresControl_Prologue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_ConsoleMemory_RmResource.offset), pCallContext, pParams); +} + +static NvBool __nvoc_thunk_Memory_conmemIsGpuMapAllowed(struct ConsoleMemory *pMemory, struct OBJGPU *pGpu) { + return memIsGpuMapAllowed((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_ConsoleMemory_Memory.offset), pGpu); +} + +static NV_STATUS __nvoc_thunk_RsResource_conmemUnmapFrom(struct ConsoleMemory *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { + return resUnmapFrom((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_ConsoleMemory_RsResource.offset), pParams); +} + +static void __nvoc_thunk_RmResource_conmemControl_Epilogue(struct ConsoleMemory *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + rmresControl_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_ConsoleMemory_RmResource.offset), pCallContext, pParams); +} + +static NV_STATUS __nvoc_thunk_RsResource_conmemControlLookup(struct ConsoleMemory *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { + return resControlLookup((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_ConsoleMemory_RsResource.offset), pParams, ppEntry); +} + +static NV_STATUS __nvoc_thunk_Memory_conmemControl(struct ConsoleMemory *pMemory, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return memControl((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_ConsoleMemory_Memory.offset), pCallContext, pParams); +} + +static NV_STATUS __nvoc_thunk_Memory_conmemUnmap(struct ConsoleMemory *pMemory, CALL_CONTEXT *pCallContext, RsCpuMapping *pCpuMapping) { + return memUnmap((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_ConsoleMemory_Memory.offset), pCallContext, pCpuMapping); +} + +static NV_STATUS __nvoc_thunk_Memory_conmemGetMemInterMapParams(struct ConsoleMemory *pMemory, RMRES_MEM_INTER_MAP_PARAMS *pParams) { + return memGetMemInterMapParams((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_ConsoleMemory_Memory.offset), pParams); +} + +static NV_STATUS __nvoc_thunk_Memory_conmemGetMemoryMappingDescriptor(struct ConsoleMemory *pMemory, MEMORY_DESCRIPTOR **ppMemDesc) { + return memGetMemoryMappingDescriptor((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_ConsoleMemory_Memory.offset), ppMemDesc); +} + +static NV_STATUS __nvoc_thunk_RsResource_conmemControlFilter(struct ConsoleMemory *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return resControlFilter((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_ConsoleMemory_RsResource.offset), pCallContext, pParams); +} + +static NV_STATUS __nvoc_thunk_RmResource_conmemControlSerialization_Prologue(struct ConsoleMemory *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return rmresControlSerialization_Prologue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_ConsoleMemory_RmResource.offset), pCallContext, pParams); +} + +static NV_STATUS __nvoc_thunk_Memory_conmemIsReady(struct ConsoleMemory *pMemory, NvBool bCopyConstructorContext) { + return memIsReady((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_ConsoleMemory_Memory.offset), bCopyConstructorContext); +} + +static NV_STATUS __nvoc_thunk_Memory_conmemCheckCopyPermissions(struct ConsoleMemory *pMemory, struct OBJGPU *pDstGpu, struct Device *pDstDevice) { + return memCheckCopyPermissions((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_ConsoleMemory_Memory.offset), pDstGpu, pDstDevice); +} + +static void __nvoc_thunk_RsResource_conmemPreDestruct(struct ConsoleMemory *pResource) { + resPreDestruct((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_ConsoleMemory_RsResource.offset)); +} + +static NV_STATUS __nvoc_thunk_Memory_conmemIsDuplicate(struct ConsoleMemory *pMemory, NvHandle hMemory, NvBool *pDuplicate) { + return memIsDuplicate((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_ConsoleMemory_Memory.offset), hMemory, pDuplicate); +} + +static void __nvoc_thunk_RmResource_conmemControlSerialization_Epilogue(struct ConsoleMemory *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + rmresControlSerialization_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_ConsoleMemory_RmResource.offset), pCallContext, pParams); +} + +static NV_STATUS __nvoc_thunk_Memory_conmemMap(struct ConsoleMemory *pMemory, CALL_CONTEXT *pCallContext, struct RS_CPU_MAP_PARAMS *pParams, RsCpuMapping *pCpuMapping) { + return memMap((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_ConsoleMemory_Memory.offset), pCallContext, pParams, pCpuMapping); +} + +static NvBool __nvoc_thunk_RmResource_conmemAccessCallback(struct ConsoleMemory *pResource, struct RsClient *pInvokingClient, void *pAllocParams, RsAccessRight accessRight) { + return rmresAccessCallback((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_ConsoleMemory_RmResource.offset), pInvokingClient, pAllocParams, accessRight); +} + +const struct NVOC_EXPORT_INFO __nvoc_export_info_ConsoleMemory = +{ + /*numEntries=*/ 0, + /*pExportEntries=*/ 0 +}; + +void __nvoc_dtor_Memory(Memory*); +void __nvoc_dtor_ConsoleMemory(ConsoleMemory *pThis) { + __nvoc_dtor_Memory(&pThis->__nvoc_base_Memory); + PORT_UNREFERENCED_VARIABLE(pThis); +} + +void __nvoc_init_dataField_ConsoleMemory(ConsoleMemory *pThis) { + PORT_UNREFERENCED_VARIABLE(pThis); +} + +NV_STATUS __nvoc_ctor_Memory(Memory* , CALL_CONTEXT *, struct RS_RES_ALLOC_PARAMS_INTERNAL *); +NV_STATUS __nvoc_ctor_ConsoleMemory(ConsoleMemory *pThis, CALL_CONTEXT * arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL * arg_pParams) { + NV_STATUS status = NV_OK; + status = __nvoc_ctor_Memory(&pThis->__nvoc_base_Memory, arg_pCallContext, arg_pParams); + if (status != NV_OK) goto __nvoc_ctor_ConsoleMemory_fail_Memory; + __nvoc_init_dataField_ConsoleMemory(pThis); + + status = __nvoc_conmemConstruct(pThis, arg_pCallContext, arg_pParams); + if (status != NV_OK) goto __nvoc_ctor_ConsoleMemory_fail__init; + goto __nvoc_ctor_ConsoleMemory_exit; // Success + +__nvoc_ctor_ConsoleMemory_fail__init: + __nvoc_dtor_Memory(&pThis->__nvoc_base_Memory); +__nvoc_ctor_ConsoleMemory_fail_Memory: +__nvoc_ctor_ConsoleMemory_exit: + + return status; +} + +static void __nvoc_init_funcTable_ConsoleMemory_1(ConsoleMemory *pThis) { + PORT_UNREFERENCED_VARIABLE(pThis); + + pThis->__conmemCanCopy__ = &conmemCanCopy_IMPL; + + pThis->__nvoc_base_Memory.__nvoc_base_RmResource.__nvoc_base_RsResource.__resCanCopy__ = &__nvoc_thunk_ConsoleMemory_resCanCopy; + + pThis->__conmemCheckMemInterUnmap__ = &__nvoc_thunk_Memory_conmemCheckMemInterUnmap; + + pThis->__conmemShareCallback__ = &__nvoc_thunk_RmResource_conmemShareCallback; + + pThis->__conmemMapTo__ = &__nvoc_thunk_RsResource_conmemMapTo; + + pThis->__conmemGetMapAddrSpace__ = &__nvoc_thunk_Memory_conmemGetMapAddrSpace; + + pThis->__conmemGetRefCount__ = &__nvoc_thunk_RsResource_conmemGetRefCount; + + pThis->__conmemAddAdditionalDependants__ = &__nvoc_thunk_RsResource_conmemAddAdditionalDependants; + + pThis->__conmemControl_Prologue__ = &__nvoc_thunk_RmResource_conmemControl_Prologue; + + pThis->__conmemIsGpuMapAllowed__ = &__nvoc_thunk_Memory_conmemIsGpuMapAllowed; + + pThis->__conmemUnmapFrom__ = &__nvoc_thunk_RsResource_conmemUnmapFrom; + + pThis->__conmemControl_Epilogue__ = &__nvoc_thunk_RmResource_conmemControl_Epilogue; + + pThis->__conmemControlLookup__ = &__nvoc_thunk_RsResource_conmemControlLookup; + + pThis->__conmemControl__ = &__nvoc_thunk_Memory_conmemControl; + + pThis->__conmemUnmap__ = &__nvoc_thunk_Memory_conmemUnmap; + + pThis->__conmemGetMemInterMapParams__ = &__nvoc_thunk_Memory_conmemGetMemInterMapParams; + + pThis->__conmemGetMemoryMappingDescriptor__ = &__nvoc_thunk_Memory_conmemGetMemoryMappingDescriptor; + + pThis->__conmemControlFilter__ = &__nvoc_thunk_RsResource_conmemControlFilter; + + pThis->__conmemControlSerialization_Prologue__ = &__nvoc_thunk_RmResource_conmemControlSerialization_Prologue; + + pThis->__conmemIsReady__ = &__nvoc_thunk_Memory_conmemIsReady; + + pThis->__conmemCheckCopyPermissions__ = &__nvoc_thunk_Memory_conmemCheckCopyPermissions; + + pThis->__conmemPreDestruct__ = &__nvoc_thunk_RsResource_conmemPreDestruct; + + pThis->__conmemIsDuplicate__ = &__nvoc_thunk_Memory_conmemIsDuplicate; + + pThis->__conmemControlSerialization_Epilogue__ = &__nvoc_thunk_RmResource_conmemControlSerialization_Epilogue; + + pThis->__conmemMap__ = &__nvoc_thunk_Memory_conmemMap; + + pThis->__conmemAccessCallback__ = &__nvoc_thunk_RmResource_conmemAccessCallback; +} + +void __nvoc_init_funcTable_ConsoleMemory(ConsoleMemory *pThis) { + __nvoc_init_funcTable_ConsoleMemory_1(pThis); +} + +void __nvoc_init_Memory(Memory*); +void __nvoc_init_ConsoleMemory(ConsoleMemory *pThis) { + pThis->__nvoc_pbase_ConsoleMemory = pThis; + pThis->__nvoc_pbase_Object = &pThis->__nvoc_base_Memory.__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object; + pThis->__nvoc_pbase_RsResource = &pThis->__nvoc_base_Memory.__nvoc_base_RmResource.__nvoc_base_RsResource; + pThis->__nvoc_pbase_RmResourceCommon = &pThis->__nvoc_base_Memory.__nvoc_base_RmResource.__nvoc_base_RmResourceCommon; + pThis->__nvoc_pbase_RmResource = &pThis->__nvoc_base_Memory.__nvoc_base_RmResource; + pThis->__nvoc_pbase_Memory = &pThis->__nvoc_base_Memory; + __nvoc_init_Memory(&pThis->__nvoc_base_Memory); + __nvoc_init_funcTable_ConsoleMemory(pThis); +} + +NV_STATUS __nvoc_objCreate_ConsoleMemory(ConsoleMemory **ppThis, Dynamic *pParent, NvU32 createFlags, CALL_CONTEXT * arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL * arg_pParams) { + NV_STATUS status; + Object *pParentObj; + ConsoleMemory *pThis; + + status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(ConsoleMemory), (void**)&pThis, (void**)ppThis); + if (status != NV_OK) + return status; + + portMemSet(pThis, 0, sizeof(ConsoleMemory)); + + __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_ConsoleMemory); + + pThis->__nvoc_base_Memory.__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object.createFlags = createFlags; + + if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) + { + pParentObj = dynamicCast(pParent, Object); + objAddChild(pParentObj, &pThis->__nvoc_base_Memory.__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object); + } + else + { + pThis->__nvoc_base_Memory.__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object.pParent = NULL; + } + + __nvoc_init_ConsoleMemory(pThis); + status = __nvoc_ctor_ConsoleMemory(pThis, arg_pCallContext, arg_pParams); + if (status != NV_OK) goto __nvoc_objCreate_ConsoleMemory_cleanup; + + *ppThis = pThis; + + return NV_OK; + +__nvoc_objCreate_ConsoleMemory_cleanup: + // do not call destructors here since the constructor already called them + if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) + portMemSet(pThis, 0, sizeof(ConsoleMemory)); + else + portMemFree(pThis); + + // coverity[leaked_storage:FALSE] + return status; +} + +NV_STATUS __nvoc_objCreateDynamic_ConsoleMemory(ConsoleMemory **ppThis, Dynamic *pParent, NvU32 createFlags, va_list args) { + NV_STATUS status; + CALL_CONTEXT * arg_pCallContext = va_arg(args, CALL_CONTEXT *); + struct RS_RES_ALLOC_PARAMS_INTERNAL * arg_pParams = va_arg(args, struct RS_RES_ALLOC_PARAMS_INTERNAL *); + + status = __nvoc_objCreate_ConsoleMemory(ppThis, pParent, createFlags, arg_pCallContext, arg_pParams); + + return status; +} + diff --git a/src/nvidia/generated/g_console_mem_nvoc.h b/src/nvidia/generated/g_console_mem_nvoc.h new file mode 100644 index 0000000..ddab103 --- /dev/null +++ b/src/nvidia/generated/g_console_mem_nvoc.h @@ -0,0 +1,249 @@ +#ifndef _G_CONSOLE_MEM_NVOC_H_ +#define _G_CONSOLE_MEM_NVOC_H_ +#include "nvoc/runtime.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/* + * SPDX-FileCopyrightText: Copyright (c) 1993-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#include "g_console_mem_nvoc.h" + +#ifndef _CONSOLE_MEMORY_H_ +#define _CONSOLE_MEMORY_H_ + +#include "mem_mgr/mem.h" + +/*! + * This class is used to create hMemory referencing reserved console memory + */ +#ifdef NVOC_CONSOLE_MEM_H_PRIVATE_ACCESS_ALLOWED +#define PRIVATE_FIELD(x) x +#else +#define PRIVATE_FIELD(x) NVOC_PRIVATE_FIELD(x) +#endif +struct ConsoleMemory { + const struct NVOC_RTTI *__nvoc_rtti; + struct Memory __nvoc_base_Memory; + struct Object *__nvoc_pbase_Object; + struct RsResource *__nvoc_pbase_RsResource; + struct RmResourceCommon *__nvoc_pbase_RmResourceCommon; + struct RmResource *__nvoc_pbase_RmResource; + struct Memory *__nvoc_pbase_Memory; + struct ConsoleMemory *__nvoc_pbase_ConsoleMemory; + NvBool (*__conmemCanCopy__)(struct ConsoleMemory *); + NV_STATUS (*__conmemCheckMemInterUnmap__)(struct ConsoleMemory *, NvBool); + NvBool (*__conmemShareCallback__)(struct ConsoleMemory *, struct RsClient *, struct RsResourceRef *, RS_SHARE_POLICY *); + NV_STATUS (*__conmemMapTo__)(struct ConsoleMemory *, RS_RES_MAP_TO_PARAMS *); + NV_STATUS (*__conmemGetMapAddrSpace__)(struct ConsoleMemory *, CALL_CONTEXT *, NvU32, NV_ADDRESS_SPACE *); + NvU32 (*__conmemGetRefCount__)(struct ConsoleMemory *); + void (*__conmemAddAdditionalDependants__)(struct RsClient *, struct ConsoleMemory *, RsResourceRef *); + NV_STATUS (*__conmemControl_Prologue__)(struct ConsoleMemory *, CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + NvBool (*__conmemIsGpuMapAllowed__)(struct ConsoleMemory *, struct OBJGPU *); + NV_STATUS (*__conmemUnmapFrom__)(struct ConsoleMemory *, RS_RES_UNMAP_FROM_PARAMS *); + void (*__conmemControl_Epilogue__)(struct ConsoleMemory *, CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + NV_STATUS (*__conmemControlLookup__)(struct ConsoleMemory *, struct RS_RES_CONTROL_PARAMS_INTERNAL *, const struct NVOC_EXPORTED_METHOD_DEF **); + NV_STATUS (*__conmemControl__)(struct ConsoleMemory *, CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + NV_STATUS (*__conmemUnmap__)(struct ConsoleMemory *, CALL_CONTEXT *, RsCpuMapping *); + NV_STATUS (*__conmemGetMemInterMapParams__)(struct ConsoleMemory *, RMRES_MEM_INTER_MAP_PARAMS *); + NV_STATUS (*__conmemGetMemoryMappingDescriptor__)(struct ConsoleMemory *, MEMORY_DESCRIPTOR **); + NV_STATUS (*__conmemControlFilter__)(struct ConsoleMemory *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + NV_STATUS (*__conmemControlSerialization_Prologue__)(struct ConsoleMemory *, CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + NV_STATUS (*__conmemIsReady__)(struct ConsoleMemory *, NvBool); + NV_STATUS (*__conmemCheckCopyPermissions__)(struct ConsoleMemory *, struct OBJGPU *, struct Device *); + void (*__conmemPreDestruct__)(struct ConsoleMemory *); + NV_STATUS (*__conmemIsDuplicate__)(struct ConsoleMemory *, NvHandle, NvBool *); + void (*__conmemControlSerialization_Epilogue__)(struct ConsoleMemory *, CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + NV_STATUS (*__conmemMap__)(struct ConsoleMemory *, CALL_CONTEXT *, struct RS_CPU_MAP_PARAMS *, RsCpuMapping *); + NvBool (*__conmemAccessCallback__)(struct ConsoleMemory *, struct RsClient *, void *, RsAccessRight); +}; + +#ifndef __NVOC_CLASS_ConsoleMemory_TYPEDEF__ +#define __NVOC_CLASS_ConsoleMemory_TYPEDEF__ +typedef struct ConsoleMemory ConsoleMemory; +#endif /* __NVOC_CLASS_ConsoleMemory_TYPEDEF__ */ + +#ifndef __nvoc_class_id_ConsoleMemory +#define __nvoc_class_id_ConsoleMemory 0xaac69e +#endif /* __nvoc_class_id_ConsoleMemory */ + +extern const struct NVOC_CLASS_DEF __nvoc_class_def_ConsoleMemory; + +#define __staticCast_ConsoleMemory(pThis) \ + ((pThis)->__nvoc_pbase_ConsoleMemory) + +#ifdef __nvoc_console_mem_h_disabled +#define __dynamicCast_ConsoleMemory(pThis) ((ConsoleMemory*)NULL) +#else //__nvoc_console_mem_h_disabled +#define __dynamicCast_ConsoleMemory(pThis) \ + ((ConsoleMemory*)__nvoc_dynamicCast(staticCast((pThis), Dynamic), classInfo(ConsoleMemory))) +#endif //__nvoc_console_mem_h_disabled + + +NV_STATUS __nvoc_objCreateDynamic_ConsoleMemory(ConsoleMemory**, Dynamic*, NvU32, va_list); + +NV_STATUS __nvoc_objCreate_ConsoleMemory(ConsoleMemory**, Dynamic*, NvU32, CALL_CONTEXT * arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL * arg_pParams); +#define __objCreate_ConsoleMemory(ppNewObj, pParent, createFlags, arg_pCallContext, arg_pParams) \ + __nvoc_objCreate_ConsoleMemory((ppNewObj), staticCast((pParent), Dynamic), (createFlags), arg_pCallContext, arg_pParams) + +#define conmemCanCopy(pConsoleMemory) conmemCanCopy_DISPATCH(pConsoleMemory) +#define conmemCheckMemInterUnmap(pMemory, bSubdeviceHandleProvided) conmemCheckMemInterUnmap_DISPATCH(pMemory, bSubdeviceHandleProvided) +#define conmemShareCallback(pResource, pInvokingClient, pParentRef, pSharePolicy) conmemShareCallback_DISPATCH(pResource, pInvokingClient, pParentRef, pSharePolicy) +#define conmemMapTo(pResource, pParams) conmemMapTo_DISPATCH(pResource, pParams) +#define conmemGetMapAddrSpace(pMemory, pCallContext, mapFlags, pAddrSpace) conmemGetMapAddrSpace_DISPATCH(pMemory, pCallContext, mapFlags, pAddrSpace) +#define conmemGetRefCount(pResource) conmemGetRefCount_DISPATCH(pResource) +#define conmemAddAdditionalDependants(pClient, pResource, pReference) conmemAddAdditionalDependants_DISPATCH(pClient, pResource, pReference) +#define conmemControl_Prologue(pResource, pCallContext, pParams) conmemControl_Prologue_DISPATCH(pResource, pCallContext, pParams) +#define conmemIsGpuMapAllowed(pMemory, pGpu) conmemIsGpuMapAllowed_DISPATCH(pMemory, pGpu) +#define conmemUnmapFrom(pResource, pParams) conmemUnmapFrom_DISPATCH(pResource, pParams) +#define conmemControl_Epilogue(pResource, pCallContext, pParams) conmemControl_Epilogue_DISPATCH(pResource, pCallContext, pParams) +#define conmemControlLookup(pResource, pParams, ppEntry) conmemControlLookup_DISPATCH(pResource, pParams, ppEntry) +#define conmemControl(pMemory, pCallContext, pParams) conmemControl_DISPATCH(pMemory, pCallContext, pParams) +#define conmemUnmap(pMemory, pCallContext, pCpuMapping) conmemUnmap_DISPATCH(pMemory, pCallContext, pCpuMapping) +#define conmemGetMemInterMapParams(pMemory, pParams) conmemGetMemInterMapParams_DISPATCH(pMemory, pParams) +#define conmemGetMemoryMappingDescriptor(pMemory, ppMemDesc) conmemGetMemoryMappingDescriptor_DISPATCH(pMemory, ppMemDesc) +#define conmemControlFilter(pResource, pCallContext, pParams) conmemControlFilter_DISPATCH(pResource, pCallContext, pParams) +#define conmemControlSerialization_Prologue(pResource, pCallContext, pParams) conmemControlSerialization_Prologue_DISPATCH(pResource, pCallContext, pParams) +#define conmemIsReady(pMemory, bCopyConstructorContext) conmemIsReady_DISPATCH(pMemory, bCopyConstructorContext) +#define conmemCheckCopyPermissions(pMemory, pDstGpu, pDstDevice) conmemCheckCopyPermissions_DISPATCH(pMemory, pDstGpu, pDstDevice) +#define conmemPreDestruct(pResource) conmemPreDestruct_DISPATCH(pResource) +#define conmemIsDuplicate(pMemory, hMemory, pDuplicate) conmemIsDuplicate_DISPATCH(pMemory, hMemory, pDuplicate) +#define conmemControlSerialization_Epilogue(pResource, pCallContext, pParams) conmemControlSerialization_Epilogue_DISPATCH(pResource, pCallContext, pParams) +#define conmemMap(pMemory, pCallContext, pParams, pCpuMapping) conmemMap_DISPATCH(pMemory, pCallContext, pParams, pCpuMapping) +#define conmemAccessCallback(pResource, pInvokingClient, pAllocParams, accessRight) conmemAccessCallback_DISPATCH(pResource, pInvokingClient, pAllocParams, accessRight) +NvBool conmemCanCopy_IMPL(struct ConsoleMemory *pConsoleMemory); + +static inline NvBool conmemCanCopy_DISPATCH(struct ConsoleMemory *pConsoleMemory) { + return pConsoleMemory->__conmemCanCopy__(pConsoleMemory); +} + +static inline NV_STATUS conmemCheckMemInterUnmap_DISPATCH(struct ConsoleMemory *pMemory, NvBool bSubdeviceHandleProvided) { + return pMemory->__conmemCheckMemInterUnmap__(pMemory, bSubdeviceHandleProvided); +} + +static inline NvBool conmemShareCallback_DISPATCH(struct ConsoleMemory *pResource, struct RsClient *pInvokingClient, struct RsResourceRef *pParentRef, RS_SHARE_POLICY *pSharePolicy) { + return pResource->__conmemShareCallback__(pResource, pInvokingClient, pParentRef, pSharePolicy); +} + +static inline NV_STATUS conmemMapTo_DISPATCH(struct ConsoleMemory *pResource, RS_RES_MAP_TO_PARAMS *pParams) { + return pResource->__conmemMapTo__(pResource, pParams); +} + +static inline NV_STATUS conmemGetMapAddrSpace_DISPATCH(struct ConsoleMemory *pMemory, CALL_CONTEXT *pCallContext, NvU32 mapFlags, NV_ADDRESS_SPACE *pAddrSpace) { + return pMemory->__conmemGetMapAddrSpace__(pMemory, pCallContext, mapFlags, pAddrSpace); +} + +static inline NvU32 conmemGetRefCount_DISPATCH(struct ConsoleMemory *pResource) { + return pResource->__conmemGetRefCount__(pResource); +} + +static inline void conmemAddAdditionalDependants_DISPATCH(struct RsClient *pClient, struct ConsoleMemory *pResource, RsResourceRef *pReference) { + pResource->__conmemAddAdditionalDependants__(pClient, pResource, pReference); +} + +static inline NV_STATUS conmemControl_Prologue_DISPATCH(struct ConsoleMemory *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pResource->__conmemControl_Prologue__(pResource, pCallContext, pParams); +} + +static inline NvBool conmemIsGpuMapAllowed_DISPATCH(struct ConsoleMemory *pMemory, struct OBJGPU *pGpu) { + return pMemory->__conmemIsGpuMapAllowed__(pMemory, pGpu); +} + +static inline NV_STATUS conmemUnmapFrom_DISPATCH(struct ConsoleMemory *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { + return pResource->__conmemUnmapFrom__(pResource, pParams); +} + +static inline void conmemControl_Epilogue_DISPATCH(struct ConsoleMemory *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + pResource->__conmemControl_Epilogue__(pResource, pCallContext, pParams); +} + +static inline NV_STATUS conmemControlLookup_DISPATCH(struct ConsoleMemory *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { + return pResource->__conmemControlLookup__(pResource, pParams, ppEntry); +} + +static inline NV_STATUS conmemControl_DISPATCH(struct ConsoleMemory *pMemory, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pMemory->__conmemControl__(pMemory, pCallContext, pParams); +} + +static inline NV_STATUS conmemUnmap_DISPATCH(struct ConsoleMemory *pMemory, CALL_CONTEXT *pCallContext, RsCpuMapping *pCpuMapping) { + return pMemory->__conmemUnmap__(pMemory, pCallContext, pCpuMapping); +} + +static inline NV_STATUS conmemGetMemInterMapParams_DISPATCH(struct ConsoleMemory *pMemory, RMRES_MEM_INTER_MAP_PARAMS *pParams) { + return pMemory->__conmemGetMemInterMapParams__(pMemory, pParams); +} + +static inline NV_STATUS conmemGetMemoryMappingDescriptor_DISPATCH(struct ConsoleMemory *pMemory, MEMORY_DESCRIPTOR **ppMemDesc) { + return pMemory->__conmemGetMemoryMappingDescriptor__(pMemory, ppMemDesc); +} + +static inline NV_STATUS conmemControlFilter_DISPATCH(struct ConsoleMemory *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pResource->__conmemControlFilter__(pResource, pCallContext, pParams); +} + +static inline NV_STATUS conmemControlSerialization_Prologue_DISPATCH(struct ConsoleMemory *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pResource->__conmemControlSerialization_Prologue__(pResource, pCallContext, pParams); +} + +static inline NV_STATUS conmemIsReady_DISPATCH(struct ConsoleMemory *pMemory, NvBool bCopyConstructorContext) { + return pMemory->__conmemIsReady__(pMemory, bCopyConstructorContext); +} + +static inline NV_STATUS conmemCheckCopyPermissions_DISPATCH(struct ConsoleMemory *pMemory, struct OBJGPU *pDstGpu, struct Device *pDstDevice) { + return pMemory->__conmemCheckCopyPermissions__(pMemory, pDstGpu, pDstDevice); +} + +static inline void conmemPreDestruct_DISPATCH(struct ConsoleMemory *pResource) { + pResource->__conmemPreDestruct__(pResource); +} + +static inline NV_STATUS conmemIsDuplicate_DISPATCH(struct ConsoleMemory *pMemory, NvHandle hMemory, NvBool *pDuplicate) { + return pMemory->__conmemIsDuplicate__(pMemory, hMemory, pDuplicate); +} + +static inline void conmemControlSerialization_Epilogue_DISPATCH(struct ConsoleMemory *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + pResource->__conmemControlSerialization_Epilogue__(pResource, pCallContext, pParams); +} + +static inline NV_STATUS conmemMap_DISPATCH(struct ConsoleMemory *pMemory, CALL_CONTEXT *pCallContext, struct RS_CPU_MAP_PARAMS *pParams, RsCpuMapping *pCpuMapping) { + return pMemory->__conmemMap__(pMemory, pCallContext, pParams, pCpuMapping); +} + +static inline NvBool conmemAccessCallback_DISPATCH(struct ConsoleMemory *pResource, struct RsClient *pInvokingClient, void *pAllocParams, RsAccessRight accessRight) { + return pResource->__conmemAccessCallback__(pResource, pInvokingClient, pAllocParams, accessRight); +} + +NV_STATUS conmemConstruct_IMPL(struct ConsoleMemory *arg_pConsoleMemory, CALL_CONTEXT *arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL *arg_pParams); + +#define __nvoc_conmemConstruct(arg_pConsoleMemory, arg_pCallContext, arg_pParams) conmemConstruct_IMPL(arg_pConsoleMemory, arg_pCallContext, arg_pParams) +#undef PRIVATE_FIELD + + +#endif + +#ifdef __cplusplus +} // extern "C" +#endif +#endif // _G_CONSOLE_MEM_NVOC_H_ diff --git a/src/nvidia/generated/g_disp_console_mem_nvoc.c b/src/nvidia/generated/g_disp_console_mem_nvoc.c new file mode 100644 index 0000000..90494b7 --- /dev/null +++ b/src/nvidia/generated/g_disp_console_mem_nvoc.c @@ -0,0 +1,163 @@ +#define NVOC_DISP_CONSOLE_MEM_H_PRIVATE_ACCESS_ALLOWED +#include "nvoc/runtime.h" +#include "nvoc/rtti.h" +#include "nvtypes.h" +#include "nvport/nvport.h" +#include "nvport/inline/util_valist.h" +#include "utils/nvassert.h" +#include "g_disp_console_mem_nvoc.h" + +#ifdef DEBUG +char __nvoc_class_id_uniqueness_check_0x0f96d3 = 1; +#endif + +extern const struct NVOC_CLASS_DEF __nvoc_class_def_DisplayConsoleMemory; + +extern const struct NVOC_CLASS_DEF __nvoc_class_def_Object; + +void __nvoc_init_DisplayConsoleMemory(DisplayConsoleMemory*); +void __nvoc_init_funcTable_DisplayConsoleMemory(DisplayConsoleMemory*); +NV_STATUS __nvoc_ctor_DisplayConsoleMemory(DisplayConsoleMemory*); +void __nvoc_init_dataField_DisplayConsoleMemory(DisplayConsoleMemory*); +void __nvoc_dtor_DisplayConsoleMemory(DisplayConsoleMemory*); +extern const struct NVOC_EXPORT_INFO __nvoc_export_info_DisplayConsoleMemory; + +static const struct NVOC_RTTI __nvoc_rtti_DisplayConsoleMemory_DisplayConsoleMemory = { + /*pClassDef=*/ &__nvoc_class_def_DisplayConsoleMemory, + /*dtor=*/ (NVOC_DYNAMIC_DTOR) &__nvoc_dtor_DisplayConsoleMemory, + /*offset=*/ 0, +}; + +static const struct NVOC_RTTI __nvoc_rtti_DisplayConsoleMemory_Object = { + /*pClassDef=*/ &__nvoc_class_def_Object, + /*dtor=*/ &__nvoc_destructFromBase, + /*offset=*/ NV_OFFSETOF(DisplayConsoleMemory, __nvoc_base_Object), +}; + +static const struct NVOC_CASTINFO __nvoc_castinfo_DisplayConsoleMemory = { + /*numRelatives=*/ 2, + /*relatives=*/ { + &__nvoc_rtti_DisplayConsoleMemory_DisplayConsoleMemory, + &__nvoc_rtti_DisplayConsoleMemory_Object, + }, +}; + +const struct NVOC_CLASS_DEF __nvoc_class_def_DisplayConsoleMemory = +{ + /*classInfo=*/ { + /*size=*/ sizeof(DisplayConsoleMemory), + /*classId=*/ classId(DisplayConsoleMemory), + /*providerId=*/ &__nvoc_rtti_provider, +#if NV_PRINTF_STRINGS_ALLOWED + /*name=*/ "DisplayConsoleMemory", +#endif + }, + /*objCreatefn=*/ (NVOC_DYNAMIC_OBJ_CREATE) &__nvoc_objCreateDynamic_DisplayConsoleMemory, + /*pCastInfo=*/ &__nvoc_castinfo_DisplayConsoleMemory, + /*pExportInfo=*/ &__nvoc_export_info_DisplayConsoleMemory +}; + +const struct NVOC_EXPORT_INFO __nvoc_export_info_DisplayConsoleMemory = +{ + /*numEntries=*/ 0, + /*pExportEntries=*/ 0 +}; + +void __nvoc_dtor_Object(Object*); +void __nvoc_dtor_DisplayConsoleMemory(DisplayConsoleMemory *pThis) { + __nvoc_consolememDestruct(pThis); + __nvoc_dtor_Object(&pThis->__nvoc_base_Object); + PORT_UNREFERENCED_VARIABLE(pThis); +} + +void __nvoc_init_dataField_DisplayConsoleMemory(DisplayConsoleMemory *pThis) { + PORT_UNREFERENCED_VARIABLE(pThis); +} + +NV_STATUS __nvoc_ctor_Object(Object* ); +NV_STATUS __nvoc_ctor_DisplayConsoleMemory(DisplayConsoleMemory *pThis) { + NV_STATUS status = NV_OK; + status = __nvoc_ctor_Object(&pThis->__nvoc_base_Object); + if (status != NV_OK) goto __nvoc_ctor_DisplayConsoleMemory_fail_Object; + __nvoc_init_dataField_DisplayConsoleMemory(pThis); + + status = __nvoc_consolememConstruct(pThis); + if (status != NV_OK) goto __nvoc_ctor_DisplayConsoleMemory_fail__init; + goto __nvoc_ctor_DisplayConsoleMemory_exit; // Success + +__nvoc_ctor_DisplayConsoleMemory_fail__init: + __nvoc_dtor_Object(&pThis->__nvoc_base_Object); +__nvoc_ctor_DisplayConsoleMemory_fail_Object: +__nvoc_ctor_DisplayConsoleMemory_exit: + + return status; +} + +static void __nvoc_init_funcTable_DisplayConsoleMemory_1(DisplayConsoleMemory *pThis) { + PORT_UNREFERENCED_VARIABLE(pThis); +} + +void __nvoc_init_funcTable_DisplayConsoleMemory(DisplayConsoleMemory *pThis) { + __nvoc_init_funcTable_DisplayConsoleMemory_1(pThis); +} + +void __nvoc_init_Object(Object*); +void __nvoc_init_DisplayConsoleMemory(DisplayConsoleMemory *pThis) { + pThis->__nvoc_pbase_DisplayConsoleMemory = pThis; + pThis->__nvoc_pbase_Object = &pThis->__nvoc_base_Object; + __nvoc_init_Object(&pThis->__nvoc_base_Object); + __nvoc_init_funcTable_DisplayConsoleMemory(pThis); +} + +NV_STATUS __nvoc_objCreate_DisplayConsoleMemory(DisplayConsoleMemory **ppThis, Dynamic *pParent, NvU32 createFlags) { + NV_STATUS status; + Object *pParentObj; + DisplayConsoleMemory *pThis; + + status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(DisplayConsoleMemory), (void**)&pThis, (void**)ppThis); + if (status != NV_OK) + return status; + + portMemSet(pThis, 0, sizeof(DisplayConsoleMemory)); + + __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_DisplayConsoleMemory); + + pThis->__nvoc_base_Object.createFlags = createFlags; + + if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) + { + pParentObj = dynamicCast(pParent, Object); + objAddChild(pParentObj, &pThis->__nvoc_base_Object); + } + else + { + pThis->__nvoc_base_Object.pParent = NULL; + } + + __nvoc_init_DisplayConsoleMemory(pThis); + status = __nvoc_ctor_DisplayConsoleMemory(pThis); + if (status != NV_OK) goto __nvoc_objCreate_DisplayConsoleMemory_cleanup; + + *ppThis = pThis; + + return NV_OK; + +__nvoc_objCreate_DisplayConsoleMemory_cleanup: + // do not call destructors here since the constructor already called them + if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) + portMemSet(pThis, 0, sizeof(DisplayConsoleMemory)); + else + portMemFree(pThis); + + // coverity[leaked_storage:FALSE] + return status; +} + +NV_STATUS __nvoc_objCreateDynamic_DisplayConsoleMemory(DisplayConsoleMemory **ppThis, Dynamic *pParent, NvU32 createFlags, va_list args) { + NV_STATUS status; + + status = __nvoc_objCreate_DisplayConsoleMemory(ppThis, pParent, createFlags); + + return status; +} + diff --git a/src/nvidia/generated/g_disp_console_mem_nvoc.h b/src/nvidia/generated/g_disp_console_mem_nvoc.h new file mode 100644 index 0000000..b8a22c7 --- /dev/null +++ b/src/nvidia/generated/g_disp_console_mem_nvoc.h @@ -0,0 +1,174 @@ +#ifndef _G_DISP_CONSOLE_MEM_NVOC_H_ +#define _G_DISP_CONSOLE_MEM_NVOC_H_ +#include "nvoc/runtime.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/* + * SPDX-FileCopyrightText: Copyright (c) 2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#include "g_disp_console_mem_nvoc.h" + +#ifndef DISPLAY_CONSOLE_MEMORY_H +#define DISPLAY_CONSOLE_MEMORY_H + +/* ------------------------ Includes --------------------------------------- */ +#include "nvtypes.h" +#include "nvoc/utility.h" +#include "gpu/disp/kern_disp.h" +#include "gpu/mem_mgr/mem_desc.h" + +/* ------------------------ Forward Declaration ---------------------------- */ + +/* ------------------------ Macros & Defines ------------------------------- */ +#define KERNEL_DISPLAY_GET_CONSOLE_MEM(p) ((p)->pConsoleMem) + +/* ------------------------ Types definitions ------------------------------ */ + +#ifdef NVOC_DISP_CONSOLE_MEM_H_PRIVATE_ACCESS_ALLOWED +#define PRIVATE_FIELD(x) x +#else +#define PRIVATE_FIELD(x) NVOC_PRIVATE_FIELD(x) +#endif +struct DisplayConsoleMemory { + const struct NVOC_RTTI *__nvoc_rtti; + struct Object __nvoc_base_Object; + struct Object *__nvoc_pbase_Object; + struct DisplayConsoleMemory *__nvoc_pbase_DisplayConsoleMemory; + NV_ADDRESS_SPACE consoleMemAddrSpace; + NvU32 consoleMemAttr; + NvU64 consoleMemBaseAddress; + NvU64 consoleMemSize; + MEMORY_DESCRIPTOR *pConsoleMemDesc; + void *pConsoleMem; +}; + +#ifndef __NVOC_CLASS_DisplayConsoleMemory_TYPEDEF__ +#define __NVOC_CLASS_DisplayConsoleMemory_TYPEDEF__ +typedef struct DisplayConsoleMemory DisplayConsoleMemory; +#endif /* __NVOC_CLASS_DisplayConsoleMemory_TYPEDEF__ */ + +#ifndef __nvoc_class_id_DisplayConsoleMemory +#define __nvoc_class_id_DisplayConsoleMemory 0x0f96d3 +#endif /* __nvoc_class_id_DisplayConsoleMemory */ + +extern const struct NVOC_CLASS_DEF __nvoc_class_def_DisplayConsoleMemory; + +#define __staticCast_DisplayConsoleMemory(pThis) \ + ((pThis)->__nvoc_pbase_DisplayConsoleMemory) + +#ifdef __nvoc_disp_console_mem_h_disabled +#define __dynamicCast_DisplayConsoleMemory(pThis) ((DisplayConsoleMemory*)NULL) +#else //__nvoc_disp_console_mem_h_disabled +#define __dynamicCast_DisplayConsoleMemory(pThis) \ + ((DisplayConsoleMemory*)__nvoc_dynamicCast(staticCast((pThis), Dynamic), classInfo(DisplayConsoleMemory))) +#endif //__nvoc_disp_console_mem_h_disabled + + +NV_STATUS __nvoc_objCreateDynamic_DisplayConsoleMemory(DisplayConsoleMemory**, Dynamic*, NvU32, va_list); + +NV_STATUS __nvoc_objCreate_DisplayConsoleMemory(DisplayConsoleMemory**, Dynamic*, NvU32); +#define __objCreate_DisplayConsoleMemory(ppNewObj, pParent, createFlags) \ + __nvoc_objCreate_DisplayConsoleMemory((ppNewObj), staticCast((pParent), Dynamic), (createFlags)) + +NV_STATUS consolememConstruct_IMPL(struct DisplayConsoleMemory *arg_pConsoleMem); + +#define __nvoc_consolememConstruct(arg_pConsoleMem) consolememConstruct_IMPL(arg_pConsoleMem) +void consolememDestruct_IMPL(struct DisplayConsoleMemory *pConsoleMem); + +#define __nvoc_consolememDestruct(pConsoleMem) consolememDestruct_IMPL(pConsoleMem) +NV_STATUS consolememStateInitLocked_IMPL(struct OBJGPU *pGpu, struct DisplayConsoleMemory *pConsoleMem); + +#ifdef __nvoc_disp_console_mem_h_disabled +static inline NV_STATUS consolememStateInitLocked(struct OBJGPU *pGpu, struct DisplayConsoleMemory *pConsoleMem) { + NV_ASSERT_FAILED_PRECOMP("DisplayConsoleMemory was disabled!"); + return NV_ERR_NOT_SUPPORTED; +} +#else //__nvoc_disp_console_mem_h_disabled +#define consolememStateInitLocked(pGpu, pConsoleMem) consolememStateInitLocked_IMPL(pGpu, pConsoleMem) +#endif //__nvoc_disp_console_mem_h_disabled + +void consolememStateDestroy_IMPL(struct OBJGPU *pGpu, struct DisplayConsoleMemory *pConsoleMem); + +#ifdef __nvoc_disp_console_mem_h_disabled +static inline void consolememStateDestroy(struct OBJGPU *pGpu, struct DisplayConsoleMemory *pConsoleMem) { + NV_ASSERT_FAILED_PRECOMP("DisplayConsoleMemory was disabled!"); +} +#else //__nvoc_disp_console_mem_h_disabled +#define consolememStateDestroy(pGpu, pConsoleMem) consolememStateDestroy_IMPL(pGpu, pConsoleMem) +#endif //__nvoc_disp_console_mem_h_disabled + +NV_STATUS consolememStateLoad_IMPL(struct OBJGPU *pGpu, struct DisplayConsoleMemory *pConsoleMem, NvU32 flags); + +#ifdef __nvoc_disp_console_mem_h_disabled +static inline NV_STATUS consolememStateLoad(struct OBJGPU *pGpu, struct DisplayConsoleMemory *pConsoleMem, NvU32 flags) { + NV_ASSERT_FAILED_PRECOMP("DisplayConsoleMemory was disabled!"); + return NV_ERR_NOT_SUPPORTED; +} +#else //__nvoc_disp_console_mem_h_disabled +#define consolememStateLoad(pGpu, pConsoleMem, flags) consolememStateLoad_IMPL(pGpu, pConsoleMem, flags) +#endif //__nvoc_disp_console_mem_h_disabled + +NV_STATUS consolememStateUnload_IMPL(struct OBJGPU *pGpu, struct DisplayConsoleMemory *pConsoleMem, NvU32 flags); + +#ifdef __nvoc_disp_console_mem_h_disabled +static inline NV_STATUS consolememStateUnload(struct OBJGPU *pGpu, struct DisplayConsoleMemory *pConsoleMem, NvU32 flags) { + NV_ASSERT_FAILED_PRECOMP("DisplayConsoleMemory was disabled!"); + return NV_ERR_NOT_SUPPORTED; +} +#else //__nvoc_disp_console_mem_h_disabled +#define consolememStateUnload(pGpu, pConsoleMem, flags) consolememStateUnload_IMPL(pGpu, pConsoleMem, flags) +#endif //__nvoc_disp_console_mem_h_disabled + +PMEMORY_DESCRIPTOR consolememGetMemDesc_IMPL(struct OBJGPU *pGpu, struct DisplayConsoleMemory *pConsoleMem); + +#ifdef __nvoc_disp_console_mem_h_disabled +static inline PMEMORY_DESCRIPTOR consolememGetMemDesc(struct OBJGPU *pGpu, struct DisplayConsoleMemory *pConsoleMem) { + NV_ASSERT_FAILED_PRECOMP("DisplayConsoleMemory was disabled!"); + return NULL; +} +#else //__nvoc_disp_console_mem_h_disabled +#define consolememGetMemDesc(pGpu, pConsoleMem) consolememGetMemDesc_IMPL(pGpu, pConsoleMem) +#endif //__nvoc_disp_console_mem_h_disabled + +void consolememSetMemory_IMPL(struct OBJGPU *pGpu, struct DisplayConsoleMemory *pConsoleMem, NvU64 memoryRegionBaseAddress, NvU64 memoryRegionSize); + +#ifdef __nvoc_disp_console_mem_h_disabled +static inline void consolememSetMemory(struct OBJGPU *pGpu, struct DisplayConsoleMemory *pConsoleMem, NvU64 memoryRegionBaseAddress, NvU64 memoryRegionSize) { + NV_ASSERT_FAILED_PRECOMP("DisplayConsoleMemory was disabled!"); +} +#else //__nvoc_disp_console_mem_h_disabled +#define consolememSetMemory(pGpu, pConsoleMem, memoryRegionBaseAddress, memoryRegionSize) consolememSetMemory_IMPL(pGpu, pConsoleMem, memoryRegionBaseAddress, memoryRegionSize) +#endif //__nvoc_disp_console_mem_h_disabled + +#undef PRIVATE_FIELD + + +#endif // DISPLAY_CONSOLE_MEMORY_H + +#ifdef __cplusplus +} // extern "C" +#endif +#endif // _G_DISP_CONSOLE_MEM_NVOC_H_ diff --git a/src/nvidia/generated/g_eng_desc_nvoc.h b/src/nvidia/generated/g_eng_desc_nvoc.h index ba8b244..b4f49bf 100644 --- a/src/nvidia/generated/g_eng_desc_nvoc.h +++ b/src/nvidia/generated/g_eng_desc_nvoc.h @@ -572,6 +572,18 @@ typedef struct DisplayInstanceMemory DisplayInstanceMemory; #endif /* __nvoc_class_id_DisplayInstanceMemory */ +struct DisplayConsoleMemory; + +#ifndef __NVOC_CLASS_DisplayConsoleMemory_TYPEDEF__ +#define __NVOC_CLASS_DisplayConsoleMemory_TYPEDEF__ +typedef struct DisplayConsoleMemory DisplayConsoleMemory; +#endif /* __NVOC_CLASS_DisplayConsoleMemory_TYPEDEF__ */ + +#ifndef __nvoc_class_id_DisplayConsoleMemory +#define __nvoc_class_id_DisplayConsoleMemory 0x0f96d3 +#endif /* __nvoc_class_id_DisplayConsoleMemory */ + + struct KernelHead; #ifndef __NVOC_CLASS_KernelHead_TYPEDEF__ @@ -1380,6 +1392,7 @@ typedef struct OBJGMMU OBJGMMU; #define ENG_DPU MKENGDESC(classId(OBJDPU), 0) #define ENG_FAN MKENGDESC(classId(Fan), 0) #define ENG_INST MKENGDESC(classId(DisplayInstanceMemory), 0) +#define ENG_CONSOLE_MEM MKENGDESC(classId(DisplayConsoleMemory), 0) #define ENG_KERNEL_HEAD MKENGDESC(classId(KernelHead), 0) #define ENG_VOLT MKENGDESC(classId(OBJVOLT), 0) #define ENG_INTR MKENGDESC(classId(Intr), 0) diff --git a/src/nvidia/generated/g_kern_disp_nvoc.h b/src/nvidia/generated/g_kern_disp_nvoc.h index 46f5150..1c56836 100644 --- a/src/nvidia/generated/g_kern_disp_nvoc.h +++ b/src/nvidia/generated/g_kern_disp_nvoc.h @@ -115,6 +115,7 @@ struct KernelDisplay { NvBool PDB_PROP_KDISP_BUG_2089053_SERIALIZE_AGGRESSIVE_VBLANKS_ONLY_ON_HMD_ACTIVE; NvBool PDB_PROP_KDISP_IN_AWAKEN_INTR; struct DisplayInstanceMemory *pInst; + struct DisplayConsoleMemory *pConsoleMem; struct KernelHead *pKernelHead[4]; const KernelDisplayStaticInfo *pStaticInfo; NvBool bWarPurgeSatellitesOnCoreFree; @@ -208,6 +209,33 @@ static inline void kdispDestructInstMem(struct KernelDisplay *pKernelDisplay) { #define kdispDestructInstMem_HAL(pKernelDisplay) kdispDestructInstMem(pKernelDisplay) +NV_STATUS kdispConstructConsoleMem_IMPL(struct KernelDisplay *pKernelDisplay); + + +#ifdef __nvoc_kern_disp_h_disabled +static inline NV_STATUS kdispConstructConsoleMem(struct KernelDisplay *pKernelDisplay) { + NV_ASSERT_FAILED_PRECOMP("KernelDisplay was disabled!"); + return NV_ERR_NOT_SUPPORTED; +} +#else //__nvoc_kern_disp_h_disabled +#define kdispConstructConsoleMem(pKernelDisplay) kdispConstructConsoleMem_IMPL(pKernelDisplay) +#endif //__nvoc_kern_disp_h_disabled + +#define kdispConstructConsoleMem_HAL(pKernelDisplay) kdispConstructConsoleMem(pKernelDisplay) + +void kdispDestructConsoleMem_IMPL(struct KernelDisplay *pKernelDisplay); + + +#ifdef __nvoc_kern_disp_h_disabled +static inline void kdispDestructConsoleMem(struct KernelDisplay *pKernelDisplay) { + NV_ASSERT_FAILED_PRECOMP("KernelDisplay was disabled!"); +} +#else //__nvoc_kern_disp_h_disabled +#define kdispDestructConsoleMem(pKernelDisplay) kdispDestructConsoleMem_IMPL(pKernelDisplay) +#endif //__nvoc_kern_disp_h_disabled + +#define kdispDestructConsoleMem_HAL(pKernelDisplay) kdispDestructConsoleMem(pKernelDisplay) + NV_STATUS kdispSelectClass_v03_00_KERNEL(struct OBJGPU *pGpu, struct KernelDisplay *pKernelDisplay, NvU32 swClass); diff --git a/src/nvidia/generated/g_resource_fwd_decls_nvoc.h b/src/nvidia/generated/g_resource_fwd_decls_nvoc.h index 3ac2ada..a7779e8 100644 --- a/src/nvidia/generated/g_resource_fwd_decls_nvoc.h +++ b/src/nvidia/generated/g_resource_fwd_decls_nvoc.h @@ -387,6 +387,17 @@ typedef struct SyncpointMemory SyncpointMemory; #define __nvoc_class_id_SyncpointMemory 0x529def #endif /* __nvoc_class_id_SyncpointMemory */ +struct ConsoleMemory; + +#ifndef __NVOC_CLASS_ConsoleMemory_TYPEDEF__ +#define __NVOC_CLASS_ConsoleMemory_TYPEDEF__ +typedef struct ConsoleMemory ConsoleMemory; +#endif /* __NVOC_CLASS_ConsoleMemory_TYPEDEF__ */ + +#ifndef __nvoc_class_id_ConsoleMemory +#define __nvoc_class_id_ConsoleMemory 0xaac69e +#endif /* __nvoc_class_id_ConsoleMemory */ + struct DispSfUser; #ifndef __NVOC_CLASS_DispSfUser_TYPEDEF__ @@ -502,6 +513,7 @@ struct NVOCFwdDeclHack { struct SystemMemory *PRIVATE_FIELD(SystemMemory_NV01_MEMORY_SYSTEM); struct OsDescMemory *PRIVATE_FIELD(OsDescMemory_NV01_MEMORY_SYSTEM_OS_DESCRIPTOR); struct SyncpointMemory *PRIVATE_FIELD(SyncpointMemory_NV01_MEMORY_SYNCPOINT); + struct ConsoleMemory *PRIVATE_FIELD(ConsoleMemory_NV01_MEMORY_FRAMEBUFFER_CONSOLE); struct DispSfUser *PRIVATE_FIELD(DispSfUser_NVC671_DISP_SF_USER); struct NvDispApi *PRIVATE_FIELD(NvDispApi_NVC670_DISPLAY); struct DispSwObj *PRIVATE_FIELD(DispSwObj_NVC372_DISPLAY_SW); diff --git a/src/nvidia/generated/rmconfig.h b/src/nvidia/generated/rmconfig.h index e6c95b9..ef38004 100644 --- a/src/nvidia/generated/rmconfig.h +++ b/src/nvidia/generated/rmconfig.h @@ -303,7 +303,7 @@ #define RMCFG_CLASS_NV01_MEMORY_SYNCPOINT 1 #define RMCFG_CLASS_NV01_MEMORY_SYSTEM_OS_DESCRIPTOR 1 #define RMCFG_CLASS_NV01_MEMORY_DEVICELESS 0 -#define RMCFG_CLASS_NV01_MEMORY_FRAMEBUFFER_CONSOLE 0 +#define RMCFG_CLASS_NV01_MEMORY_FRAMEBUFFER_CONSOLE 1 #define RMCFG_CLASS_NV01_MEMORY_HW_RESOURCES 0 #define RMCFG_CLASS_NV01_MEMORY_LIST_SYSTEM 0 #define RMCFG_CLASS_NV01_MEMORY_LIST_FBMEM 0 @@ -528,6 +528,7 @@ #define RMCFG_MODULE_SF 1 // Display component: Serial Formatter, output protocol formatting #define RMCFG_MODULE_DISPLAY_INSTANCE_MEMORY 1 #define RMCFG_MODULE_KERNEL_HEAD 1 +#define RMCFG_MODULE_DISPLAY_CONSOLE_MEMORY 1 #define RMCFG_MODULE_INTR 0 #define RMCFG_MODULE_MC 0 #define RMCFG_MODULE_KERNEL_MC 0 // Master Control-related code needed in Kernel RM diff --git a/src/nvidia/inc/kernel/gpu/disp/console_mem/disp_console_mem.h b/src/nvidia/inc/kernel/gpu/disp/console_mem/disp_console_mem.h new file mode 100644 index 0000000..2bc1760 --- /dev/null +++ b/src/nvidia/inc/kernel/gpu/disp/console_mem/disp_console_mem.h @@ -0,0 +1,3 @@ + +#include "g_disp_console_mem_nvoc.h" + diff --git a/src/nvidia/inc/kernel/mem_mgr/console_mem.h b/src/nvidia/inc/kernel/mem_mgr/console_mem.h new file mode 100644 index 0000000..a9582ae --- /dev/null +++ b/src/nvidia/inc/kernel/mem_mgr/console_mem.h @@ -0,0 +1,3 @@ + +#include "g_console_mem_nvoc.h" + diff --git a/src/nvidia/src/kernel/gpu/disp/console_mem/disp_console_mem.c b/src/nvidia/src/kernel/gpu/disp/console_mem/disp_console_mem.c new file mode 100644 index 0000000..c7524db --- /dev/null +++ b/src/nvidia/src/kernel/gpu/disp/console_mem/disp_console_mem.c @@ -0,0 +1,224 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +/**************************** Instmem Routines *****************************\ +* * +* Display console memory object function Definitions. * +* * +\***************************************************************************/ + +#define RM_STRICT_CONFIG_EMIT_DISP_ENGINE_DEFINITIONS 0 + +#include "gpu/disp/kern_disp.h" +#include "gpu/disp/console_mem/disp_console_mem.h" +#include "gpu/mem_mgr/mem_mgr.h" +#include "os/nv_memory_type.h" + + +/*! @brief Constructor */ +NV_STATUS +consolememConstruct_IMPL +( + DisplayConsoleMemory *pConsoleMem +) +{ + pConsoleMem->pConsoleMem = NULL; + pConsoleMem->pConsoleMemDesc = NULL; + + return NV_OK; +} + + +/*! @brief destructor */ +void +consolememDestruct_IMPL +( + DisplayConsoleMemory *pConsoleMem +) +{ + // Free up the console mem descriptors + memdescDestroy(pConsoleMem->pConsoleMemDesc); + pConsoleMem->pConsoleMemDesc = NULL; +} + +/*! @brief Set console memory params */ +void +consolememSetMemory_IMPL +( + OBJGPU *pGpu, + DisplayConsoleMemory *pConsoleMem, + NvU64 memoryRegionBaseAddress, + NvU64 memoryRegionSize +) +{ + pConsoleMem->consoleMemBaseAddress = memoryRegionBaseAddress; + pConsoleMem->consoleMemSize = memoryRegionSize; +} + +/*! @brief Initialize console memory descriptor */ +static NV_STATUS +consolememInitMemDesc +( + OBJGPU *pGpu, + DisplayConsoleMemory *pConsoleMem +) +{ + NV_STATUS status = NV_OK; + MEMORY_DESCRIPTOR *pMemDesc = NULL; + RmPhysAddr *pPteArray = NULL; + + if (pGpu->getProperty(pGpu, PDB_PROP_GPU_TEGRA_SOC_NVDISPLAY)) + { + // + // FB reserved memory logic not be getting called for Tegra system memory scanout. + // So as ConsoleMem Desc is not getting initialized, currently hardcoding + // dispConsoleMemAttr to NV_MEMORY_UNCACHED this needs to be set based on system configuration/registry parameter. + // + pConsoleMem->consoleMemAttr = NV_MEMORY_UNCACHED; + pConsoleMem->consoleMemAddrSpace = ADDR_SYSMEM; + } + else + { + NV_PRINTF(LEVEL_ERROR, "DisplayConsoleMemory is not supported for non Tegra SOC Display yet.\n"); + NV_ASSERT(0); + status = NV_ERR_NOT_SUPPORTED; + goto exit; + } + + switch (pConsoleMem->consoleMemAddrSpace) + { + default: + case ADDR_FBMEM: + { + NV_PRINTF(LEVEL_ERROR, "DisplayConsoleMemory is not supported for ADDR_FBMEM address space yet.\n"); + NV_ASSERT(0); + status = NV_ERR_NOT_SUPPORTED; + } + break; + + case ADDR_SYSMEM: + { + if (pConsoleMem->consoleMemSize > 0) + { + NV_CHECK_OK_OR_GOTO(status, LEVEL_ERROR, + memdescCreate(&pConsoleMem->pConsoleMemDesc, pGpu, + pConsoleMem->consoleMemSize, + RM_PAGE_SIZE, + NV_MEMORY_CONTIGUOUS, pConsoleMem->consoleMemAddrSpace, + pConsoleMem->consoleMemAttr, + MEMDESC_FLAGS_SKIP_RESOURCE_COMPUTE), + exit); + + pMemDesc = pConsoleMem->pConsoleMemDesc; + memdescSetAddress(pMemDesc, NvP64_NULL); + memdescSetMemData(pMemDesc, NULL, NULL); + memdescSetFlag(pMemDesc, MEMDESC_FLAGS_SKIP_IOMMU_MAPPING, NV_TRUE); + pPteArray = memdescGetPteArray(pMemDesc, AT_GPU); + pPteArray[0] = pConsoleMem->consoleMemBaseAddress; + } + } + break; + } + +exit: + // Clean-up is handled by the caller + return status; +} + +/*! @brief Free all memory allocations done for display console memory */ +static void +consolememDestroy +( + OBJGPU *pGpu, + DisplayConsoleMemory *pConsoleMem +) +{ + // Free up the console mem descriptors + memdescDestroy(pConsoleMem->pConsoleMemDesc); + pConsoleMem->pConsoleMemDesc = NULL; +} + +NV_STATUS +consolememStateInitLocked_IMPL +( + OBJGPU *pGpu, + DisplayConsoleMemory *pConsoleMem +) +{ + NV_STATUS status = NV_OK; + // Memory descriptor has to be created in StateInit call and not in Construct call + // because console memory region parameters are read from linux kernel after + // construct call. + NV_CHECK_OK_OR_GOTO(status, LEVEL_ERROR, + consolememInitMemDesc(pGpu, pConsoleMem), exit); + +exit: + if (status != NV_OK) + { + consolememDestroy(pGpu, pConsoleMem); + } + + return status; +} + +void +consolememStateDestroy_IMPL +( + OBJGPU *pGpu, + DisplayConsoleMemory *pConsoleMem +) +{ + consolememDestroy(pGpu, pConsoleMem); +} + +NV_STATUS +consolememStateLoad_IMPL +( + OBJGPU *pGpu, + DisplayConsoleMemory *pConsoleMem, + NvU32 flags +) +{ + return NV_OK; +} + +NV_STATUS +consolememStateUnload_IMPL +( + OBJGPU *pGpu, + DisplayConsoleMemory *pConsoleMem, + NvU32 flags +) +{ + return NV_OK; +} + +PMEMORY_DESCRIPTOR +consolememGetMemDesc_IMPL +( + OBJGPU *pGpu, + DisplayConsoleMemory *pConsoleMem +) +{ + return pConsoleMem->pConsoleMemDesc; +} diff --git a/src/nvidia/src/kernel/gpu/disp/kern_disp.c b/src/nvidia/src/kernel/gpu/disp/kern_disp.c index 434b45c..0351895 100644 --- a/src/nvidia/src/kernel/gpu/disp/kern_disp.c +++ b/src/nvidia/src/kernel/gpu/disp/kern_disp.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2021-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2021-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -39,6 +39,7 @@ #include "gpu/device/device.h" #include "gpu/disp/kern_disp.h" #include "gpu/disp/inst_mem/disp_inst_mem.h" +#include "gpu/disp/console_mem/disp_console_mem.h" #include "gpu/disp/head/kernel_head.h" #include "gpu/disp/disp_objs.h" #include "gpu_mgr/gpu_mgr.h" @@ -111,6 +112,13 @@ kdispConstructEngine_IMPL(OBJGPU *pGpu, return status; } + pKernelDisplay->pConsoleMem = NULL; + status = kdispConstructConsoleMem_HAL(pKernelDisplay); + if (status != NV_OK) + { + return status; + } + status = kdispConstructKhead(pKernelDisplay); // We defer checking whether DISP has been disabled some other way until @@ -127,6 +135,7 @@ kdispDestruct_IMPL { // Destroy children kdispDestructInstMem_HAL(pKernelDisplay); + kdispDestructConsoleMem_HAL(pKernelDisplay); kdispDestructKhead(pKernelDisplay); } @@ -161,6 +170,37 @@ kdispDestructInstMem_IMPL pKernelDisplay->pInst = NULL; } +/*! Constructor for DisplayConsoleMemory */ +NV_STATUS +kdispConstructConsoleMem_IMPL +( + KernelDisplay *pKernelDisplay +) +{ + NV_STATUS status; + DisplayConsoleMemory *pConsole; + + status = objCreate(&pConsole, pKernelDisplay, DisplayConsoleMemory); + if (status != NV_OK) + { + return status; + } + pKernelDisplay->pConsoleMem = pConsole; + + return NV_OK; +} + +/*! Destructor for DisplayConsoleMemory */ +void +kdispDestructConsoleMem_IMPL +( + KernelDisplay *pKernelDisplay +) +{ + objDelete(pKernelDisplay->pConsoleMem); + pKernelDisplay->pConsoleMem = NULL; +} + /*! Constructor for Kernel head */ NV_STATUS kdispConstructKhead_IMPL @@ -448,6 +488,12 @@ kdispStateInitLocked_IMPL(OBJGPU *pGpu, instmemStateInitLocked(pGpu, pKernelDisplay->pInst), exit); } + if (pKernelDisplay->pConsoleMem != NULL) + { + NV_CHECK_OK_OR_GOTO(status, LEVEL_ERROR, + consolememStateInitLocked(pGpu, pKernelDisplay->pConsoleMem), exit); + } + if (pKernelDisplay->getProperty(pKernelDisplay, PDB_PROP_KDISP_IMP_ENABLE)) { // NOTE: Fills IMP parameters and populate those to disp object in Tegra @@ -469,7 +515,10 @@ kdispStateDestroy_IMPL(OBJGPU *pGpu, { instmemStateDestroy(pGpu, pKernelDisplay->pInst); } - + if (pKernelDisplay->pConsoleMem != NULL) + { + consolememStateDestroy(pGpu, pKernelDisplay->pConsoleMem); + } portMemFree((void*) pKernelDisplay->pStaticInfo); pKernelDisplay->pStaticInfo = NULL; diff --git a/src/nvidia/src/kernel/gpu/gpu.c b/src/nvidia/src/kernel/gpu/gpu.c index 2fffbf6..8b0e721 100644 --- a/src/nvidia/src/kernel/gpu/gpu.c +++ b/src/nvidia/src/kernel/gpu/gpu.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 1993-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 1993-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -31,6 +31,7 @@ #include "gpu/gpu.h" #include "gpu/disp/kern_disp.h" #include "gpu/disp/inst_mem/disp_inst_mem.h" +#include "gpu/disp/console_mem/disp_console_mem.h" #include "gpu/subdevice/subdevice.h" #include "gpu/eng_desc.h" #include "nv_ref.h" @@ -3807,6 +3808,13 @@ gpuInitDispIpHal_IMPL pRmHalspecOwner); } + void __nvoc_init_funcTable_DisplayConsoleMemory(DisplayConsoleMemory *, RmHalspecOwner *); + void __nvoc_init_dataField_DisplayConsoleMemory(DisplayConsoleMemory *, RmHalspecOwner *); + __nvoc_init_funcTable_DisplayConsoleMemory(KERNEL_DISPLAY_GET_CONSOLE_MEM(pKernelDisplay), + pRmHalspecOwner); + __nvoc_init_dataField_DisplayConsoleMemory(KERNEL_DISPLAY_GET_CONSOLE_MEM(pKernelDisplay), + pRmHalspecOwner); + return NV_OK; } diff --git a/src/nvidia/src/kernel/mem_mgr/console_mem.c b/src/nvidia/src/kernel/mem_mgr/console_mem.c new file mode 100644 index 0000000..be1e9c8 --- /dev/null +++ b/src/nvidia/src/kernel/mem_mgr/console_mem.c @@ -0,0 +1,98 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2018-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#include "mem_mgr_internal.h" +#include "mem_mgr/console_mem.h" +#include "gpu/mem_mgr/mem_desc.h" +#include +#include +#include "os/os.h" +#include "gpu/mem_mgr/mem_mgr.h" +#include "rmapi/client.h" +#include "virtualization/hypervisor/hypervisor.h" + +#include "class/cl003e.h" // NV01_MEMORY_SYSTEM +#include "class/cl0040.h" // NV01_MEMORY_LOCAL_USER + +static PMEMORY_DESCRIPTOR +_getDisplayConsoleMemDesc +( + OBJGPU *pGpu +) +{ + MEMORY_DESCRIPTOR *pMemDesc = NULL; + + KernelDisplay *pKernelDisplay = GPU_GET_KERNEL_DISPLAY(pGpu); + DisplayConsoleMemory *pConsoleMem = KERNEL_DISPLAY_GET_CONSOLE_MEM(pKernelDisplay); + + pMemDesc = consolememGetMemDesc(pGpu, pConsoleMem); + + return pMemDesc; +} + +NV_STATUS +conmemConstruct_IMPL +( + ConsoleMemory *pConsoleMemory, + CALL_CONTEXT *pCallContext, + RS_RES_ALLOC_PARAMS_INTERNAL *pParams +) +{ + NV_STATUS status = NV_OK; + Memory *pMemory = staticCast(pConsoleMemory, Memory); + OBJGPU *pGpu = pMemory->pGpu; + MEMORY_DESCRIPTOR *pMemDesc = _getDisplayConsoleMemDesc(pGpu); + + NV_ASSERT_OR_RETURN(RMCFG_FEATURE_KERNEL_RM, NV_ERR_NOT_SUPPORTED); + + // Copy-construction has already been done by the base Memory class + if (RS_IS_COPY_CTOR(pParams)) + return NV_OK; + + if (pMemDesc == NULL) + { + return NV_ERR_INVALID_ARGUMENT; + } + + NV_ASSERT(pMemDesc->Allocated == 0); + memdescAddRef(pMemDesc); + pMemDesc->DupCount++; + + status = memConstructCommon(pMemory, NV01_MEMORY_SYSTEM, 0, pMemDesc, + 0, NULL, 0, 0, 0, 0, NVOS32_MEM_TAG_NONE, + (HWRESOURCE_INFO *)NULL); + if (status != NV_OK) + { + memdescDestroy(pMemDesc); + } + return status; +} + +NvBool +conmemCanCopy_IMPL +( + ConsoleMemory *pConsoleMemory +) +{ + return NV_TRUE; +} diff --git a/src/nvidia/src/kernel/rmapi/resource_list.h b/src/nvidia/src/kernel/rmapi/resource_list.h index 873e4e2..96af6d4 100644 --- a/src/nvidia/src/kernel/rmapi/resource_list.h +++ b/src/nvidia/src/kernel/rmapi/resource_list.h @@ -181,6 +181,16 @@ RS_ENTRY( /* Resource Free Priority */ RS_FREE_PRIORITY_DEFAULT, /* Flags */ RS_FLAGS_ALLOC_PRIVILEGED | RS_FLAGS_ACQUIRE_GPU_GROUP_LOCK, /* Required Access Rights */ RS_ACCESS_NONE +) +RS_ENTRY( + /* External Class */ NV01_MEMORY_FRAMEBUFFER_CONSOLE, + /* Internal Class */ ConsoleMemory, + /* Multi-Instance */ NV_TRUE, + /* Parents */ RS_LIST(classId(Device)), + /* Alloc Param Info */ RS_NONE, + /* Resource Free Priority */ RS_FREE_PRIORITY_DEFAULT, + /* Flags */ RS_FLAGS_ALLOC_PRIVILEGED | RS_FLAGS_ACQUIRE_GPUS_LOCK, + /* Required Access Rights */ RS_ACCESS_NONE ) /* Subdevice Children: */ RS_ENTRY( diff --git a/src/nvidia/srcs.mk b/src/nvidia/srcs.mk index 2d61c23..68ae7b0 100644 --- a/src/nvidia/srcs.mk +++ b/src/nvidia/srcs.mk @@ -5,11 +5,13 @@ SRCS += generated/g_binary_api_nvoc.c SRCS += generated/g_chips2halspec_nvoc.c SRCS += generated/g_client_nvoc.c SRCS += generated/g_client_resource_nvoc.c +SRCS += generated/g_console_mem_nvoc.c SRCS += generated/g_context_dma_nvoc.c SRCS += generated/g_dce_client_nvoc.c SRCS += generated/g_device_nvoc.c SRCS += generated/g_disp_capabilities_nvoc.c SRCS += generated/g_disp_channel_nvoc.c +SRCS += generated/g_disp_console_mem_nvoc.c SRCS += generated/g_disp_inst_mem_nvoc.c SRCS += generated/g_disp_objs_nvoc.c SRCS += generated/g_disp_sf_user_nvoc.c @@ -68,6 +70,7 @@ SRCS += arch/nvalloc/unix/src/osunix.c SRCS += arch/nvalloc/unix/src/power-management-tegra.c SRCS += arch/nvalloc/unix/src/registry.c SRCS += arch/nvalloc/unix/src/rmobjexportimport.c +SRCS += arch/nvalloc/unix/src/unix_console.c SRCS += interface/deprecated/rmapi_deprecated_utils.c SRCS += interface/rmapi/src/g_finn_rm_api.c SRCS += src/kernel/core/hal/hal.c @@ -90,6 +93,7 @@ SRCS += src/kernel/gpu/device_ctrl.c SRCS += src/kernel/gpu/device_share.c SRCS += src/kernel/gpu/disp/arch/v03/kern_disp_0300.c SRCS += src/kernel/gpu/disp/arch/v04/kern_disp_0402.c +SRCS += src/kernel/gpu/disp/console_mem/disp_console_mem.c SRCS += src/kernel/gpu/disp/disp_capabilities.c SRCS += src/kernel/gpu/disp/disp_channel.c SRCS += src/kernel/gpu/disp/disp_common_kern_ctrl_minimal.c @@ -128,6 +132,7 @@ SRCS += src/kernel/gpu_mgr/gpu_db.c SRCS += src/kernel/gpu_mgr/gpu_group.c SRCS += src/kernel/gpu_mgr/gpu_mgmt_api.c SRCS += src/kernel/gpu_mgr/gpu_mgr.c +SRCS += src/kernel/mem_mgr/console_mem.c SRCS += src/kernel/mem_mgr/io_vaspace.c SRCS += src/kernel/mem_mgr/mem.c SRCS += src/kernel/mem_mgr/os_desc_mem.c