Updating prebuilts and/or headers

c2e810fc3453d74ee0493168dbf7981ba482acd3 - NVIDIA-kernel-module-source-TempVersion/SECURITY.md
7d577fdb9594ae572ff38fdda682a4796ab832ca - NVIDIA-kernel-module-source-TempVersion/COPYING
12f1806bdc25917299525e0e48815306159de132 - NVIDIA-kernel-module-source-TempVersion/Makefile
60176067d89204db2a337983144481c56d94baf2 - NVIDIA-kernel-module-source-TempVersion/README.md
4f4410c3c8db46e5a98d7a35f7d909a49de6cb43 - NVIDIA-kernel-module-source-TempVersion/kernel-open/Makefile
90d4457b6fec29378645d5932ad82d706942f4a6 - NVIDIA-kernel-module-source-TempVersion/kernel-open/conftest.sh
a0a15eb341be905ced2a09b8c4feb8bb43b4fb39 - NVIDIA-kernel-module-source-TempVersion/kernel-open/Kbuild
0b1508742a1c5a04b6c3a4be1b48b506f4180848 - NVIDIA-kernel-module-source-TempVersion/kernel-open/dkms.conf
1d17329caf26cdf931122b3c3b7edf4932f43c38 - NVIDIA-kernel-module-source-TempVersion/kernel-open/common/inc/nv-msi.h
88399279bd5e31b6e77cb32c7ef6220ce529526b - NVIDIA-kernel-module-source-TempVersion/kernel-open/common/inc/nv-hypervisor.h
60ef64c0f15526ae2d786e5cec07f28570f0663b - NVIDIA-kernel-module-source-TempVersion/kernel-open/common/inc/conftest.h
ea98628370602119afb1a065ff954784757ddb10 - NVIDIA-kernel-module-source-TempVersion/kernel-open/common/inc/os_dsi_panel_props.h
c06b2748cd7c8f86b5864d5e9abe6ecf0ab622f0 - NVIDIA-kernel-module-source-TempVersion/kernel-open/common/inc/nv-hash.h
423282211355a8cb20bff268166885ac90e2986c - NVIDIA-kernel-module-source-TempVersion/kernel-open/common/inc/nv_uvm_interface.h
c75bfc368c6ce3fc2c1a0c5062834e90d822b365 - NVIDIA-kernel-module-source-TempVersion/kernel-open/common/inc/nv-memdbg.h
35da37c070544f565d0f1de82abc7569b5df06af - NVIDIA-kernel-module-source-TempVersion/kernel-open/common/inc/nv_firmware_types.h
82940edf4650b9be67275d3a360ef4e63387a0a7 - NVIDIA-kernel-module-source-TempVersion/kernel-open/common/inc/cpuopsys.h
1d8b347e4b92c340a0e9eac77e0f63b9fb4ae977 - NVIDIA-kernel-module-source-TempVersion/kernel-open/common/inc/nv-ioctl-numbers.h
4b7414705ce10f0a1e312c36a43824b59d572661 - NVIDIA-kernel-module-source-TempVersion/kernel-open/common/inc/nvmisc.h
e4a4f57abb8769d204468b2f5000c81f5ea7c92f - NVIDIA-kernel-module-source-TempVersion/kernel-open/common/inc/nv-procfs.h
6337f595602bce9d76559de1be90553b52f405d8 - NVIDIA-kernel-module-source-TempVersion/kernel-open/common/inc/nv-proto.h
b249abc0a7d0c9889008e98cb2f8515a9d310b85 - NVIDIA-kernel-module-source-TempVersion/kernel-open/common/inc/nvgputypes.h
e20882a9b14f2bf887e7465d3f238e5ac17bc2f5 - NVIDIA-kernel-module-source-TempVersion/kernel-open/common/inc/nv_speculation_barrier.h
5c4c05e5a638888babb5a8af2f0a61c94ecd150b - NVIDIA-kernel-module-source-TempVersion/kernel-open/common/inc/nvkms-format.h
b4c5d759f035b540648117b1bff6b1701476a398 - NVIDIA-kernel-module-source-TempVersion/kernel-open/common/inc/nvCpuUuid.h
880e45b68b19fdb91ac94991f0e6d7fc3b406b1f - NVIDIA-kernel-module-source-TempVersion/kernel-open/common/inc/nv-pci-types.h
c45b2faf17ca2a205c56daa11e3cb9d864be2238 - NVIDIA-kernel-module-source-TempVersion/kernel-open/common/inc/nv-modeset-interface.h
349696856890bdbe76f457376648522b35f874ef - NVIDIA-kernel-module-source-TempVersion/kernel-open/common/inc/nvimpshared.h
003b2cbe3d82e467c09371aee86e48d65ae6c29b - NVIDIA-kernel-module-source-TempVersion/kernel-open/common/inc/nv-ioctl-numa.h
b642fb649ce2ba17f37c8aa73f61b38f99a74986 - NVIDIA-kernel-module-source-TempVersion/kernel-open/common/inc/nv-retpoline.h
1e7eec6561b04d2d21c3515987aaa116e9401c1f - NVIDIA-kernel-module-source-TempVersion/kernel-open/common/inc/nv-kernel-interface-api.h
3b12d770f8592b94a8c7774c372e80ad08c5774c - NVIDIA-kernel-module-source-TempVersion/kernel-open/common/inc/nvi2c.h
b02c378ac0521c380fc2403f0520949f785b1db6 - NVIDIA-kernel-module-source-TempVersion/kernel-open/common/inc/nv-dmabuf.h
3100c536eb4c81ae913b92d4bc5905e752301311 - NVIDIA-kernel-module-source-TempVersion/kernel-open/common/inc/os-interface.h
143051f69a53db0e7c5d2f846a9c14d666e264b4 - NVIDIA-kernel-module-source-TempVersion/kernel-open/common/inc/nv-kref.h
3a26838c4edd3525daa68ac6fc7b06842dc6fc07 - NVIDIA-kernel-module-source-TempVersion/kernel-open/common/inc/nv-gpu-info.h
7b2e2e6ff278acddc6980b330f68e374f38e0a6c - NVIDIA-kernel-module-source-TempVersion/kernel-open/common/inc/nv-timer.h
fdbaee144adb26c00776b802560e15f775ed5aef - NVIDIA-kernel-module-source-TempVersion/kernel-open/common/inc/nv-mm.h
befb2c0bf0a31b61be5469575ce3c73a9204f4e9 - NVIDIA-kernel-module-source-TempVersion/kernel-open/common/inc/nv_stdarg.h
80fcb510fad25cb7a017139f487da1843b7cfcbd - NVIDIA-kernel-module-source-TempVersion/kernel-open/common/inc/nv-lock.h
59d537c1d1b284a9d52277aff87c237e3ec2c99d - NVIDIA-kernel-module-source-TempVersion/kernel-open/common/inc/nv-procfs-utils.h
e3362c33fe6c7cdec013eceac31e8f6f38dc465f - NVIDIA-kernel-module-source-TempVersion/kernel-open/common/inc/nv_uvm_types.h
5d8de06378994201e91c2179d149c0edcd694900 - NVIDIA-kernel-module-source-TempVersion/kernel-open/common/inc/nvstatuscodes.h
95bf694a98ba78d5a19e66463b8adda631e6ce4c - NVIDIA-kernel-module-source-TempVersion/kernel-open/common/inc/nvstatus.h
4750735d6f3b334499c81d499a06a654a052713d - NVIDIA-kernel-module-source-TempVersion/kernel-open/common/inc/nv-caps.h
009cd8e2b7ee8c0aeb05dac44cc84fc8f6f37c06 - NVIDIA-kernel-module-source-TempVersion/kernel-open/common/inc/nvkms-kapi.h
d721fca5f2317b9b325dedcbfba51c00d0b23648 - NVIDIA-kernel-module-source-TempVersion/kernel-open/common/inc/nv-linux.h
4b1a6c372a531b0d3e0a4e9815dde74cb222447c - NVIDIA-kernel-module-source-TempVersion/kernel-open/common/inc/rm-gpu-ops.h
94ad0ba9fd6eb21445baec4fddd7c67a30cceefa - NVIDIA-kernel-module-source-TempVersion/kernel-open/common/inc/nv-pci.h
f3e0f71abf34300d322e313adcd4fcbde9aa6f87 - NVIDIA-kernel-module-source-TempVersion/kernel-open/common/inc/nv-kthread-q.h
256b5dc6f28738b3ce656c984f01d8f3e13e9faa - NVIDIA-kernel-module-source-TempVersion/kernel-open/common/inc/nv-pgprot.h
c57259130166701bf6d5e5bb1968397716d29fc0 - NVIDIA-kernel-module-source-TempVersion/kernel-open/common/inc/nv-platform.h
84e9b6cba7ba26ef4032666f769c5b43fa510aad - NVIDIA-kernel-module-source-TempVersion/kernel-open/common/inc/nv-list-helpers.h
df0420a5e3576e5a8b77a7bcefa6888ad62d6fd7 - NVIDIA-kernel-module-source-TempVersion/kernel-open/common/inc/nv.h
910255a4d92e002463175a28e38c3f24716fb654 - NVIDIA-kernel-module-source-TempVersion/kernel-open/common/inc/nvkms-api-types.h
42ece56d0459eb9f27b2497de48f08360c4f7f6b - NVIDIA-kernel-module-source-TempVersion/kernel-open/common/inc/nvlimits.h
4a8b7f3cc65fa530670f510796bef51cf8c4bb6b - NVIDIA-kernel-module-source-TempVersion/kernel-open/common/inc/nv-register-module.h
5fd1da24ae8263c43dc5dada4702564b6f0ca3d9 - NVIDIA-kernel-module-source-TempVersion/kernel-open/common/inc/dce_rm_client_ipc.h
906329ae5773732896e6fe94948f7674d0b04c17 - NVIDIA-kernel-module-source-TempVersion/kernel-open/common/inc/os_gpio.h
2f5fec803685c61c13f7955baaed056b5524652c - NVIDIA-kernel-module-source-TempVersion/kernel-open/common/inc/nv-ioctl.h
d25291d32caef187daf3589ce4976e4fa6bec70d - NVIDIA-kernel-module-source-TempVersion/kernel-open/common/inc/nv-time.h
8c041edbf4ed4fefdfd8006252cf542e34aa617b - NVIDIA-kernel-module-source-TempVersion/kernel-open/common/inc/nvtypes.h
cda75171ca7d8bf920aab6d56ef9aadec16fd15d - NVIDIA-kernel-module-source-TempVersion/kernel-open/common/inc/os/nv_memory_type.h
2ea1436104463c5e3d177e8574c3b4298976d37e - NVIDIA-kernel-module-source-TempVersion/kernel-open/nvidia-modeset/nvkms-ioctl.h
17855f638fd09abfec7d188e49b396793a9f6106 - NVIDIA-kernel-module-source-TempVersion/kernel-open/nvidia-modeset/nvkms.h
c181ab9960b0c01a7672bc1fe1bc8870f1e8856d - NVIDIA-kernel-module-source-TempVersion/kernel-open/nvidia-modeset/nvidia-modeset-linux.c
0b7e063481a0e195c6e91a4d3464c4792c684f03 - NVIDIA-kernel-module-source-TempVersion/kernel-open/nvidia-modeset/nv-kthread-q.c
07a2d5fa54ff88a0cb30c0945ef3c33ca630a490 - NVIDIA-kernel-module-source-TempVersion/kernel-open/nvidia-modeset/nvidia-modeset.Kbuild
7d108165b4a7b6a44ac21460ea3bf4381fb48c5b - NVIDIA-kernel-module-source-TempVersion/kernel-open/nvidia-modeset/nvidia-modeset-os-interface.h
8bedc7374d7a43250e49fb09139c511b489d45e3 - NVIDIA-kernel-module-source-TempVersion/kernel-open/nvidia/nv-pci-table.h
9a0f445fda73c69e1bee7f6b121cbed33fcb01bf - NVIDIA-kernel-module-source-TempVersion/kernel-open/nvidia/nv-mmap.c
c5cfba80ea122c9078f2d44f1538144747d7931b - NVIDIA-kernel-module-source-TempVersion/kernel-open/nvidia/nv.c
95ae148b016e4111122c2d9f8f004b53e78998f3 - NVIDIA-kernel-module-source-TempVersion/kernel-open/nvidia/nv-memdbg.c
24fd035338936c76fda8faeb0d8b1cd59875db92 - NVIDIA-kernel-module-source-TempVersion/kernel-open/nvidia/nvidia.Kbuild
3ee953312a6a246d65520fc4a65407f448d1d2b8 - NVIDIA-kernel-module-source-TempVersion/kernel-open/nvidia/nv-gpio.c
cded6e9b6324fd429b865173596c8e549a682bba - NVIDIA-kernel-module-source-TempVersion/kernel-open/nvidia/nv_uvm_interface.c
5f2e279a4abe0dabd478b1589be67df18de4b09d - NVIDIA-kernel-module-source-TempVersion/kernel-open/nvidia/nv-i2c.c
c1ebcfec42f7898dd9d909eacd439d288b80523f - NVIDIA-kernel-module-source-TempVersion/kernel-open/nvidia/os-mlock.c
d11ab03a617b29efcf00f85e24ebce60f91cf82c - NVIDIA-kernel-module-source-TempVersion/kernel-open/nvidia/nv-backlight.c
dc39c4ee87f4dc5f5ccc179a98e07ddb82bb8bce - NVIDIA-kernel-module-source-TempVersion/kernel-open/nvidia/nv-modeset-interface.c
7b1bd10726481626dd51f4eebb693794561c20f6 - NVIDIA-kernel-module-source-TempVersion/kernel-open/nvidia/nv-host1x.c
06e7ec77cd21c43f900984553a4960064753e444 - NVIDIA-kernel-module-source-TempVersion/kernel-open/nvidia/nv-platform-pm.c
d4f2cac6234e5ad337c254875a26d17372f28162 - NVIDIA-kernel-module-source-TempVersion/kernel-open/nvidia/os-interface.c
e903f50b2624f33807214973558b9ff380bd68e0 - NVIDIA-kernel-module-source-TempVersion/kernel-open/nvidia/nv-platform.c
805042e7cdb9663a0d3ca3064baeec8aa8eb3688 - NVIDIA-kernel-module-source-TempVersion/kernel-open/nvidia/nv-ibmnpu.c
c7f1aaa6a5f3a3cdf1e5f80adf40b3c9f185fb94 - NVIDIA-kernel-module-source-TempVersion/kernel-open/nvidia/nv-report-err.c
0b0ec8d75dfece909db55136731196162c4152d5 - NVIDIA-kernel-module-source-TempVersion/kernel-open/nvidia/nv-dmabuf.c
84d84563c003d3f568068e7322ce314387a6f579 - NVIDIA-kernel-module-source-TempVersion/kernel-open/nvidia/nv-caps.c
94c406f36836c3396b0ca08b4ff71496666b9c43 - NVIDIA-kernel-module-source-TempVersion/kernel-open/nvidia/os-usermap.c
fbae5663e3c278d8206d07ec6446ca4c2781795f - NVIDIA-kernel-module-source-TempVersion/kernel-open/nvidia/nv-ibmnpu.h
2c0d17f9babe897435c7dfa43adb96020f45da2b - NVIDIA-kernel-module-source-TempVersion/kernel-open/nvidia/nv-dsi-parse-panel-props.c
9b701fe42a0e87d62c58b15c553086a608e89f7b - NVIDIA-kernel-module-source-TempVersion/kernel-open/nvidia/nv-frontend.h
0ce95e5ed52d6d6ca2bb6aac33ca8f197145ec45 - NVIDIA-kernel-module-source-TempVersion/kernel-open/nvidia/nv-procfs-utils.c
cf90d9ea3abced81d182ab3c4161e1b5d3ad280d - NVIDIA-kernel-module-source-TempVersion/kernel-open/nvidia/nv-rsync.h
02b1936dd9a9e30141245209d79b8304b7f12eb9 - NVIDIA-kernel-module-source-TempVersion/kernel-open/nvidia/nv-cray.c
26c3971ea7afb4b7f237db9ab1c321c3de814518 - NVIDIA-kernel-module-source-TempVersion/kernel-open/nvidia/nv-p2p.c
218aac0c408be15523a2d0b70fdbdadd7e1a2e48 - NVIDIA-kernel-module-source-TempVersion/kernel-open/nvidia/nv-imp.c
6d4fbea733fdcd92fc6a8a5884e8bb359f9e8abd - NVIDIA-kernel-module-source-TempVersion/kernel-open/nvidia/rmp2pdefines.h
5ac10d9b20ccd37e1e24d4a81b8ac8f83db981e4 - NVIDIA-kernel-module-source-TempVersion/kernel-open/nvidia/nv-vtophys.c
9999872b1513360d8ecf6c0894f81c63e7d435e9 - NVIDIA-kernel-module-source-TempVersion/kernel-open/nvidia/nv-dma.c
fc566df59becef7bc7511ae62a9a97b1532a5af2 - NVIDIA-kernel-module-source-TempVersion/kernel-open/nvidia/nv-frontend.c
b71bf4426322ab59e78e2a1500509a5f4b2b71ab - NVIDIA-kernel-module-source-TempVersion/kernel-open/nvidia/nv-pat.h
a3626bf1b80a81c14408c5181e8bd27696df2caf - NVIDIA-kernel-module-source-TempVersion/kernel-open/nvidia/nv-pci.c
98c1be29932b843453567d4ada2f9912ea4523d7 - NVIDIA-kernel-module-source-TempVersion/kernel-open/nvidia/nv-vm.c
0b7e063481a0e195c6e91a4d3464c4792c684f03 - NVIDIA-kernel-module-source-TempVersion/kernel-open/nvidia/nv-kthread-q.c
61eadfa0f5b44a3d95e4d2d42d79321fc909c661 - NVIDIA-kernel-module-source-TempVersion/kernel-open/nvidia/nv-clk.c
4eee7319202366822e17d29ecec9f662c075e7ac - NVIDIA-kernel-module-source-TempVersion/kernel-open/nvidia/nv-rsync.c
495bcdff3847ff67ba4bbf9af23729eb66eed487 - NVIDIA-kernel-module-source-TempVersion/kernel-open/nvidia/nv-acpi.c
64f1c96761f6d9e7e02ab049dd0c810196568036 - NVIDIA-kernel-module-source-TempVersion/kernel-open/nvidia/nv-pat.c
d844fcaa5b02f1d1a753965a336287148b2ce689 - NVIDIA-kernel-module-source-TempVersion/kernel-open/nvidia/nv-p2p.h
dc165103f9196f5f9e97433ec32ef6dded86d4bb - NVIDIA-kernel-module-source-TempVersion/kernel-open/nvidia/os-registry.c
68d781e929d103e6fa55fa92b5d4f933fbfb6526 - NVIDIA-kernel-module-source-TempVersion/kernel-open/nvidia/nv-report-err.h
978d00b0d319c5ad5c0d3732b0e44f4ac0ac9a4c - NVIDIA-kernel-module-source-TempVersion/kernel-open/nvidia/nv_gpu_ops.h
fbfa2125b2bac1953af6d6fd99352898e516a686 - NVIDIA-kernel-module-source-TempVersion/kernel-open/nvidia/nv-msi.c
027fd0ab218eb98abe2b66d05f10b14ebb57e7a3 - NVIDIA-kernel-module-source-TempVersion/kernel-open/nvidia/nv-nano-timer.c
07f95171c241880c472a630d1ee38fb222be4d59 - NVIDIA-kernel-module-source-TempVersion/kernel-open/nvidia/nvidia-sources.Kbuild
a392fa800565c8345b07af5132db7078b914d59f - NVIDIA-kernel-module-source-TempVersion/kernel-open/nvidia/os-pci.c
ee894ec530acbd765c04aec93c1c312d42210aeb - NVIDIA-kernel-module-source-TempVersion/kernel-open/nvidia/nv-ipc-soc.c
f179d308e984ff44a82f6e1c6007624f1ac916ba - NVIDIA-kernel-module-source-TempVersion/kernel-open/nvidia/nv-procfs.c
e2b0e4ef01bb28ff6dcc10cb44570e185ce82df0 - NVIDIA-kernel-module-source-TempVersion/kernel-open/nvidia/nv-reg.h
7ac10bc4b3b1c5a261388c3f5f9ce0e9b35d7b44 - NVIDIA-kernel-module-source-TempVersion/kernel-open/nvidia/nv-usermap.c
d9221522e02e18b037b8929fbc075dc3c1e58654 - NVIDIA-kernel-module-source-TempVersion/kernel-open/nvidia/nv-pci-table.c
8bedc7374d7a43250e49fb09139c511b489d45e3 - NVIDIA-kernel-module-source-TempVersion/kernel-open/nvidia-drm/nv-pci-table.h
eca70b3b8146903ec678a60eebb0462e6ccf4569 - NVIDIA-kernel-module-source-TempVersion/kernel-open/nvidia-drm/nvidia-drm-encoder.h
3c9a013abdc787a1022b11099af4277c37cd666b - NVIDIA-kernel-module-source-TempVersion/kernel-open/nvidia-drm/nvidia-drm.Kbuild
e4bb0073eb9d6f965923bb9874e4714518850a27 - NVIDIA-kernel-module-source-TempVersion/kernel-open/nvidia-drm/nvidia-drm-connector.h
99642b76e9a84b5a1d2e2f4a8c7fb7bcd77a44fd - NVIDIA-kernel-module-source-TempVersion/kernel-open/nvidia-drm/nvidia-drm.h
8b2063f0cc2e328f4f986c2ce556cfb626c89810 - NVIDIA-kernel-module-source-TempVersion/kernel-open/nvidia-drm/nvidia-drm-utils.c
6528efa1f8061678b8543c5c0be8761cab860858 - NVIDIA-kernel-module-source-TempVersion/kernel-open/nvidia-drm/nvidia-drm-modeset.h
ab63f2a971db8bf10585b1a05fe0e3ca180ad6c7 - NVIDIA-kernel-module-source-TempVersion/kernel-open/nvidia-drm/nvidia-drm-os-interface.h
40b5613d1fbbe6b74bff67a5d07974ad321f75f0 - NVIDIA-kernel-module-source-TempVersion/kernel-open/nvidia-drm/nvidia-drm-utils.h
2911436a80d67074106c507871f4b480aa307237 - NVIDIA-kernel-module-source-TempVersion/kernel-open/nvidia-drm/nvidia-drm-helper.c
8c95aa7ab01dd928974ce7880a532557209bd8e0 - NVIDIA-kernel-module-source-TempVersion/kernel-open/nvidia-drm/nvidia-drm-gem.h
fa8d8d10ae773bb7db3b3ce1df545de0e04c937e - NVIDIA-kernel-module-source-TempVersion/kernel-open/nvidia-drm/nvidia-drm-connector.c
23586447526d9ffedd7878b6cf5ba00139fadb5e - NVIDIA-kernel-module-source-TempVersion/kernel-open/nvidia-drm/nvidia-drm-gem-user-memory.h
cbcd6e13d84ea6b52db12eda98be38e321888eb0 - NVIDIA-kernel-module-source-TempVersion/kernel-open/nvidia-drm/nvidia-drm-prime-fence.h
a7bc26c1078e95f9ff49c164f3652787adf1fef3 - NVIDIA-kernel-module-source-TempVersion/kernel-open/nvidia-drm/nvidia-drm-modeset.c
bb1f2105d19b50634d46a92ade7fc5f709ec25d3 - NVIDIA-kernel-module-source-TempVersion/kernel-open/nvidia-drm/nvidia-drm-crtc.c
c8982ace6fc79f75c092662902c0c61371195f0c - NVIDIA-kernel-module-source-TempVersion/kernel-open/nvidia-drm/nvidia-drm-linux.c
66b33e4ac9abe09835635f6776c1222deefad741 - NVIDIA-kernel-module-source-TempVersion/kernel-open/nvidia-drm/nvidia-drm-fb.h
6d65ea9f067e09831a8196022bfe00a145bec270 - NVIDIA-kernel-module-source-TempVersion/kernel-open/nvidia-drm/nvidia-drm-gem-dma-buf.h
45ec9fd1abfe9a0c7f9ffaf665014cec89c9e7e6 - NVIDIA-kernel-module-source-TempVersion/kernel-open/nvidia-drm/nvidia-drm-crtc.h
7129c765da5bfb77788441fed39b46dc7dc0fa8e - NVIDIA-kernel-module-source-TempVersion/kernel-open/nvidia-drm/nvidia-drm-gem-nvkms-memory.c
59bb05ef214b5c5f2fe3cf70142dabd47ea70650 - NVIDIA-kernel-module-source-TempVersion/kernel-open/nvidia-drm/nvidia-drm-ioctl.h
ef03d0ae581cc0326abe6054249791f8c0faa9a8 - NVIDIA-kernel-module-source-TempVersion/kernel-open/nvidia-drm/nvidia-drm-prime-fence.c
044071d60c8cc8ea66c6caaf1b70fe01c4081ad3 - NVIDIA-kernel-module-source-TempVersion/kernel-open/nvidia-drm/nvidia-drm-conftest.h
708d02c8bcdfb12e4d55896e667821357c8251ec - NVIDIA-kernel-module-source-TempVersion/kernel-open/nvidia-drm/nvidia-drm-priv.h
dc0fe38909e2f38e919495b7b4f21652a035a3ee - NVIDIA-kernel-module-source-TempVersion/kernel-open/nvidia-drm/nvidia-drm.c
e4efab24f90d397c270568abb337ab815a447fec - NVIDIA-kernel-module-source-TempVersion/kernel-open/nvidia-drm/nvidia-dma-fence-helper.h
b775af5899366845f9b87393d17a0ab0f1f6a725 - NVIDIA-kernel-module-source-TempVersion/kernel-open/nvidia-drm/nvidia-drm-gem.c
1e05d0ff4e51a10fa3fcd6519dc915bf13aa69c0 - NVIDIA-kernel-module-source-TempVersion/kernel-open/nvidia-drm/nvidia-drm-helper.h
492a1b0b02dcd2d60f05ac670daeeddcaa4b0da5 - NVIDIA-kernel-module-source-TempVersion/kernel-open/nvidia-drm/nvidia-dma-resv-helper.h
892cac6dd51ccfde68b3c29a5676504f93ee8cd7 - NVIDIA-kernel-module-source-TempVersion/kernel-open/nvidia-drm/nvidia-drm-format.c
355126d65ea1472ce3b278066811d4fb764354ec - NVIDIA-kernel-module-source-TempVersion/kernel-open/nvidia-drm/nvidia-drm-gem-user-memory.c
5209eba37913f5d621a13091783622759706e6e3 - NVIDIA-kernel-module-source-TempVersion/kernel-open/nvidia-drm/nvidia-drm-fb.c
e362c64aa67b47becdbf5c8ba2a245e135adeedf - NVIDIA-kernel-module-source-TempVersion/kernel-open/nvidia-drm/nvidia-drm-gem-dma-buf.c
9a882b31b2acc9e1ad3909c0061eee536e648aae - NVIDIA-kernel-module-source-TempVersion/kernel-open/nvidia-drm/nvidia-drm-drv.h
5008845a531207899830bcf4568c3463ad0ea6bc - NVIDIA-kernel-module-source-TempVersion/kernel-open/nvidia-drm/nvidia-drm-drv.c
97b6c56b1407de976898e0a8b5a8f38a5211f8bb - NVIDIA-kernel-module-source-TempVersion/kernel-open/nvidia-drm/nvidia-drm-format.h
d862cc13c29bbce52f6b380b7a0a45a07fe9cbac - NVIDIA-kernel-module-source-TempVersion/kernel-open/nvidia-drm/nvidia-drm-encoder.c
c294224282118c70cd546ae024a95479ad9b1de4 - NVIDIA-kernel-module-source-TempVersion/kernel-open/nvidia-drm/nvidia-drm-gem-nvkms-memory.h
d9221522e02e18b037b8929fbc075dc3c1e58654 - NVIDIA-kernel-module-source-TempVersion/kernel-open/nvidia-drm/nv-pci-table.c
bda08c8398f68ffc2866ebc390dc63a09a16b0b9 - NVIDIA-kernel-module-source-TempVersion/src/common/unix/common/utils/unix_rm_handle.c
e903bbbecf4fb3085aaccca0628f0a0e4aba3e58 - NVIDIA-kernel-module-source-TempVersion/src/common/unix/common/utils/nv_mode_timings_utils.c
5ef40af650eb65b2c87572a1bbfe655d8821f2d5 - NVIDIA-kernel-module-source-TempVersion/src/common/unix/common/utils/nv_memory_tracker.c
26f2a36442266c5d2664d509ecfd31094a83e152 - NVIDIA-kernel-module-source-TempVersion/src/common/unix/common/utils/nv_vasprintf.c
9e008270f277e243f9167ab50401602378a2a6e8 - NVIDIA-kernel-module-source-TempVersion/src/common/unix/common/utils/interface/nv_vasprintf.h
8d9c4d69394b23d689a4aa6727eb3da1d383765a - NVIDIA-kernel-module-source-TempVersion/src/common/unix/common/utils/interface/unix_rm_handle.h
07c675d22c4f0f4be6647b65b6487e2d6927c347 - NVIDIA-kernel-module-source-TempVersion/src/common/unix/common/utils/interface/nv_memory_tracker.h
667b361db93e35d12d979c47e4d7a68be9aa93b6 - NVIDIA-kernel-module-source-TempVersion/src/common/unix/common/utils/interface/nv_mode_timings_utils.h
881cbcc7ed39ea9198279136205dbe40142be35e - NVIDIA-kernel-module-source-TempVersion/src/common/unix/common/inc/nv_assert.h
1c947cfc8a133b00727104684764e5bb900c9d28 - NVIDIA-kernel-module-source-TempVersion/src/common/unix/common/inc/nv_mode_timings.h
83044eb5259200922f78ad3248fbc1d4de1ec098 - NVIDIA-kernel-module-source-TempVersion/src/common/unix/common/inc/nv_common_utils.h
2476f128437c0520204e13a4ddd2239ff3f40c21 - NVIDIA-kernel-module-source-TempVersion/src/common/unix/common/inc/nv-float.h
a8e49041c1b95431e604852ad0fa3612548e3c82 - NVIDIA-kernel-module-source-TempVersion/src/common/unix/common/inc/nv_dpy_id.h
e3be7ba45506c42d2fca87e9da45db75ced750ca - NVIDIA-kernel-module-source-TempVersion/src/common/modeset/hdmipacket/nvhdmipkt_common.h
f669280a5e86ba51b691e2609fa7d8c223bd85dc - NVIDIA-kernel-module-source-TempVersion/src/common/modeset/hdmipacket/nvhdmipkt_C671.c
7c2fe72426fa304315e169e91dc6c1c58b5422fd - NVIDIA-kernel-module-source-TempVersion/src/common/modeset/hdmipacket/nvhdmipkt_0073.c
381e1b8aeaa8bd586c51db1f9b37d3634285c16a - NVIDIA-kernel-module-source-TempVersion/src/common/modeset/hdmipacket/nvhdmipkt_class.h
67db549636b67a32d646fb7fc6c8db2f13689ecc - NVIDIA-kernel-module-source-TempVersion/src/common/modeset/hdmipacket/nvhdmipkt_9271.c
5e12a290fc91202e4ba9e823b6d8457594ed72d3 - NVIDIA-kernel-module-source-TempVersion/src/common/modeset/hdmipacket/nvhdmi_frlInterface.h
d2c79c8a4e914519d653d1f14f706ec4a1f787e8 - NVIDIA-kernel-module-source-TempVersion/src/common/modeset/hdmipacket/nvhdmipkt_9171.c
15d54c86d78404639c7f151adc672e19472dcf4a - NVIDIA-kernel-module-source-TempVersion/src/common/modeset/hdmipacket/nvhdmipkt.c
9be7b7be94a35d1d9a04f269ff560dbbb7860a2a - NVIDIA-kernel-module-source-TempVersion/src/common/modeset/hdmipacket/nvhdmipkt_9571.c
54a1b5e5aaf0848a72befc896ed12f1de433ad4f - NVIDIA-kernel-module-source-TempVersion/src/common/modeset/hdmipacket/nvhdmipkt_9471.c
443c0a4b17a0019e4de3032c93c5cac258529f01 - NVIDIA-kernel-module-source-TempVersion/src/common/modeset/hdmipacket/nvhdmipkt_internal.h
e6d500269128cbd93790fe68fbcad5ba45c2ba7d - NVIDIA-kernel-module-source-TempVersion/src/common/modeset/hdmipacket/nvhdmipkt_C371.c
90e8ce7638a28cd781b5d30df565116dc1cea9e8 - NVIDIA-kernel-module-source-TempVersion/src/common/modeset/hdmipacket/nvhdmipkt.h
f75b1d98895bdccda0db2d8dd8feba53b88180c5 - NVIDIA-kernel-module-source-TempVersion/src/common/modeset/timing/displayid.h
ba9e382b24f57caa9dcf1c26a60b1f2070b1b9dd - NVIDIA-kernel-module-source-TempVersion/src/common/modeset/timing/nvt_displayid20.c
28d7b753825d5f4a9402aff14488c125453e95c5 - NVIDIA-kernel-module-source-TempVersion/src/common/modeset/timing/nvt_tv.c
b4813a5e854e75fb38f460e0c27dca8e1ce8dc21 - NVIDIA-kernel-module-source-TempVersion/src/common/modeset/timing/nvt_edid.c
1290abde75d218ae24f930c3b011042a3f360c2e - NVIDIA-kernel-module-source-TempVersion/src/common/modeset/timing/displayid20.h
4a2ad30f49ed92694b717a99ce7adeeb565e8a37 - NVIDIA-kernel-module-source-TempVersion/src/common/modeset/timing/nvt_edidext_861.c
439ef00ffa340bd1b6506970d154a33ca4b64b4a - NVIDIA-kernel-module-source-TempVersion/src/common/modeset/timing/nvt_dmt.c
cfaa569ac3d63484c86e8a8d7a483dd849f96be8 - NVIDIA-kernel-module-source-TempVersion/src/common/modeset/timing/nvt_edidext_displayid20.c
1997adbf2f6f5be7eb6c7a88e6660391a85d891b - NVIDIA-kernel-module-source-TempVersion/src/common/modeset/timing/nvt_gtf.c
49df9034c1634d0a9588e5588efa832a71750a37 - NVIDIA-kernel-module-source-TempVersion/src/common/modeset/timing/nvt_cvt.c
58b68f1272b069bb7819cbe86fd9e19d8acd0571 - NVIDIA-kernel-module-source-TempVersion/src/common/modeset/timing/edid.h
890d8c2898a3277b0fed360301c2dc2688724f47 - NVIDIA-kernel-module-source-TempVersion/src/common/modeset/timing/nvt_util.c
3023a58fd19d32280607d4027b09fe51fdb7a096 - NVIDIA-kernel-module-source-TempVersion/src/common/modeset/timing/nvt_dsc_pps.h
e66a20fc1579b0dd1392033089f97cf170e8cf10 - NVIDIA-kernel-module-source-TempVersion/src/common/modeset/timing/dpsdp.h
b5bd3a58b499216e4fe0e0c9c99525b07ac237dc - NVIDIA-kernel-module-source-TempVersion/src/common/modeset/timing/nvt_dsc_pps.c
f531475d8b978bca5b79d39d729b0c9986fe7b36 - NVIDIA-kernel-module-source-TempVersion/src/common/modeset/timing/nvtiming.h
95dae946088f21339299dae48eeafaab31b97b05 - NVIDIA-kernel-module-source-TempVersion/src/common/modeset/timing/nvtiming_pvt.h
0a04709ebdc4acb12038656c433e10c4e7096518 - NVIDIA-kernel-module-source-TempVersion/src/common/modeset/timing/nvt_edidext_displayid.c
1ff879eca2a273293b5cd6048419b2d2d8063b93 - NVIDIA-kernel-module-source-TempVersion/src/common/softfloat/source/f64_mulAdd.c
1a86a6948bf6768bd23a19f1f05d40968c1d2b15 - NVIDIA-kernel-module-source-TempVersion/src/common/softfloat/source/f64_rem.c
c3ce12c227d25bc0de48fbcf914fc208e2448741 - NVIDIA-kernel-module-source-TempVersion/src/common/softfloat/source/f64_sub.c
fb062ecbe62a1f5878fd47f0c61490f2bde279dd - NVIDIA-kernel-module-source-TempVersion/src/common/softfloat/source/s_roundToI32.c
38bd00e9c4d2f1354c611404cca6209a6c417669 - NVIDIA-kernel-module-source-TempVersion/src/common/softfloat/source/s_countLeadingZeros64.c
0e9694d551848d88531f5461a9b3b91611652e9a - NVIDIA-kernel-module-source-TempVersion/src/common/softfloat/source/f64_to_ui32_r_minMag.c
9f4d355d85fbe998e243fe4c7bbf8ad23062b6e2 - NVIDIA-kernel-module-source-TempVersion/src/common/softfloat/source/i64_to_f64.c
23b76c1d0be64e27a6f7e2ea7b8919f1a45a8e7c - NVIDIA-kernel-module-source-TempVersion/src/common/softfloat/source/f32_to_ui32_r_minMag.c
5c4ee32cc78efc718aaa60ec31d0b00b1bee3c2c - NVIDIA-kernel-module-source-TempVersion/src/common/softfloat/source/f64_to_ui64_r_minMag.c
09cb0cdb90eb23b53cd9c1a76ba26021084710d1 - NVIDIA-kernel-module-source-TempVersion/src/common/softfloat/source/s_addMagsF32.c
00c612847b3bd227a006a4a2697df85866b80315 - NVIDIA-kernel-module-source-TempVersion/src/common/softfloat/source/s_mulAddF32.c
29321080baa7eab86947ac825561fdcff54a0e43 - NVIDIA-kernel-module-source-TempVersion/src/common/softfloat/source/i32_to_f32.c
2e0fec421f4defd293cf55c5f3af7d91f4b7d2cc - NVIDIA-kernel-module-source-TempVersion/src/common/softfloat/source/ui64_to_f32.c
ebb4f674b6213fec29761fc4e05c1e3ddeda6d17 - NVIDIA-kernel-module-source-TempVersion/src/common/softfloat/source/f32_mulAdd.c
2e5c29d842a8ebc5fbf987068dc9394cee609cc7 - NVIDIA-kernel-module-source-TempVersion/src/common/softfloat/source/f32_to_ui64.c
daeb408588738b3eb4c8b092d7f92ac597cf1fc6 - NVIDIA-kernel-module-source-TempVersion/src/common/softfloat/source/f32_rem.c
da3b3f94a817909a3dc93ca5fa7675805c7979e0 - NVIDIA-kernel-module-source-TempVersion/src/common/softfloat/source/f64_isSignalingNaN.c
bc992c88f3de09e3a82447cf06dbde7c6604f7f8 - NVIDIA-kernel-module-source-TempVersion/src/common/softfloat/source/f64_to_f32.c
dafa667ee5dd52c97fc0c3b7144f6b619406c225 - NVIDIA-kernel-module-source-TempVersion/src/common/softfloat/source/s_mulAddF64.c
2960704c290f29aae36b8fe006884d5c4abcabb4 - NVIDIA-kernel-module-source-TempVersion/src/common/softfloat/source/f32_div.c
d4b26dc407a891e9ff5324853f1845a99c5d5cd2 - NVIDIA-kernel-module-source-TempVersion/src/common/softfloat/source/f32_to_i32.c
0adfa7e174cdb488bb22b06642e14e7fc6f49c67 - NVIDIA-kernel-module-source-TempVersion/src/common/softfloat/source/s_roundToI64.c
fd40a71c7ebf9d632a384fadf9487cfef4f3ea98 - NVIDIA-kernel-module-source-TempVersion/src/common/softfloat/source/s_shiftRightJam128.c
9a5b93459ace2da23964da98617d6b18006fab86 - NVIDIA-kernel-module-source-TempVersion/src/common/softfloat/source/s_countLeadingZeros8.c
ae25eea499b3ea5bdd96c905fd0542da11083048 - NVIDIA-kernel-module-source-TempVersion/src/common/softfloat/source/s_normRoundPackToF64.c
729e790328168c64d65a1355e990274c249bbb3a - NVIDIA-kernel-module-source-TempVersion/src/common/softfloat/source/f32_to_i32_r_minMag.c
296c40b0589536cb9af3231ad3dcd7f2baaa6887 - NVIDIA-kernel-module-source-TempVersion/src/common/softfloat/source/f64_lt.c
5c1026617c588bcf5f1e59230bd5bb900600b9ac - NVIDIA-kernel-module-source-TempVersion/src/common/softfloat/source/f64_mul.c
4b37be398b3e73ae59245f03b2ba2394fc902b4d - NVIDIA-kernel-module-source-TempVersion/src/common/softfloat/source/s_normSubnormalF64Sig.c
69dc4cc63b2a9873a6eb636ee7cb704cbd502001 - NVIDIA-kernel-module-source-TempVersion/src/common/softfloat/source/f64_to_ui32.c
d0f8f08c225b60d88b6358d344404ba9df3038ec - NVIDIA-kernel-module-source-TempVersion/src/common/softfloat/source/s_normSubnormalF32Sig.c
c951c9dffa123e4f77ed235eca49ef9b67f9f3d2 - NVIDIA-kernel-module-source-TempVersion/src/common/softfloat/source/s_subMagsF64.c
dde685423af544e5359efdb51b4bf9457c67fa3b - NVIDIA-kernel-module-source-TempVersion/src/common/softfloat/source/f32_sqrt.c
577821f706c7de4ca327c1e2fcc34161c96c89f3 - NVIDIA-kernel-module-source-TempVersion/src/common/softfloat/source/f64_to_i64_r_minMag.c
5a5e0d9f1ee7e8c0d1d4f9fbcf6eba330a5f1792 - NVIDIA-kernel-module-source-TempVersion/src/common/softfloat/source/f32_isSignalingNaN.c
84b0a01ba2a667eb28b166d45bd91352ead83e69 - NVIDIA-kernel-module-source-TempVersion/src/common/softfloat/source/i64_to_f32.c
513a7d1c3053fc119efcd8ae1bcc9652edc45315 - NVIDIA-kernel-module-source-TempVersion/src/common/softfloat/source/f32_lt.c
4445b1fbbd507144f038fd939311ff95bc2cf5f1 - NVIDIA-kernel-module-source-TempVersion/src/common/softfloat/source/ui64_to_f64.c
b9fd15957f7ae5effeccb5d8adaa7434b43f44e1 - NVIDIA-kernel-module-source-TempVersion/src/common/softfloat/source/s_roundToUI64.c
ab19c6b50c40b8089cb915226d4553d1aa902b0e - NVIDIA-kernel-module-source-TempVersion/src/common/softfloat/source/f64_to_i32_r_minMag.c
7bc81f5bc894118c08bfd52b59e010bc068ed762 - NVIDIA-kernel-module-source-TempVersion/src/common/softfloat/source/ui32_to_f32.c
7c8e5ab3f9bf6b2764ce5fffe80b2674be566a12 - NVIDIA-kernel-module-source-TempVersion/src/common/softfloat/source/softfloat_state.c
ec1a797b11f6e846928a4a49a8756f288bda1dfa - NVIDIA-kernel-module-source-TempVersion/src/common/softfloat/source/i32_to_f64.c
86fdc2472526375539216461732d1db6a9f85b55 - NVIDIA-kernel-module-source-TempVersion/src/common/softfloat/source/s_roundPackToF32.c
b22876b0695f58ee56143c9f461f1dde32fefbf3 - NVIDIA-kernel-module-source-TempVersion/src/common/softfloat/source/f64_to_ui64.c
d701741d8d6a92bb890e53deda1b795f5787f465 - NVIDIA-kernel-module-source-TempVersion/src/common/softfloat/source/f64_le.c
baa7af4eea226140c26ffe6ab02a863d07f729fb - NVIDIA-kernel-module-source-TempVersion/src/common/softfloat/source/f64_eq_signaling.c
ce37cdce572a3b02d42120e81c4969b39d1a67b6 - NVIDIA-kernel-module-source-TempVersion/src/common/softfloat/source/f64_to_i32.c
0108fe6f0d394ad72083aff9bb58507f97a0b669 - NVIDIA-kernel-module-source-TempVersion/src/common/softfloat/source/ui32_to_f64.c
b8c5ccc1e511637d8b2ba2657de4937b80c01c07 - NVIDIA-kernel-module-source-TempVersion/src/common/softfloat/source/f32_le.c
54cbeb5872a86e822bda852ec15d3dcdad4511ce - NVIDIA-kernel-module-source-TempVersion/src/common/softfloat/source/f64_add.c
c29536f617d71fe30accac44b2f1df61c98a97dc - NVIDIA-kernel-module-source-TempVersion/src/common/softfloat/source/f64_div.c
871cb1a4037d7b4e73cb20ad18390736eea7ae36 - NVIDIA-kernel-module-source-TempVersion/src/common/softfloat/source/f32_to_ui64_r_minMag.c
21a6232d93734b01692689258a3fdfbbf4ff089d - NVIDIA-kernel-module-source-TempVersion/src/common/softfloat/source/s_roundToUI32.c
760fd7c257a1f915b61a1089b2acb143c18a082e - NVIDIA-kernel-module-source-TempVersion/src/common/softfloat/source/s_addMagsF64.c
5e6f9e120a17cc73297a35e4d57e4b9cbce01780 - NVIDIA-kernel-module-source-TempVersion/src/common/softfloat/source/s_mul64To128.c
0bf499c0e3a54186fa32b38b310cc9d98ccdcfe3 - NVIDIA-kernel-module-source-TempVersion/src/common/softfloat/source/f32_eq.c
29396b7c23941024a59d5ea06698d2fbc7e1a6ca - NVIDIA-kernel-module-source-TempVersion/src/common/softfloat/source/f64_to_i64.c
108eec2abf1cddb397ce9f652465c2e52f7c143b - NVIDIA-kernel-module-source-TempVersion/src/common/softfloat/source/f64_roundToInt.c
fe06512577e642b09196d46430d038d027491e9f - NVIDIA-kernel-module-source-TempVersion/src/common/softfloat/source/f32_eq_signaling.c
d19ff7dfece53875f2d6c6f7dd9e7772f7b0b7ec - NVIDIA-kernel-module-source-TempVersion/src/common/softfloat/source/f32_to_i64_r_minMag.c
1484fc96d7731695bda674e99947280a86990997 - NVIDIA-kernel-module-source-TempVersion/src/common/softfloat/source/f32_to_i64.c
8e58f0258218475616ff4e6317516d40ad475626 - NVIDIA-kernel-module-source-TempVersion/src/common/softfloat/source/f32_lt_quiet.c
6fa7493285fe2f7fdc0ac056a6367e90327905c2 - NVIDIA-kernel-module-source-TempVersion/src/common/softfloat/source/f32_sub.c
aaf6ccb77a1a89fa055a0fb63513297b35e2e54b - NVIDIA-kernel-module-source-TempVersion/src/common/softfloat/source/f64_le_quiet.c
bbc70102b30f152a560eb98e7a1a4b11b9ede85e - NVIDIA-kernel-module-source-TempVersion/src/common/softfloat/source/f64_sqrt.c
e0ad81cfb5d2c0e74dc4ece9518ca15ffc77beaf - NVIDIA-kernel-module-source-TempVersion/src/common/softfloat/source/f32_roundToInt.c
50b3147f8413f0595a4c3d6e6eeab84c1ffecada - NVIDIA-kernel-module-source-TempVersion/src/common/softfloat/source/s_normRoundPackToF32.c
50daf9186bc5d0180d1453c957164b136d5ffc89 - NVIDIA-kernel-module-source-TempVersion/src/common/softfloat/source/f64_eq.c
6f83fa864007e8227ae09bb36a7fdc18832d4445 - NVIDIA-kernel-module-source-TempVersion/src/common/softfloat/source/f32_mul.c
a94c8c2bd74633027e52e96f41d24714d8081eb4 - NVIDIA-kernel-module-source-TempVersion/src/common/softfloat/source/s_approxRecipSqrt_1Ks.c
e7890082ce426d88b4ec93893da32e306478c0d1 - NVIDIA-kernel-module-source-TempVersion/src/common/softfloat/source/s_approxRecipSqrt32_1.c
2db07bbb8242bc55a24ef483af6d648db0660de0 - NVIDIA-kernel-module-source-TempVersion/src/common/softfloat/source/f32_add.c
9266c83f3e50093cc45d7be6ab993a0e72af1685 - NVIDIA-kernel-module-source-TempVersion/src/common/softfloat/source/s_roundPackToF64.c
00ab2120f71117161d4f6daaa9b90a3036a99841 - NVIDIA-kernel-module-source-TempVersion/src/common/softfloat/source/f32_to_ui32.c
824383b03952c611154bea0a862da2b9e2a43827 - NVIDIA-kernel-module-source-TempVersion/src/common/softfloat/source/s_subMagsF32.c
68843a93e1f46195243ef1164f611b759cf19d17 - NVIDIA-kernel-module-source-TempVersion/src/common/softfloat/source/f32_le_quiet.c
e4930e155580a0f5aa7f3694a6205bc9aebfe7aa - NVIDIA-kernel-module-source-TempVersion/src/common/softfloat/source/f32_to_f64.c
054b23a974fc8d0bab232be433c4e516e6c1250a - NVIDIA-kernel-module-source-TempVersion/src/common/softfloat/source/f64_lt_quiet.c
0d8e42636a3409a647291fdb388001c2b11bba07 - NVIDIA-kernel-module-source-TempVersion/src/common/softfloat/source/f32_to_f16.c
d9a86343e6cc75714f65f690082dd4b0ba724be9 - NVIDIA-kernel-module-source-TempVersion/src/common/softfloat/source/s_roundPackToF16.c
1dd1b424087d9c872684df0c1b4063b077992d5f - NVIDIA-kernel-module-source-TempVersion/src/common/softfloat/source/8086-SSE/s_f64UIToCommonNaN.c
86cda6550cb02bbf595d1667573e4be83702a95e - NVIDIA-kernel-module-source-TempVersion/src/common/softfloat/source/8086-SSE/specialize.h
21a11759ed2afd746a47c4d78b67640c2d052165 - NVIDIA-kernel-module-source-TempVersion/src/common/softfloat/source/8086-SSE/s_commonNaNToF32UI.c
a6d5c83f6a0542b33ac9c23ac65ef69002cfff9d - NVIDIA-kernel-module-source-TempVersion/src/common/softfloat/source/8086-SSE/s_propagateNaNF32UI.c
3d0dbc0a672d039a6346e1c21ddf87ffc9181978 - NVIDIA-kernel-module-source-TempVersion/src/common/softfloat/source/8086-SSE/s_f32UIToCommonNaN.c
252c816378fddab616b1f2a61e9fedd549224483 - NVIDIA-kernel-module-source-TempVersion/src/common/softfloat/source/8086-SSE/s_commonNaNToF64UI.c
d8b0c55a49c4fa0b040541db6d5ff634d7d103e7 - NVIDIA-kernel-module-source-TempVersion/src/common/softfloat/source/8086-SSE/s_propagateNaNF64UI.c
d152bc457b655725185bdff42b36bb96d6e6715e - NVIDIA-kernel-module-source-TempVersion/src/common/softfloat/source/8086-SSE/s_commonNaNToF16UI.c
0cbae7a5abc336331d460cbd3640d2cda02af434 - NVIDIA-kernel-module-source-TempVersion/src/common/softfloat/source/8086-SSE/softfloat_raiseFlags.c
1ded4df85ff5fa904fa54c27d681265425be1658 - NVIDIA-kernel-module-source-TempVersion/src/common/softfloat/source/include/primitiveTypes.h
f36c896cfa01f1de9f9420189319e4e00c7fc52a - NVIDIA-kernel-module-source-TempVersion/src/common/softfloat/source/include/internals.h
9645e179cf888bcd0e3836e8126b204b4b42b315 - NVIDIA-kernel-module-source-TempVersion/src/common/softfloat/source/include/softfloat.h
de09949a0ca5cd2a84b882b5b5c874d01d3ae11a - NVIDIA-kernel-module-source-TempVersion/src/common/softfloat/source/include/primitives.h
4cd1d6cfca3936a39aab9bc0eb622f5c7c848be1 - NVIDIA-kernel-module-source-TempVersion/src/common/softfloat/source/include/softfloat_types.h
b882497ae393bf66a728dae395b64ac53602a1a5 - NVIDIA-kernel-module-source-TempVersion/src/common/softfloat/nvidia/nv-softfloat.h
be9407a273620c0ba619b53ed72d59d52620c3e4 - NVIDIA-kernel-module-source-TempVersion/src/common/softfloat/nvidia/platform.h
91e9bc3214d6bb9b20bc8001d85fe8699df5184a - NVIDIA-kernel-module-source-TempVersion/src/common/sdk/nvidia/inc/nvos.h
88399279bd5e31b6e77cb32c7ef6220ce529526b - NVIDIA-kernel-module-source-TempVersion/src/common/sdk/nvidia/inc/nv-hypervisor.h
f28f98589e65b71e47dbcb2c4230538ae0545e75 - NVIDIA-kernel-module-source-TempVersion/src/common/sdk/nvidia/inc/cpuopsys.h
4b7414705ce10f0a1e312c36a43824b59d572661 - NVIDIA-kernel-module-source-TempVersion/src/common/sdk/nvidia/inc/nvmisc.h
af0bc90b3ad4767de53b8ff91e246fdab0146e8b - NVIDIA-kernel-module-source-TempVersion/src/common/sdk/nvidia/inc/nvsecurityinfo.h
a506a41b8dcf657fb39a740ffc1dfd83835d6c89 - NVIDIA-kernel-module-source-TempVersion/src/common/sdk/nvidia/inc/nvcfg_sdk.h
b249abc0a7d0c9889008e98cb2f8515a9d310b85 - NVIDIA-kernel-module-source-TempVersion/src/common/sdk/nvidia/inc/nvgputypes.h
ae60d53603c7ddbbd72d4e16ce2951f3d42aed32 - NVIDIA-kernel-module-source-TempVersion/src/common/sdk/nvidia/inc/nverror.h
a31b82c454df785a1d7893af38e83443cfe6f2fc - NVIDIA-kernel-module-source-TempVersion/src/common/sdk/nvidia/inc/nvdisptypes.h
ffa91e1110a5cc286ec44a7bda5461b2be941ea2 - NVIDIA-kernel-module-source-TempVersion/src/common/sdk/nvidia/inc/nv_vgpu_types.h
9bca638f5832d831880f090c583fac6fc8cf6ee6 - NVIDIA-kernel-module-source-TempVersion/src/common/sdk/nvidia/inc/dpringbuffertypes.h
821a01976045d7c3d2ac35b0f115e90a9e95f8e8 - NVIDIA-kernel-module-source-TempVersion/src/common/sdk/nvidia/inc/nvimpshared.h
1e7eec6561b04d2d21c3515987aaa116e9401c1f - NVIDIA-kernel-module-source-TempVersion/src/common/sdk/nvidia/inc/nv-kernel-interface-api.h
3b12d770f8592b94a8c7774c372e80ad08c5774c - NVIDIA-kernel-module-source-TempVersion/src/common/sdk/nvidia/inc/nvi2c.h
befb2c0bf0a31b61be5469575ce3c73a9204f4e9 - NVIDIA-kernel-module-source-TempVersion/src/common/sdk/nvidia/inc/nv_stdarg.h
5d8de06378994201e91c2179d149c0edcd694900 - NVIDIA-kernel-module-source-TempVersion/src/common/sdk/nvidia/inc/nvstatuscodes.h
95bf694a98ba78d5a19e66463b8adda631e6ce4c - NVIDIA-kernel-module-source-TempVersion/src/common/sdk/nvidia/inc/nvstatus.h
50d31a6d133b0ea9230f9dc1b701ce16a88a7935 - NVIDIA-kernel-module-source-TempVersion/src/common/sdk/nvidia/inc/rs_access.h
eb42327a2b948b79edc04d9145c7aa5b2a2b420e - NVIDIA-kernel-module-source-TempVersion/src/common/sdk/nvidia/inc/nvlimits.h
9f2e225f027f5a04d1104d29a0039cd2bb7dd85a - NVIDIA-kernel-module-source-TempVersion/src/common/sdk/nvidia/inc/nvfixedtypes.h
a9bf4969ae3e39cc315b6180ee7055e0ad1279c6 - NVIDIA-kernel-module-source-TempVersion/src/common/sdk/nvidia/inc/nvtypes.h
00e9a0ace4b59958a8b048229fb22b4d9e2f8864 - NVIDIA-kernel-module-source-TempVersion/src/common/sdk/nvidia/inc/ctrl/ctrl90cd.h
3449834cb8b8c630ab1de6df30503c846b26e86b - NVIDIA-kernel-module-source-TempVersion/src/common/sdk/nvidia/inc/ctrl/ctrl90ec.h
f779cd0470e428160fc590b590f2cd4855950058 - NVIDIA-kernel-module-source-TempVersion/src/common/sdk/nvidia/inc/ctrl/ctrl402c.h
7c4aef225d174ecbe1130d63b8e8ff752bddf48e - NVIDIA-kernel-module-source-TempVersion/src/common/sdk/nvidia/inc/ctrl/ctrl0041.h
5abe75cf18a2fede23529194b406c3cf742edced - NVIDIA-kernel-module-source-TempVersion/src/common/sdk/nvidia/inc/ctrl/ctrlxxxx.h
c8490da9f200f4dbbac7ebe636f3a83485f3001c - NVIDIA-kernel-module-source-TempVersion/src/common/sdk/nvidia/inc/ctrl/ctrl0073.h
1022bba330a71b92dcc81f47ba460209fcc70cd0 - NVIDIA-kernel-module-source-TempVersion/src/common/sdk/nvidia/inc/ctrl/ctrl0002.h
b72318d58806bfd25f922107a606b222baa2e28c - NVIDIA-kernel-module-source-TempVersion/src/common/sdk/nvidia/inc/ctrl/ctrl30f1.h
7a0c878431a9b0d9dda117f165946b1cdf8ebbde - NVIDIA-kernel-module-source-TempVersion/src/common/sdk/nvidia/inc/ctrl/ctrl0020.h
e2d8133537e2687df022c6a966c55fbfea1974f3 - NVIDIA-kernel-module-source-TempVersion/src/common/sdk/nvidia/inc/ctrl/ctrl0004.h
9c6a4f1d864b5161564869b19f8cb2ce9d629c1d - NVIDIA-kernel-module-source-TempVersion/src/common/sdk/nvidia/inc/ctrl/ctrl003e.h
0639d6cd553994aff4195e8e7547eebf8e713145 - NVIDIA-kernel-module-source-TempVersion/src/common/sdk/nvidia/inc/ctrl/ctrl0080.h
79204c26eb58ee812cc2f72ee1f6d4d7d93817c7 - NVIDIA-kernel-module-source-TempVersion/src/common/sdk/nvidia/inc/ctrl/ctrl2080.h
ea9aac6f0e23f0de444ac3919c35e4b78c18c942 - NVIDIA-kernel-module-source-TempVersion/src/common/sdk/nvidia/inc/ctrl/ctrl0080/ctrl0080bif.h
f7435e356d54d682a949734574388abbe7ffe1d0 - NVIDIA-kernel-module-source-TempVersion/src/common/sdk/nvidia/inc/ctrl/ctrl0080/ctrl0080base.h
64f849ed19609320461b8938f24f0b40fb1a35b0 - NVIDIA-kernel-module-source-TempVersion/src/common/sdk/nvidia/inc/ctrl/ctrl0080/ctrl0080cipher.h
d107e41878b5bc50a5c8b29684122c9589625a6f - NVIDIA-kernel-module-source-TempVersion/src/common/sdk/nvidia/inc/ctrl/ctrl0080/ctrl0080perf.h
f4a4eeb35e15e0642d1bf4e2e5b31394f4cbbfa1 - NVIDIA-kernel-module-source-TempVersion/src/common/sdk/nvidia/inc/ctrl/ctrl0080/ctrl0080host.h
b7b0360b1a6ca78267fa10f7adcd370da86513c3 - NVIDIA-kernel-module-source-TempVersion/src/common/sdk/nvidia/inc/ctrl/ctrl0080/ctrl0080bsp.h
862a17958488d69ca3e92c42ee1bed55cb299fa4 - NVIDIA-kernel-module-source-TempVersion/src/common/sdk/nvidia/inc/ctrl/ctrl0080/ctrl0080gpu.h
bb4182eeea20779f62165d2d50ed209b6a07e54e - NVIDIA-kernel-module-source-TempVersion/src/common/sdk/nvidia/inc/ctrl/ctrl0080/ctrl0080msenc.h
b7f2957f506dc285acb87d41d34cfd60408b00ae - NVIDIA-kernel-module-source-TempVersion/src/common/sdk/nvidia/inc/ctrl/ctrl0080/ctrl0080rc.h
c72f147e8fb78126d13567278239acfcd9b9cc1f - NVIDIA-kernel-module-source-TempVersion/src/common/sdk/nvidia/inc/ctrl/ctrl0080/ctrl0080internal.h
8dd5acedc0b1613314eb3fe9130a9c282bd49ca1 - NVIDIA-kernel-module-source-TempVersion/src/common/sdk/nvidia/inc/ctrl/ctrl0080/ctrl0080clk.h
681c94b982e29049638814f6c1e4eb508f8b0bf3 - NVIDIA-kernel-module-source-TempVersion/src/common/sdk/nvidia/inc/ctrl/ctrl0080/ctrl0080unix.h
3646710984d5c3024d16f9ab346222ad6dfdb4f0 - NVIDIA-kernel-module-source-TempVersion/src/common/sdk/nvidia/inc/ctrl/ctrl0080/ctrl0080fifo.h
6c34803c213ea0a28114bc921e1867cefebec088 - NVIDIA-kernel-module-source-TempVersion/src/common/sdk/nvidia/inc/ctrl/ctrl0080/ctrl0080dma.h
76c9f104e04a8fd9e73e03ad59b2e72264c5f169 - NVIDIA-kernel-module-source-TempVersion/src/common/sdk/nvidia/inc/ctrl/ctrl0080/ctrl0080nvjpg.h
9e61da81ecdff15d63f9ae8a1c2f0960b820c65c - NVIDIA-kernel-module-source-TempVersion/src/common/sdk/nvidia/inc/ctrl/ctrl0080/ctrl0080gr.h
dac18fcaf5d652b21f84cfba455f4f5972e786c5 - NVIDIA-kernel-module-source-TempVersion/src/common/sdk/nvidia/inc/ctrl/ctrl0080/ctrl0080fb.h
d51e47795dfe1fc0bae31b9379d6a39ac4d3080f - NVIDIA-kernel-module-source-TempVersion/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080bios.h
8a613db1c31724a577c4718752c15d9754882f48 - NVIDIA-kernel-module-source-TempVersion/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080lpwr.h
3966d65c9701bf97c807cf87838a08cda10f418d - NVIDIA-kernel-module-source-TempVersion/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080tmr.h
a1830232f18afe44230d6a8598c50b3fc7656089 - NVIDIA-kernel-module-source-TempVersion/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080nvd.h
2dd40e3e41d74de3865bc700acc9ab7e0540c647 - NVIDIA-kernel-module-source-TempVersion/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080gpio.h
f97e7f88aa17788bbbebf55807e449c0ee016384 - NVIDIA-kernel-module-source-TempVersion/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080ucodefuzzer.h
b2b6b3b413ae17af1afde2fc8672cd1bf48e7b19 - NVIDIA-kernel-module-source-TempVersion/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080illum.h
3c7130d0613d3c8baef6b23bb63c6ee7a10ed21b - NVIDIA-kernel-module-source-TempVersion/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080cipher.h
39f5e838aa6ab007c56e7a59c7d2986d1a7aa34a - NVIDIA-kernel-module-source-TempVersion/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080ce.h
6679d97e3852ed78ee44780408c523b94f426ca4 - NVIDIA-kernel-module-source-TempVersion/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080perf_cf_pwr_model.h
090f908931690302e3a2c77f3ce41c4de0c61efc - NVIDIA-kernel-module-source-TempVersion/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080vfe.h
7c4e426dee0ae86c00b3bd10873a1a2bd94ed3b2 - NVIDIA-kernel-module-source-TempVersion/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080power.h
5bdddb9a949a78443f83a7da81ad5fee8a300c44 - NVIDIA-kernel-module-source-TempVersion/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080perf_cf.h
d084d99035f4cc34cd803ff4a5328b9e10ea77fc - NVIDIA-kernel-module-source-TempVersion/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080boardobj.h
4b8fa2ce546ae3f06b7dc61df3d534449cdb5b2d - NVIDIA-kernel-module-source-TempVersion/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080clkavfs.h
8855ee8bad2f2169ebd147e7ac77d9f1340cbad8 - NVIDIA-kernel-module-source-TempVersion/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080spi.h
82a2e7a2fc6501163d07870f3f640a591f4a8996 - NVIDIA-kernel-module-source-TempVersion/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080volt.h
f3a855fe7a91c2acf2be41629ce906996e01a9fc - NVIDIA-kernel-module-source-TempVersion/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080perf.h
3d8e37aa8485aadf55335d8f9f913273d90a2442 - NVIDIA-kernel-module-source-TempVersion/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080boardobjgrpclasses.h
da220a5608a0e4c73fa0315b13e2b29d92b114e9 - NVIDIA-kernel-module-source-TempVersion/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080dmabuf.h
6834a9c75265c25adfb03f0b2dbfe0559f28cadf - NVIDIA-kernel-module-source-TempVersion/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080dma.h
051dbfd1d5ff02b2771bc9b3fad8aaef29aab9ae - NVIDIA-kernel-module-source-TempVersion/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080base.h
c3a75647f5ca6cd7b456511af36a9de6d90329c3 - NVIDIA-kernel-module-source-TempVersion/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080nvlink.h
82364e263f43ea028c2d66db58887958bdef64b0 - NVIDIA-kernel-module-source-TempVersion/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080fb.h
143c1c24ec926142d1f84dec7a543f2b98541545 - NVIDIA-kernel-module-source-TempVersion/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080fuse.h
1684a3a8111fd3d83363cebe68d016a54eaaf686 - NVIDIA-kernel-module-source-TempVersion/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080clk.h
72292c9844eaf24c38967dd4a879c0c0f070a0de - NVIDIA-kernel-module-source-TempVersion/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080gr.h
091f7bac99f5c786a64b6fa59d9d27af786bab10 - NVIDIA-kernel-module-source-TempVersion/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080acr.h
c0181e959c1ba5ebfc3f130c8764687b58453f9b - NVIDIA-kernel-module-source-TempVersion/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080fla.h
2a11fc0a499f8293b83e08572f5e6be04bd1da61 - NVIDIA-kernel-module-source-TempVersion/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080gpu.h
a44d2f1b31b8ec124355018204909df19df09748 - NVIDIA-kernel-module-source-TempVersion/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080unix.h
8ef946f1d7545277ef64891b45a29db44c4e9913 - NVIDIA-kernel-module-source-TempVersion/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080fan.h
774fd1e730d1d853bf97946f7ecd24c6648c7af4 - NVIDIA-kernel-module-source-TempVersion/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080hshub.h
22d828c87b223f937c589a0e863a25d95b734371 - NVIDIA-kernel-module-source-TempVersion/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080event.h
7d3819683e9f562a87f36a3e23c043b2b6fd814e - NVIDIA-kernel-module-source-TempVersion/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080rc.h
7d27fafff043d290b2ec1d2dddbecea2f1df4704 - NVIDIA-kernel-module-source-TempVersion/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080gsp.h
27ad8b5c2406fcd572cd098dd215e93ae1db99e3 - NVIDIA-kernel-module-source-TempVersion/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080mc.h
783db6da0b92b6b8ae26b180129beb0bccb13a5b - NVIDIA-kernel-module-source-TempVersion/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080thermal.h
e6f6beaed64167088608027b442f5449cff027c1 - NVIDIA-kernel-module-source-TempVersion/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080common.h
6b4418e269bb97b9996b05ea153ccd195c661e11 - NVIDIA-kernel-module-source-TempVersion/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080fifo.h
0ac7e4eb4d952c84c6f4e697cbfcb355069377c2 - NVIDIA-kernel-module-source-TempVersion/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080flcn.h
1651ec548a2899391a05bc6463b3f7162c7807ab - NVIDIA-kernel-module-source-TempVersion/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080internal.h
bc22bf13b7d99ee6f80c30b569e084a2b03e385a - NVIDIA-kernel-module-source-TempVersion/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080grmgr.h
1ebfe9f0f9a7d2dd2873df82bbc78b1ec982ca93 - NVIDIA-kernel-module-source-TempVersion/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080pmumon.h
291f91212d5a37aae46a2944cf89f4b74b1d1809 - NVIDIA-kernel-module-source-TempVersion/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080pmgr.h
82aa4d6108ce6abebcbbc95afcb7a6350e287f5f - NVIDIA-kernel-module-source-TempVersion/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080i2c.h
c4474dc1f53661c67d8fce5303dcc636d9ad3b8f - NVIDIA-kernel-module-source-TempVersion/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080gpumon.h
18814de559257f07bad8a0a9006ac9751fcfa1cb - NVIDIA-kernel-module-source-TempVersion/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080ecc.h
e9d692b06c70951dbbd0663a89f822153bce1146 - NVIDIA-kernel-module-source-TempVersion/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080bus.h
1248e113751f8ed9e4111e86a7f7fb632b102eca - NVIDIA-kernel-module-source-TempVersion/src/common/sdk/nvidia/inc/ctrl/ctrl0073/ctrl0073stereo.h
b921747a65c67fa093de08fa782c164d048824b0 - NVIDIA-kernel-module-source-TempVersion/src/common/sdk/nvidia/inc/ctrl/ctrl0073/ctrl0073system.h
7e0773f7bf13350a9fd25b0df4d6c45a55a008df - NVIDIA-kernel-module-source-TempVersion/src/common/sdk/nvidia/inc/ctrl/ctrl0073/ctrl0073event.h
8fd661537cc4eb55c167b9daae404bfb82408bfe - NVIDIA-kernel-module-source-TempVersion/src/common/sdk/nvidia/inc/ctrl/ctrl0073/ctrl0073svp.h
f88f1c519a242dfa71221bdcdafc7deab14d8503 - NVIDIA-kernel-module-source-TempVersion/src/common/sdk/nvidia/inc/ctrl/ctrl0073/ctrl0073dp.h
ccc48726d7da49cddc4d4f86d8dbd2ad585f7b38 - NVIDIA-kernel-module-source-TempVersion/src/common/sdk/nvidia/inc/ctrl/ctrl0073/ctrl0073base.h
3dc187adc0a848e68f62a6a7eb99ac02ee6502cc - NVIDIA-kernel-module-source-TempVersion/src/common/sdk/nvidia/inc/ctrl/ctrl0073/ctrl0073dpu.h
f3b81a241efe1224798b17c062e33936469c3c2b - NVIDIA-kernel-module-source-TempVersion/src/common/sdk/nvidia/inc/ctrl/ctrl0073/ctrl0073internal.h
09dedebdcff3244ab8f607a7152e9116d821f9c1 - NVIDIA-kernel-module-source-TempVersion/src/common/sdk/nvidia/inc/ctrl/ctrl0073/ctrl0073specific.h
440314f66374d35a1628ee8bd61836a80ab421eb - NVIDIA-kernel-module-source-TempVersion/src/common/sdk/nvidia/inc/ctrl/ctrl0073/ctrl0073dfp.h
92be535d68a7f18088921faa3f1742298ad341c3 - NVIDIA-kernel-module-source-TempVersion/src/common/sdk/nvidia/inc/ctrl/ctrl0073/ctrl0073psr.h
84fb76f9cff38c797b139cba40175717591d49df - NVIDIA-kernel-module-source-TempVersion/src/common/sdk/nvidia/inc/ctrl/ctrl5070/ctrl5070common.h
2f92bebccb9da5246b19bd13ff0e6e79de79bc3b - NVIDIA-kernel-module-source-TempVersion/src/common/sdk/nvidia/inc/ctrl/ctrl5070/ctrl5070verif.h
aec1b750866e34f9626e48c535336f93c5c246fa - NVIDIA-kernel-module-source-TempVersion/src/common/sdk/nvidia/inc/ctrl/ctrl5070/ctrl5070seq.h
9031642283b59ee6d52e2e1ca54332df5c2f7acc - NVIDIA-kernel-module-source-TempVersion/src/common/sdk/nvidia/inc/ctrl/ctrl5070/ctrl5070rg.h
e10cbe4875736ef16072232789dd3f48647c022f - NVIDIA-kernel-module-source-TempVersion/src/common/sdk/nvidia/inc/ctrl/ctrl5070/ctrl5070impoverrides.h
91cccede5c4f26a6b6ca7ba4bc292f3d908a88d4 - NVIDIA-kernel-module-source-TempVersion/src/common/sdk/nvidia/inc/ctrl/ctrl5070/ctrl5070base.h
f47136417885a729f9c5dee375ec9dec1bd170e0 - NVIDIA-kernel-module-source-TempVersion/src/common/sdk/nvidia/inc/ctrl/ctrl5070/ctrl5070chnc.h
f523fe4a55a6a9d01f41f9f34ff149ed75b2e739 - NVIDIA-kernel-module-source-TempVersion/src/common/sdk/nvidia/inc/ctrl/ctrl5070/ctrl5070event.h
ad7604ced12ee18c569d2a7ebe71e185ebff3fd4 - NVIDIA-kernel-module-source-TempVersion/src/common/sdk/nvidia/inc/ctrl/ctrl5070/ctrl5070system.h
209ef519cb73395cea7d66016448ebc3c6bf6fe4 - NVIDIA-kernel-module-source-TempVersion/src/common/sdk/nvidia/inc/ctrl/ctrl5070/ctrl5070or.h
4a3e7d71b9169d703d9373ff80b02a63825a80e4 - NVIDIA-kernel-module-source-TempVersion/src/common/sdk/nvidia/inc/ctrl/ctrl0000/ctrl0000unix.h
4d9116d23d27a3fc39c366f2685243b83ef7d485 - NVIDIA-kernel-module-source-TempVersion/src/common/sdk/nvidia/inc/ctrl/ctrl0000/ctrl0000diag.h
abe79ad927e7c70b7c1a8eb687052a782efcd5f4 - NVIDIA-kernel-module-source-TempVersion/src/common/sdk/nvidia/inc/ctrl/ctrl0000/ctrl0000nvd.h
ef180860a1ccbcb9f5d2f8a6656a345eef76a2a7 - NVIDIA-kernel-module-source-TempVersion/src/common/sdk/nvidia/inc/ctrl/ctrl0000/ctrl0000base.h
f7e56d494fea02515180f21b0f56ae0aff583be4 - NVIDIA-kernel-module-source-TempVersion/src/common/sdk/nvidia/inc/ctrl/ctrl0000/ctrl0000gpuacct.h
b66a45c83c84f6d458ef19fd7e0f972f2eabd109 - NVIDIA-kernel-module-source-TempVersion/src/common/sdk/nvidia/inc/ctrl/ctrl0000/ctrl0000vgpu.h
2518a62952c72ee6f3447bc8dc417129f6ac26a4 - NVIDIA-kernel-module-source-TempVersion/src/common/sdk/nvidia/inc/ctrl/ctrl0000/ctrl0000system.h
9373c51ca29afec3368fb5b8c2a2f05b0920f291 - NVIDIA-kernel-module-source-TempVersion/src/common/sdk/nvidia/inc/ctrl/ctrl0000/ctrl0000gpu.h
0ee647b929e55cf39da7e26ffc0f027676fa52fa - NVIDIA-kernel-module-source-TempVersion/src/common/sdk/nvidia/inc/ctrl/ctrl0000/ctrl0000syncgpuboost.h
6e5b278451308efbb6911a8ab03b0feba504d035 - NVIDIA-kernel-module-source-TempVersion/src/common/sdk/nvidia/inc/ctrl/ctrl0000/ctrl0000client.h
c905766589d17fcb99a5d73846ed61f7b7db56fe - NVIDIA-kernel-module-source-TempVersion/src/common/sdk/nvidia/inc/ctrl/ctrl0000/ctrl0000event.h
323fcc6af8c30d5ef292ae90810c5c2fa2009e20 - NVIDIA-kernel-module-source-TempVersion/src/common/sdk/nvidia/inc/ctrl/ctrl0000/ctrl0000proc.h
382dc80790d870047db7cea957ef208d4439801e - NVIDIA-kernel-module-source-TempVersion/src/common/sdk/nvidia/inc/ctrl/ctrl0000/ctrl0000gspc.h
825f4d976c76d375803e42967fdab53e7814d18d - NVIDIA-kernel-module-source-TempVersion/src/common/sdk/nvidia/inc/ctrl/ctrl0000/ctrl0000gsync.h
8294d43d202a9cd78367f2e69388a6c6f2c369f7 - NVIDIA-kernel-module-source-TempVersion/src/common/sdk/nvidia/inc/ctrl/ctrlc372/ctrlc372base.h
cf78a847e0882e1d164eccdb86ea033126019599 - NVIDIA-kernel-module-source-TempVersion/src/common/sdk/nvidia/inc/ctrl/ctrlc372/ctrlc372chnc.h
76c31150e2f589fbb96cfc06cdc6c1801e128656 - NVIDIA-kernel-module-source-TempVersion/src/common/sdk/nvidia/inc/ctrl/ctrlc370/ctrlc370base.h
7f5548026751a8caaebc245945ccdc4bb037b566 - NVIDIA-kernel-module-source-TempVersion/src/common/sdk/nvidia/inc/ctrl/ctrlc370/ctrlc370chnc.h
7812ba094d95c1b6d65afc6a1d26930400b8b96f - NVIDIA-kernel-module-source-TempVersion/src/common/sdk/nvidia/inc/ctrl/ctrlc370/ctrlc370event.h
f1dae17e75a24c28135cf073bf29f9609a2418e3 - NVIDIA-kernel-module-source-TempVersion/src/common/sdk/nvidia/inc/ctrl/ctrlc370/ctrlc370rg.h
24782552a13f627e2e94ebb5f7021246a0c0dc53 - NVIDIA-kernel-module-source-TempVersion/src/common/sdk/nvidia/inc/ctrl/ctrlc370/ctrlc370verif.h
127f78d2bb92ef3f74effd00c2c67cf7db5382fe - NVIDIA-kernel-module-source-TempVersion/src/common/sdk/nvidia/inc/class/clc67d.h
bb79bbd1b0a37283802bc59f184abe0f9ced08a5 - NVIDIA-kernel-module-source-TempVersion/src/common/sdk/nvidia/inc/class/cl0040.h
4a6444c347825e06bdd62401120553469f79c188 - NVIDIA-kernel-module-source-TempVersion/src/common/sdk/nvidia/inc/class/cl917dcrcnotif.h
2f87e87bcf9f38017ad84417d332a6aa7022c88f - NVIDIA-kernel-module-source-TempVersion/src/common/sdk/nvidia/inc/class/cl9471.h
0d8975eec1e3222694e98eb69ddb2c01accf1ba6 - NVIDIA-kernel-module-source-TempVersion/src/common/sdk/nvidia/inc/class/cl0000_notification.h
c2600834921f8a6aad6a0404076fa76f9bc1c04d - NVIDIA-kernel-module-source-TempVersion/src/common/sdk/nvidia/inc/class/clc37b.h
861b9d7581eab4a2b8cc7269b5d0e0d1294048d1 - NVIDIA-kernel-module-source-TempVersion/src/common/sdk/nvidia/inc/class/cl0005.h
92c2dab6bc48f32f46c6bbc282c63cb4ec7a50bf - NVIDIA-kernel-module-source-TempVersion/src/common/sdk/nvidia/inc/class/cl9170.h
0285aed652c6aedd392092cdf2c7b28fde13a263 - NVIDIA-kernel-module-source-TempVersion/src/common/sdk/nvidia/inc/class/cl00fc.h
dec74b9cf8062f1a0a8bbeca58b4f98722fd94b0 - NVIDIA-kernel-module-source-TempVersion/src/common/sdk/nvidia/inc/class/cl0076.h
a30755b3003023c093f8724cf9a2e0b0c301b586 - NVIDIA-kernel-module-source-TempVersion/src/common/sdk/nvidia/inc/class/cl9010.h
cb610aaae807d182b4a2ee46b9b43ebfa4a49a08 - NVIDIA-kernel-module-source-TempVersion/src/common/sdk/nvidia/inc/class/clc57e.h
bb8d15aee43e1feb76fddf80398e93fd805f1ddb - NVIDIA-kernel-module-source-TempVersion/src/common/sdk/nvidia/inc/class/cl2082.h
02906b5ba8aab0736a38fd1f6d7b4f6026a5185b - NVIDIA-kernel-module-source-TempVersion/src/common/sdk/nvidia/inc/class/clc57esw.h
ccefba28a2c7979701f963f2c358b4414b84ca98 - NVIDIA-kernel-module-source-TempVersion/src/common/sdk/nvidia/inc/class/cl9570.h
2e3d5c71793820d90973d547d8afdf41ff989f89 - NVIDIA-kernel-module-source-TempVersion/src/common/sdk/nvidia/inc/class/clc67a.h
204feb997ba42deab327d570e5f12235d5160f00 - NVIDIA-kernel-module-source-TempVersion/src/common/sdk/nvidia/inc/class/clc57a.h
03ab4e08e8685696477b62eb1a825e5198d61b8a - NVIDIA-kernel-module-source-TempVersion/src/common/sdk/nvidia/inc/class/cl0080.h
545dd1899c6988ffe5f50300232bd862d915cd5b - NVIDIA-kernel-module-source-TempVersion/src/common/sdk/nvidia/inc/class/clc770.h
022e8405220e482f83629dd482efee81cc49f665 - NVIDIA-kernel-module-source-TempVersion/src/common/sdk/nvidia/inc/class/clc77f.h
36b0dd6de0d0b49d435a4662c35d1f4ae5b2b1bc - NVIDIA-kernel-module-source-TempVersion/src/common/sdk/nvidia/inc/class/cl9870.h
02ff42b6686954e4571b8a318575372239db623b - NVIDIA-kernel-module-source-TempVersion/src/common/sdk/nvidia/inc/class/cl30f1_notification.h
82c9df617999f93ebd9362851966f601b8131fdd - NVIDIA-kernel-module-source-TempVersion/src/common/sdk/nvidia/inc/class/clc570.h
eac86d7180236683b86f980f89ec7ebfe6c85791 - NVIDIA-kernel-module-source-TempVersion/src/common/sdk/nvidia/inc/class/cl957d.h
866977d299eac812b41eb702a517e27bdc56e875 - NVIDIA-kernel-module-source-TempVersion/src/common/sdk/nvidia/inc/class/clc37a.h
78259dc2a70da76ef222ac2dc460fe3caa32457a - NVIDIA-kernel-module-source-TempVersion/src/common/sdk/nvidia/inc/class/clc37e.h
31939808cd46382b1c63bc1e0bd4af953302773f - NVIDIA-kernel-module-source-TempVersion/src/common/sdk/nvidia/inc/class/cl977d.h
11fd2de68ab82b81211aa20c66a9a6595199f673 - NVIDIA-kernel-module-source-TempVersion/src/common/sdk/nvidia/inc/class/cl9270.h
05605d914edda157385e430ccdbeb3fcd8ad3c36 - NVIDIA-kernel-module-source-TempVersion/src/common/sdk/nvidia/inc/class/cl9171.h
9db39be032023bff165cd9d36bee2466617015a5 - NVIDIA-kernel-module-source-TempVersion/src/common/sdk/nvidia/inc/class/cl0002.h
76c430d54887ed14cace9409712259e10f042b4c - NVIDIA-kernel-module-source-TempVersion/src/common/sdk/nvidia/inc/class/cl00c1.h
e63ed2e1ff3fe2a5b29cfc334d3da611db2aadf6 - NVIDIA-kernel-module-source-TempVersion/src/common/sdk/nvidia/inc/class/clc37dcrcnotif.h
ea10b0d938d9314638882fdc20b9158a193f7b08 - NVIDIA-kernel-module-source-TempVersion/src/common/sdk/nvidia/inc/class/cl5070.h
f5760f5054538f4ecf04d94fb1582a80a930bc29 - NVIDIA-kernel-module-source-TempVersion/src/common/sdk/nvidia/inc/class/clc673.h
b1133e9abe15cf7b22c04d9627afa2027e781b81 - NVIDIA-kernel-module-source-TempVersion/src/common/sdk/nvidia/inc/class/cl917c.h
9bd9f416844d798f352fcc6c8aaf2c251253c068 - NVIDIA-kernel-module-source-TempVersion/src/common/sdk/nvidia/inc/class/cl90cd.h
04ab1761d913030cb7485149ecd365f2f9c0f7da - NVIDIA-kernel-module-source-TempVersion/src/common/sdk/nvidia/inc/class/cl0005_notification.h
fb5ef3d6734a2ee6baba7981cdf6419d013cee85 - NVIDIA-kernel-module-source-TempVersion/src/common/sdk/nvidia/inc/class/clc671.h
ddbffcce44afa7c07924fd64a608f7f3fe608ccc - NVIDIA-kernel-module-source-TempVersion/src/common/sdk/nvidia/inc/class/cl0071.h
68c953956a63ef8f7f9bcbe71057af510f4597c1 - NVIDIA-kernel-module-source-TempVersion/src/common/sdk/nvidia/inc/class/clb0b5sw.h
38265d86eb7c771d2d3fc5102d53e6a170a7f560 - NVIDIA-kernel-module-source-TempVersion/src/common/sdk/nvidia/inc/class/cl0041.h
941a031920c0b3bb16473a6a3d4ba8c52c1259d7 - NVIDIA-kernel-module-source-TempVersion/src/common/sdk/nvidia/inc/class/cl917e.h
a23967cf3b15eefe0cc37fef5d03dfc716770d85 - NVIDIA-kernel-module-source-TempVersion/src/common/sdk/nvidia/inc/class/clc372sw.h
9b2d08d7a37beea802642f807d40413c7f9a8212 - NVIDIA-kernel-module-source-TempVersion/src/common/sdk/nvidia/inc/class/clc37d.h
e0c9a155f829c158c02c21b49c083168f8b00cbe - NVIDIA-kernel-module-source-TempVersion/src/common/sdk/nvidia/inc/class/clc37dswspare.h
95d99f0805c8451f0f221483b3618e4dbd1e1dd8 - NVIDIA-kernel-module-source-TempVersion/src/common/sdk/nvidia/inc/class/cl90f1.h
8b75d2586151302d181f59d314b6b3f9f80b8986 - NVIDIA-kernel-module-source-TempVersion/src/common/sdk/nvidia/inc/class/clc573.h
ff47d8a4b4bdb3b9cd04ddb7666005ac7fcf2231 - NVIDIA-kernel-module-source-TempVersion/src/common/sdk/nvidia/inc/class/cl003e.h
026f66c4cc7baad36f1af740ae885dae58498e07 - NVIDIA-kernel-module-source-TempVersion/src/common/sdk/nvidia/inc/class/clc371.h
15136a724baab270914a01a8c0e8f2c2c83675b6 - NVIDIA-kernel-module-source-TempVersion/src/common/sdk/nvidia/inc/class/cl00c3.h
4bbb861011139be1c76b521eaa7ae10951d5bf9a - NVIDIA-kernel-module-source-TempVersion/src/common/sdk/nvidia/inc/class/cl2081.h
d1a19dee52b3318714026f4fcc748cfa4681cd25 - NVIDIA-kernel-module-source-TempVersion/src/common/sdk/nvidia/inc/class/clc370.h
158c98c8721d558ab64a025e6fdd04ce7a16ba9e - NVIDIA-kernel-module-source-TempVersion/src/common/sdk/nvidia/inc/class/cl947d.h
435a34753d445eb9711c7132d70bd26df2b8bdab - NVIDIA-kernel-module-source-TempVersion/src/common/sdk/nvidia/inc/class/cl917d.h
326dbbeb275b4fc29f6a7e2e42b32736474fec04 - NVIDIA-kernel-module-source-TempVersion/src/common/sdk/nvidia/inc/class/cl9571.h
1409efc057e4f0d55602f374ec006f9db7ad3926 - NVIDIA-kernel-module-source-TempVersion/src/common/sdk/nvidia/inc/class/cl0000.h
bd27ceb75c4604fef53658f16a5012d97c1534b2 - NVIDIA-kernel-module-source-TempVersion/src/common/sdk/nvidia/inc/class/cl9470.h
e6818f1728a66a70080e87dac15a6f92dd875b4e - NVIDIA-kernel-module-source-TempVersion/src/common/sdk/nvidia/inc/class/cl927d.h
11b19cb8d722146044ad5a12ae96c13ed5b122b6 - NVIDIA-kernel-module-source-TempVersion/src/common/sdk/nvidia/inc/class/cl917b.h
1efc9d4aa038f208cd19533f6188ac3a629bf31a - NVIDIA-kernel-module-source-TempVersion/src/common/sdk/nvidia/inc/class/cl917a.h
c2d8bb02052e80cd0d11695e734f5e05ab7faeb5 - NVIDIA-kernel-module-source-TempVersion/src/common/sdk/nvidia/inc/class/cl907dswspare.h
4b8f95693f79a036317ab2f85e150c102ad782e9 - NVIDIA-kernel-module-source-TempVersion/src/common/sdk/nvidia/inc/class/cl84a0.h
a7c7899429766c092ee3ecf5f672b75bef55216c - NVIDIA-kernel-module-source-TempVersion/src/common/sdk/nvidia/inc/class/cl9271.h
15d1f928a9b3f36065e377e29367577ae92ab065 - NVIDIA-kernel-module-source-TempVersion/src/common/sdk/nvidia/inc/class/cl0080_notification.h
a26ddc6c62faac1ecd5c5f43499aab32c70f32cb - NVIDIA-kernel-module-source-TempVersion/src/common/sdk/nvidia/inc/class/clc67b.h
b29ba657f62f8d8d28a8bdd2976ef3ac8aa6075f - NVIDIA-kernel-module-source-TempVersion/src/common/sdk/nvidia/inc/class/cl0073.h
c5ef1b16b2bd2e33f52b71f2b78db789ebb844f0 - NVIDIA-kernel-module-source-TempVersion/src/common/sdk/nvidia/inc/class/cl9770.h
ecc56a5803b85187aa95b788aedd4fa2262c1bb6 - NVIDIA-kernel-module-source-TempVersion/src/common/sdk/nvidia/inc/class/cl2080.h
dd4f75c438d19c27e52f25b36fc8ded1ce02133c - NVIDIA-kernel-module-source-TempVersion/src/common/sdk/nvidia/inc/class/cl917cswspare.h
6db83e33cb3432f34d4b55c3de222eaf793a90f0 - NVIDIA-kernel-module-source-TempVersion/src/common/sdk/nvidia/inc/class/cl00b1.h
b29ea3f13f501327c060b9ddfac5834ed396414a - NVIDIA-kernel-module-source-TempVersion/src/common/sdk/nvidia/inc/class/cl30f1.h
4d5ccf08ab73343343e0c804002a621996866161 - NVIDIA-kernel-module-source-TempVersion/src/common/sdk/nvidia/inc/class/cl0092.h
593384ce8938ceeec46c782d6869eda3c7b8c274 - NVIDIA-kernel-module-source-TempVersion/src/common/sdk/nvidia/inc/class/cl900e.h
95ca0b08eed54d1c6dd76fdf9cf4715007df1b20 - NVIDIA-kernel-module-source-TempVersion/src/common/sdk/nvidia/inc/class/cl0020.h
c61f8348c2978eef0a07191aaf92bd73e935f7bd - NVIDIA-kernel-module-source-TempVersion/src/common/sdk/nvidia/inc/class/clc67e.h
509c56534ed6d48b06494bb22d3cf58d63254a05 - NVIDIA-kernel-module-source-TempVersion/src/common/sdk/nvidia/inc/class/clc574.h
da8d312d2fdc6012e354df4fa71ed62ae4aac369 - NVIDIA-kernel-module-source-TempVersion/src/common/sdk/nvidia/inc/class/cl927c.h
5416c871e8d50a4e76cbad446030dbedbe1644fd - NVIDIA-kernel-module-source-TempVersion/src/common/sdk/nvidia/inc/class/cl00f2.h
b7a5b31a8c3606aa98ba823e37e21520b55ba95c - NVIDIA-kernel-module-source-TempVersion/src/common/sdk/nvidia/inc/class/cl402c.h
26c3ccc33328a66ad3bcfe999424dffda991264f - NVIDIA-kernel-module-source-TempVersion/src/common/sdk/nvidia/inc/class/clc670.h
28867d69a6ceac83da53a11a5e1ef87d9476f0be - NVIDIA-kernel-module-source-TempVersion/src/common/sdk/nvidia/inc/class/clc57d.h
053e3c0de24348d3f7e7fe9cbd1743f46be7a978 - NVIDIA-kernel-module-source-TempVersion/src/common/sdk/nvidia/inc/class/cl0004.h
060722ac6a529a379375bb399785cbf2380db4fd - NVIDIA-kernel-module-source-TempVersion/src/common/sdk/nvidia/inc/class/clc373.h
13f8e49349460ef0480b74a7043d0591cf3eb68f - NVIDIA-kernel-module-source-TempVersion/src/common/sdk/nvidia/inc/class/clc57b.h
e72a7871d872b2eb823cc67c0a7d4cafb3d0ca18 - NVIDIA-kernel-module-source-TempVersion/src/common/sdk/nvidia/inc/class/cl90ec.h
ba76ecbebe0ed71ea861ed7016abbfc16ced2df7 - NVIDIA-kernel-module-source-TempVersion/src/common/sdk/nvidia/inc/class/cl5070_notification.h
bae36cac0a8d83003ded2305409192995d264d04 - NVIDIA-kernel-module-source-TempVersion/src/common/sdk/nvidia/inc/class/cl0001.h
ab27db8414f1400a3f4d9011e83ac49628b4fe91 - NVIDIA-kernel-module-source-TempVersion/src/common/sdk/nvidia/inc/class/cl987d.h
70b155b0da07a92ede884a9cec715f67e6b5c3e8 - NVIDIA-kernel-module-source-TempVersion/src/common/displayport/src/dp_list.cpp
c70d946adb4029b3476873887488748162b88b0b - NVIDIA-kernel-module-source-TempVersion/src/common/displayport/src/dp_messagecodings.cpp
ac08ccd5c2e3fadf10ae53e46e582489d1579ed0 - NVIDIA-kernel-module-source-TempVersion/src/common/displayport/src/dp_edid.cpp
6fd536d1849ea4cce5d9b72d1dcbc1db9c818b4e - NVIDIA-kernel-module-source-TempVersion/src/common/displayport/src/dp_groupimpl.cpp
d63fed0074b22584686ad4d0cdaa4388b42194d6 - NVIDIA-kernel-module-source-TempVersion/src/common/displayport/src/dp_watermark.cpp
a5df56b2cf8df9d4d8ab6fa2b3521649ef09384a - NVIDIA-kernel-module-source-TempVersion/src/common/displayport/src/dp_wardatabase.cpp
f56f92e32710b0342805b785d34ba1a9f2a54ed3 - NVIDIA-kernel-module-source-TempVersion/src/common/displayport/src/dp_guid.cpp
554e6b7dadbb68ac0f3d2e368ca3fd90832ea254 - NVIDIA-kernel-module-source-TempVersion/src/common/displayport/src/dp_discovery.cpp
60994cb1131d4d37b2d3fce6cc59dfea5ebb4129 - NVIDIA-kernel-module-source-TempVersion/src/common/displayport/src/dp_connectorimpl.cpp
37eabb1ab51cb38660eb24e294c63c8320750b96 - NVIDIA-kernel-module-source-TempVersion/src/common/displayport/src/dp_sst_edid.cpp
a0d24a4bd71f999adbaa876168adef5a7d95f2b8 - NVIDIA-kernel-module-source-TempVersion/src/common/displayport/src/dp_configcaps.cpp
fa4f4869d3d63c0180f30ae3736600a6627284c6 - NVIDIA-kernel-module-source-TempVersion/src/common/displayport/src/dp_merger.cpp
d991afdb694634e9df756184b5951739fc3fd0ab - NVIDIA-kernel-module-source-TempVersion/src/common/displayport/src/dp_auxretry.cpp
1543bbaba8f3e149239cf44be3c0d080c624d5ba - NVIDIA-kernel-module-source-TempVersion/src/common/displayport/src/dp_buffer.cpp
56ee9318a7b51a04baa1d25d7d9a798c733dc1bc - NVIDIA-kernel-module-source-TempVersion/src/common/displayport/src/dp_vrr.cpp
9f31213ab8037d7bb18c96a67d2630d61546544a - NVIDIA-kernel-module-source-TempVersion/src/common/displayport/src/dp_mst_edid.cpp
fea946e5320e7de8e9229bca8d4a6a14b9e8db59 - NVIDIA-kernel-module-source-TempVersion/src/common/displayport/src/dp_crc.cpp
719d2ddbfb8555636496cb5dd74ee6776059db92 - NVIDIA-kernel-module-source-TempVersion/src/common/displayport/src/dp_timer.cpp
f83b3c17e9f26651f12c8835a682abdd66aed3a2 - NVIDIA-kernel-module-source-TempVersion/src/common/displayport/src/dp_splitter.cpp
e874ffeaeb6deec57605bf91eaa2af116a9762bd - NVIDIA-kernel-module-source-TempVersion/src/common/displayport/src/dp_bitstream.cpp
c62ef84471074a9ed428b4a03e644885989b0b83 - NVIDIA-kernel-module-source-TempVersion/src/common/displayport/src/dp_evoadapter.cpp
38fe8122aba8a1bc5745d81192ec7fc75934dd0d - NVIDIA-kernel-module-source-TempVersion/src/common/displayport/src/dp_deviceimpl.cpp
66e91795dc65e1bc13c545a84556d200c8eb7bd5 - NVIDIA-kernel-module-source-TempVersion/src/common/displayport/src/dp_messages.cpp
4803cde0fffcf89fed46d6deaeba5c96c669a908 - NVIDIA-kernel-module-source-TempVersion/src/common/displayport/src/dp_messageheader.cpp
fe8007b3d98dad71b17595ecb67af77b198827a0 - NVIDIA-kernel-module-source-TempVersion/src/common/displayport/src/dptestutil/dp_testmessage.cpp
62d03d24af041276ba2abb96fa1634ae4f99ea8a - NVIDIA-kernel-module-source-TempVersion/src/common/displayport/inc/dp_connectorimpl.h
aeadcb0bc061b5db0fdf8aa67c1b5703976aa946 - NVIDIA-kernel-module-source-TempVersion/src/common/displayport/inc/dp_connector.h
01f1dd58ed5bb12503fa45be7a6657cde0a857e2 - NVIDIA-kernel-module-source-TempVersion/src/common/displayport/inc/dp_guid.h
07d22f84e6a386dad251761278a828dab64b6dd5 - NVIDIA-kernel-module-source-TempVersion/src/common/displayport/inc/dp_bitstream.h
11487c992494f502d1c48ff00982998504336800 - NVIDIA-kernel-module-source-TempVersion/src/common/displayport/inc/dp_internal.h
f6e1b0850f5ed0f23f263d4104523d9290bb8669 - NVIDIA-kernel-module-source-TempVersion/src/common/displayport/inc/dp_vrr.h
02b65d96a7a345eaa87042faf6dd94052235009c - NVIDIA-kernel-module-source-TempVersion/src/common/displayport/inc/dp_messageheader.h
e27519c72e533a69f7433638a1d292fb9df8772e - NVIDIA-kernel-module-source-TempVersion/src/common/displayport/inc/dp_crc.h
543efa25367763292067245cbc39c1382c35df77 - NVIDIA-kernel-module-source-TempVersion/src/common/displayport/inc/dp_discovery.h
39aece5465100489867001bf57446bcfc4999c24 - NVIDIA-kernel-module-source-TempVersion/src/common/displayport/inc/dp_evoadapter.h
6e515f398e9ae1b603e49ec32576ccd0ce5d8828 - NVIDIA-kernel-module-source-TempVersion/src/common/displayport/inc/dp_messagecodings.h
070b4f6216f19feebb6a67cbb9c3eb22dc60cf74 - NVIDIA-kernel-module-source-TempVersion/src/common/displayport/inc/dp_buffer.h
36e80dd13c5adc64c3adc9a931d5ebbf922e9502 - NVIDIA-kernel-module-source-TempVersion/src/common/displayport/inc/dp_groupimpl.h
7974abf146f1f14cd3e3854ef63ddf52ebbeb222 - NVIDIA-kernel-module-source-TempVersion/src/common/displayport/inc/dp_deviceimpl.h
cdb1e7797c250b0a7c0449e2df5ce71e42b83432 - NVIDIA-kernel-module-source-TempVersion/src/common/displayport/inc/dp_merger.h
0f747fdf03bebdcd86dbdf16d00ee2d044bc906c - NVIDIA-kernel-module-source-TempVersion/src/common/displayport/inc/dp_messages.h
325818d0a4d1b15447923e2ed92c938d293dc079 - NVIDIA-kernel-module-source-TempVersion/src/common/displayport/inc/dp_hostimp.h
2067e2ca3b86014c3e6dfc51d6574d87ae12d907 - NVIDIA-kernel-module-source-TempVersion/src/common/displayport/inc/dp_timer.h
d876d77caef3541ae05f310857f3d32e642fba04 - NVIDIA-kernel-module-source-TempVersion/src/common/displayport/inc/dp_auxdefs.h
78595e6262d5ab0e6232392dc0852feaf83c7585 - NVIDIA-kernel-module-source-TempVersion/src/common/displayport/inc/dp_auxbus.h
b4d8c44957efc90ba97092987e6e43c48e85ac86 - NVIDIA-kernel-module-source-TempVersion/src/common/displayport/inc/dp_address.h
78c6d7d85b47636fbb21153425ef90c6d0b2d4e2 - NVIDIA-kernel-module-source-TempVersion/src/common/displayport/inc/dp_configcaps.h
3b74682e142e94b1c68bf619169f12e5805044bc - NVIDIA-kernel-module-source-TempVersion/src/common/displayport/inc/dp_watermark.h
8f83883126b853c97e5859dafd98847ec54d36ac - NVIDIA-kernel-module-source-TempVersion/src/common/displayport/inc/dp_splitter.h
7b7d9a137027fbbedfc041465987fa4ed4198ce4 - NVIDIA-kernel-module-source-TempVersion/src/common/displayport/inc/dp_edid.h
cca426d571c6b01f7953180e2e550e55c629f0f4 - NVIDIA-kernel-module-source-TempVersion/src/common/displayport/inc/dp_auxretry.h
80380945c76c58648756446435d615f74630f2da - NVIDIA-kernel-module-source-TempVersion/src/common/displayport/inc/dp_timeout.h
e2075486b392d6b231f2f133922ac096ca4bc095 - NVIDIA-kernel-module-source-TempVersion/src/common/displayport/inc/dp_ringbuffer.h
3eea80c74a22de43b6edad21ea5873c791e093e2 - NVIDIA-kernel-module-source-TempVersion/src/common/displayport/inc/dp_mainlink.h
d1e8c84f279cb30978d32c784107c0247afa6e66 - NVIDIA-kernel-module-source-TempVersion/src/common/displayport/inc/dp_linkconfig.h
750ecc85242882a9e428d5a5cf1a64f418d59c5f - NVIDIA-kernel-module-source-TempVersion/src/common/displayport/inc/dp_object.h
379d3933c90eaf9c35a0bad2bd6af960a321465f - NVIDIA-kernel-module-source-TempVersion/src/common/displayport/inc/dp_wardatabase.h
e02e5621eaea52a2266a86dcd587f4714680caf4 - NVIDIA-kernel-module-source-TempVersion/src/common/displayport/inc/dp_linkedlist.h
5dff32bd1018e2c5c2540ea7fb571dbea596d5b1 - NVIDIA-kernel-module-source-TempVersion/src/common/displayport/inc/dp_regkeydatabase.h
4a098c4d09dedc33b86748d5fe9a30d097675e9f - NVIDIA-kernel-module-source-TempVersion/src/common/displayport/inc/dp_list.h
5bd3706ceea585df76a75dda7f9581b91ee8f998 - NVIDIA-kernel-module-source-TempVersion/src/common/displayport/inc/dp_tracing.h
020194b85245bad5de4dfe372a7ccb0c247d6ede - NVIDIA-kernel-module-source-TempVersion/src/common/displayport/inc/dptestutil/dp_testmessage.h
2f60ba753549b232e1b995046a356dbe0eced04a - NVIDIA-kernel-module-source-TempVersion/src/common/shared/nvstatus/nvstatus.c
ebccc5c2af2863509e957fe98b01d9a14d8b0367 - NVIDIA-kernel-module-source-TempVersion/src/common/inc/nv_list.h
48f063f09bd9b0cb6c4f47d8911643790b3ffbc8 - NVIDIA-kernel-module-source-TempVersion/src/common/inc/nvUnixVersion.h
b85b49fc4ed38a241c79731a02b3b040a654a52a - NVIDIA-kernel-module-source-TempVersion/src/common/inc/nvctassert.h
764e5c4364922e3953b4db0411d1d3c3bdac99f4 - NVIDIA-kernel-module-source-TempVersion/src/common/inc/nvlog_defs.h
8f0d91e1a8f0d3474fb91dc3e6234e55d2c79fcc - NVIDIA-kernel-module-source-TempVersion/src/common/inc/rmosxfac.h
f59a2759281341e56372d3cb37b16715944dd8e1 - NVIDIA-kernel-module-source-TempVersion/src/common/inc/nvPNPVendorIds.h
e015e955a05908d4a2202213353eac89f1b80ff6 - NVIDIA-kernel-module-source-TempVersion/src/common/inc/nvSha1.h
b58ed1b4372a5c84d5f3755b7090b196179a2729 - NVIDIA-kernel-module-source-TempVersion/src/common/inc/nv_speculation_barrier.h
b4c5d759f035b540648117b1bff6b1701476a398 - NVIDIA-kernel-module-source-TempVersion/src/common/inc/nvCpuUuid.h
4282574b39d1bcaf394b63aca8769bb52462b89b - NVIDIA-kernel-module-source-TempVersion/src/common/inc/nvBinSegment.h
a27eb14c54c6acb647a95c264b90e25f07fc757e - NVIDIA-kernel-module-source-TempVersion/src/common/inc/nvBldVer.h
5257e84f2048b01258c78cec70987f158f6b0c44 - NVIDIA-kernel-module-source-TempVersion/src/common/inc/nvlog_inc.h
963aebc9ec7bcb9c445eee419f72289b21680cdd - NVIDIA-kernel-module-source-TempVersion/src/common/inc/hdmi_spec.h
62e510fa46465f69e9c55fabf1c8124bee3091c4 - NVIDIA-kernel-module-source-TempVersion/src/common/inc/nvHdmiFrlCommon.h
3bf0416186ee90833c727f01cc891bd568ea9d0f - NVIDIA-kernel-module-source-TempVersion/src/common/inc/nvVer.h
a346380cebac17412b4efc0aef2fad27c33b8fb5 - NVIDIA-kernel-module-source-TempVersion/src/common/inc/nvlog_inc2.h
d2b4cc6228c4b13ef77e47bf30326826c5662ed4 - NVIDIA-kernel-module-source-TempVersion/src/common/inc/swref/published/nv_ref.h
06aa739230c00998e039b0104e5d73da85c322fe - NVIDIA-kernel-module-source-TempVersion/src/common/inc/swref/published/nv_arch.h
86a59440492fd6f869aef3509f0e64a492b4550d - NVIDIA-kernel-module-source-TempVersion/src/common/inc/swref/published/turing/tu102/dev_mmu.h
38edc89fd4148b5b013b9e07081ba1e9b34516ac - NVIDIA-kernel-module-source-TempVersion/src/common/inc/swref/published/turing/tu102/kind_macros.h
f9311a35f375c7453d99fdde3876440b54d4cb5a - NVIDIA-kernel-module-source-TempVersion/src/common/inc/swref/published/disp/v03_00/dev_disp.h
1ea0c3d6ea0c79c01accc7b25d15b421ab49a55d - NVIDIA-kernel-module-source-TempVersion/src/common/inc/swref/published/disp/v04_02/dev_disp.h
a26df21c3cc3eeb395428101f11da68386e0d72b - NVIDIA-kernel-module-source-TempVersion/src/common/inc/displayport/dpcd14.h
8159b4189c577d545c1280d7d905a2dc2ba29fa7 - NVIDIA-kernel-module-source-TempVersion/src/common/inc/displayport/dpcd.h
96b9560d322f43a980db5d6cc5072e9e81fdb9d2 - NVIDIA-kernel-module-source-TempVersion/src/common/inc/displayport/displayport.h
249d4f7317ce68c3ceb64e2b1ee257cc75eb002b - NVIDIA-kernel-module-source-TempVersion/src/common/inc/displayport/dpcd20.h
8c43da4fae8a0aeb374ce46ce19eb8c38b552ae4 - NVIDIA-kernel-module-source-TempVersion/src/nvidia-modeset/Makefile
17855f638fd09abfec7d188e49b396793a9f6106 - NVIDIA-kernel-module-source-TempVersion/src/nvidia-modeset/os-interface/include/nvkms.h
7d108165b4a7b6a44ac21460ea3bf4381fb48c5b - NVIDIA-kernel-module-source-TempVersion/src/nvidia-modeset/os-interface/include/nvidia-modeset-os-interface.h
16a2e187afedf93bade7967816b0723708544e0d - NVIDIA-kernel-module-source-TempVersion/src/nvidia-modeset/include/nvkms-modeset-workarea.h
20213d53bb52bf9f38400e35d7963d0f4db22f96 - NVIDIA-kernel-module-source-TempVersion/src/nvidia-modeset/include/nvkms-evo-states.h
70d9251f331bbf28f5c5bbdf939ebad94db9362d - NVIDIA-kernel-module-source-TempVersion/src/nvidia-modeset/include/nvkms-softfloat.h
8a6f26ccf2e563b78f6e189c999ba470ed35271d - NVIDIA-kernel-module-source-TempVersion/src/nvidia-modeset/include/nvkms-evo.h
853d9005ec695cb5a1c7966a1f93fe0c9c8278cf - NVIDIA-kernel-module-source-TempVersion/src/nvidia-modeset/include/nvkms-hdmi.h
d4889d903bf4de06d85e55b005206ed57f28af69 - NVIDIA-kernel-module-source-TempVersion/src/nvidia-modeset/include/nvkms-lut.h
6b21a68e254becdd2641bc456f194f54c23abe51 - NVIDIA-kernel-module-source-TempVersion/src/nvidia-modeset/include/nvkms-framelock.h
c1c7047929aafc849a924c7fa9f8bc206b8e7524 - NVIDIA-kernel-module-source-TempVersion/src/nvidia-modeset/include/g_nvkms-evo-states.h
71e8c5d3c4dfec6f2261654c3fc91210bff78da9 - NVIDIA-kernel-module-source-TempVersion/src/nvidia-modeset/include/nvkms-surface.h
64af1df50d2a5b827c1c829a303844de20527522 - NVIDIA-kernel-module-source-TempVersion/src/nvidia-modeset/include/nvkms-rm.h
260b6ef87c755e55a803adad4ce49f2d57315f9a - NVIDIA-kernel-module-source-TempVersion/src/nvidia-modeset/include/nvkms-event.h
4f5d723c80f607a0e5f797835d561795dbe40ada - NVIDIA-kernel-module-source-TempVersion/src/nvidia-modeset/include/nvkms-cursor.h
f5f3b11c78a8b0eef40c09e1751615a47f516edb - NVIDIA-kernel-module-source-TempVersion/src/nvidia-modeset/include/nvkms-hal.h
d3f5bc85b538a3a1d4c2389c81001be91205ec9f - NVIDIA-kernel-module-source-TempVersion/src/nvidia-modeset/include/nvkms-modeset-types.h
9c90df1fa1b6dd33a7e330c47e94b5b9194ad419 - NVIDIA-kernel-module-source-TempVersion/src/nvidia-modeset/include/nvkms-3dvision.h
be3a1682574426c1bf75fcdf88278c18f2783c3f - NVIDIA-kernel-module-source-TempVersion/src/nvidia-modeset/include/nvkms-dpy.h
8f1994f3f8d100ddcf8b23f5b24872bed939d885 - NVIDIA-kernel-module-source-TempVersion/src/nvidia-modeset/include/nvkms-vrr.h
75e8a8747795fad89b4d2b662477e5454863dcc7 - NVIDIA-kernel-module-source-TempVersion/src/nvidia-modeset/include/nvkms-flip.h
d7861e2373ac04ffaf6c15caeba887f727aa41fb - NVIDIA-kernel-module-source-TempVersion/src/nvidia-modeset/include/nvkms-dma.h
182a47c12496b8b7da1c4fe7035d6b36d7316322 - NVIDIA-kernel-module-source-TempVersion/src/nvidia-modeset/include/nvkms-prealloc-types.h
c8f714e80dd4bb60ceab0c0c7e6a5b3304940946 - NVIDIA-kernel-module-source-TempVersion/src/nvidia-modeset/include/nvkms-types.h
ef78e73ec9c0b8341bd83306d1f3b2c35e20c43a - NVIDIA-kernel-module-source-TempVersion/src/nvidia-modeset/include/nvkms-utils.h
867e3091a945d3d43b2f28393b40edeb9d27597b - NVIDIA-kernel-module-source-TempVersion/src/nvidia-modeset/include/nvkms-rmapi.h
c1904d38785649d2614563d0cd7de28a15ce4486 - NVIDIA-kernel-module-source-TempVersion/src/nvidia-modeset/include/nvkms-modeset.h
118d0ea84ff81de16fbdc2c7daf249ee5c82ed6e - NVIDIA-kernel-module-source-TempVersion/src/nvidia-modeset/include/nvkms-modepool.h
412d8028a548e67e9ef85cb7d3f88385e70c56f9 - NVIDIA-kernel-module-source-TempVersion/src/nvidia-modeset/include/nvkms-console-restore.h
33dbf734c9757c2c40adb2fb185e964870217743 - NVIDIA-kernel-module-source-TempVersion/src/nvidia-modeset/include/nvkms-flip-workarea.h
ebafc51b2b274cd1818e471850a5efa9618eb17d - NVIDIA-kernel-module-source-TempVersion/src/nvidia-modeset/include/nvkms-prealloc.h
4020b2a0d4f177c143db40b33d122017416dfa2e - NVIDIA-kernel-module-source-TempVersion/src/nvidia-modeset/include/nvkms-evo1.h
be6e0e97c1e7ffc0daa2f14ef7b05b9f9c11dc16 - NVIDIA-kernel-module-source-TempVersion/src/nvidia-modeset/include/nvkms-attributes.h
9dd131355ed1e25a7cee7bfef00501cf6427ae92 - NVIDIA-kernel-module-source-TempVersion/src/nvidia-modeset/include/nvkms-private.h
17f6fbbd5e0a75faec21347b691f44dcb65c01aa - NVIDIA-kernel-module-source-TempVersion/src/nvidia-modeset/include/dp/nvdp-connector.h
4625828efd425e1b29835ab91fcc3d2d85e92389 - NVIDIA-kernel-module-source-TempVersion/src/nvidia-modeset/include/dp/nvdp-connector-event-sink.h
a8fbb7a071c0e7b326f384fed7547e7b6ec81c3e - NVIDIA-kernel-module-source-TempVersion/src/nvidia-modeset/include/dp/nvdp-timer.h
52b6c19cce320677bd3a4dfcf1698b236f29e59e - NVIDIA-kernel-module-source-TempVersion/src/nvidia-modeset/include/dp/nvdp-device.h
a0cc9f36fdd73c99ad8f264efa58043d42353b0a - NVIDIA-kernel-module-source-TempVersion/src/nvidia-modeset/lib/nvkms-sync.c
381fba24abae75d98b3ada184ed0cd57335819a9 - NVIDIA-kernel-module-source-TempVersion/src/nvidia-modeset/lib/nvkms-format.c
281fdc23f82d8bdb94b26d0093b444eb0c056f51 - NVIDIA-kernel-module-source-TempVersion/src/nvidia-modeset/interface/nvkms-sync.h
445a409950ab8f36cfa24d1dc73e59718d335263 - NVIDIA-kernel-module-source-TempVersion/src/nvidia-modeset/interface/nvkms-api.h
2ea1436104463c5e3d177e8574c3b4298976d37e - NVIDIA-kernel-module-source-TempVersion/src/nvidia-modeset/interface/nvkms-ioctl.h
5c4c05e5a638888babb5a8af2f0a61c94ecd150b - NVIDIA-kernel-module-source-TempVersion/src/nvidia-modeset/interface/nvkms-format.h
910255a4d92e002463175a28e38c3f24716fb654 - NVIDIA-kernel-module-source-TempVersion/src/nvidia-modeset/interface/nvkms-api-types.h
e48c2ec8145a6f2099dddb24d2900e3ae94ec02e - NVIDIA-kernel-module-source-TempVersion/src/nvidia-modeset/kapi/include/nvkms-kapi-internal.h
727bd77cfbc9ac4989c2ab7eec171ceb516510aa - NVIDIA-kernel-module-source-TempVersion/src/nvidia-modeset/kapi/include/nvkms-kapi-notifiers.h
009cd8e2b7ee8c0aeb05dac44cc84fc8f6f37c06 - NVIDIA-kernel-module-source-TempVersion/src/nvidia-modeset/kapi/interface/nvkms-kapi.h
fb242aa7a53983118ee019415076033e596374af - NVIDIA-kernel-module-source-TempVersion/src/nvidia-modeset/kapi/interface/nvkms-kapi-private.h
f6875ef0da055900ef6ef1da5dc94cba2837e4d0 - NVIDIA-kernel-module-source-TempVersion/src/nvidia-modeset/kapi/src/nvkms-kapi-channelevent.c
01d943d6edb0c647c2b8dbc44460948665b03e7a - NVIDIA-kernel-module-source-TempVersion/src/nvidia-modeset/kapi/src/nvkms-kapi-notifiers.c
394ea31caa5957cfb2c8bb8c3cc0e4703213fe7f - NVIDIA-kernel-module-source-TempVersion/src/nvidia-modeset/kapi/src/nvkms-kapi.c
ec97ab37cdf2cec0283657c2c04a139a1a168337 - NVIDIA-kernel-module-source-TempVersion/src/nvidia-modeset/src/nvkms-modepool.c
85ddb19f89833ca57fd2deff2e2b4566e162a56c - NVIDIA-kernel-module-source-TempVersion/src/nvidia-modeset/src/nvkms-hal.c
8415bcd6ab34e356374659e965790a0715ed7971 - NVIDIA-kernel-module-source-TempVersion/src/nvidia-modeset/src/nvkms-prealloc.c
c98f76bcfc7c654a619762ebc3a2599f9aa89f8d - NVIDIA-kernel-module-source-TempVersion/src/nvidia-modeset/src/nvkms-3dvision.c
5fb73f35841c41e7376531732cb12303224e61ad - NVIDIA-kernel-module-source-TempVersion/src/nvidia-modeset/src/nvkms-lut.c
e9626eee225e58ec2d5be756c5015775ca5e54b9 - NVIDIA-kernel-module-source-TempVersion/src/nvidia-modeset/src/nvkms-vrr.c
86da3c7c09354d2c49d95562aba15cbedb543d9b - NVIDIA-kernel-module-source-TempVersion/src/nvidia-modeset/src/nvkms-evo1.c
fc8182cc1f3af77125dbfa328996bcfe0387cc41 - NVIDIA-kernel-module-source-TempVersion/src/nvidia-modeset/src/nvkms-rm.c
05548338a73ade1b3c2ad1cebf1ab5eb16ef6c9b - NVIDIA-kernel-module-source-TempVersion/src/nvidia-modeset/src/nvkms-flip.c
07c2f10473e2fbe921b2781cc107b5e56e6373e3 - NVIDIA-kernel-module-source-TempVersion/src/nvidia-modeset/src/nvkms-attributes.c
21c8184de2c9150c21ac5d6fba24e79e513a0a69 - NVIDIA-kernel-module-source-TempVersion/src/nvidia-modeset/src/nvkms-evo.c
da726d20eea99a96af4c10aace88f419e8ee2a34 - NVIDIA-kernel-module-source-TempVersion/src/nvidia-modeset/src/nvkms-event.c
5c79c271609ebcc739f8d73d7d47f0b376298438 - NVIDIA-kernel-module-source-TempVersion/src/nvidia-modeset/src/nvkms-rmapi-dgpu.c
b55665d7bceaad04bbf29a68f44536518302c3d6 - NVIDIA-kernel-module-source-TempVersion/src/nvidia-modeset/src/nvkms-evo2.c
f8bdd07a27296ef6aab86cc9dbccf8df811fff24 - NVIDIA-kernel-module-source-TempVersion/src/nvidia-modeset/src/nvkms-modeset.c
1918ca3aa611cd9dfc79d46d038ab22706f0b1ed - NVIDIA-kernel-module-source-TempVersion/src/nvidia-modeset/src/nvkms-cursor3.c
24156462f25922c8de5b5d2558db36b2e68b28ed - NVIDIA-kernel-module-source-TempVersion/src/nvidia-modeset/src/nvkms-dpy.c
c2870190ca4c4d5b3a439386583d0a7c193d6263 - NVIDIA-kernel-module-source-TempVersion/src/nvidia-modeset/src/nvkms-hw-states.c
f27f52dc428a6adeb936c8cf99e1fc2d8b0ad667 - NVIDIA-kernel-module-source-TempVersion/src/nvidia-modeset/src/nvkms-dma.c
5acf19920d56793d96c80e8461b0d0213c871b34 - NVIDIA-kernel-module-source-TempVersion/src/nvidia-modeset/src/nvkms-surface.c
c2d0e6bef0c4929a3ca4adfd74bd6168fa4aa000 - NVIDIA-kernel-module-source-TempVersion/src/nvidia-modeset/src/nvkms-framelock.c
673ad86616f9863766bfec0e118c918297d32010 - NVIDIA-kernel-module-source-TempVersion/src/nvidia-modeset/src/g_nvkms-evo-states.c
c799d52bdc792efc377fb5cd307b0eb445c44d6a - NVIDIA-kernel-module-source-TempVersion/src/nvidia-modeset/src/nvkms-cursor2.c
94f4736acf7981cebfd74302a21f19cdbafa8d71 - NVIDIA-kernel-module-source-TempVersion/src/nvidia-modeset/src/nvkms-hdmi.c
8f22c278a5839d36f74f85469b2d927d9265cb80 - NVIDIA-kernel-module-source-TempVersion/src/nvidia-modeset/src/nvkms-utils.c
eb09642e8b5d9333699f817caaf20483c840b376 - NVIDIA-kernel-module-source-TempVersion/src/nvidia-modeset/src/nvkms.c
ab17e5b4cafa92aa03691a0c187ef8c9ae53fa59 - NVIDIA-kernel-module-source-TempVersion/src/nvidia-modeset/src/nvkms-cursor.c
574b1268ff83e4e5ed4da15609247a5c0ec8f51b - NVIDIA-kernel-module-source-TempVersion/src/nvidia-modeset/src/nvkms-console-restore.c
45230e56d29c98ea0f10f87c1b16ba70c96f24d5 - NVIDIA-kernel-module-source-TempVersion/src/nvidia-modeset/src/nvkms-evo3.c
8af6062034d464f778969e26d3bf5a9b4cdaccf0 - NVIDIA-kernel-module-source-TempVersion/src/nvidia-modeset/src/dp/nvdp-connector.cpp
69fed95ab3954dd5cb26590d02cd8ba09cdff1ac - NVIDIA-kernel-module-source-TempVersion/src/nvidia-modeset/src/dp/nvdp-connector-event-sink.hpp
6b985fc50b5040ce1a81418bed73a60edb5d3289 - NVIDIA-kernel-module-source-TempVersion/src/nvidia-modeset/src/dp/nvdp-timer.hpp
f2a05c29383bfc8631ad31909f31a8351501eb27 - NVIDIA-kernel-module-source-TempVersion/src/nvidia-modeset/src/dp/nvdp-device.cpp
31767fd551f3c89e5b00f54147b6a8e8fa3320e3 - NVIDIA-kernel-module-source-TempVersion/src/nvidia-modeset/src/dp/nvdp-connector-event-sink.cpp
110ac212ee8832c3fa3c4f45d6d33eed0301e992 - NVIDIA-kernel-module-source-TempVersion/src/nvidia-modeset/src/dp/nvdp-host.cpp
51af3c1ee6b74ee0c9add3fb7d50cbc502980789 - NVIDIA-kernel-module-source-TempVersion/src/nvidia-modeset/src/dp/nvdp-evo-interface.hpp
f96cd982b4c05351faa31d04ac30d6fa7c866bcb - NVIDIA-kernel-module-source-TempVersion/src/nvidia-modeset/src/dp/nvdp-timer.cpp
f6c3e8bd4ee13970737e96f9d9a3e4d8afdf9695 - NVIDIA-kernel-module-source-TempVersion/src/nvidia-modeset/src/dp/nvdp-evo-interface.cpp
893c70c95809f463c7af6dc9c814527804fcdf53 - NVIDIA-kernel-module-source-TempVersion/src/nvidia/Makefile
c5f16fdf43ca3d2845d120c219d1da11257072b0 - NVIDIA-kernel-module-source-TempVersion/src/nvidia/nv-kernel.ld
d1089d8ee0ffcdbf73a42d7c4edb90769aa79d8c - NVIDIA-kernel-module-source-TempVersion/src/nvidia/arch/nvalloc/common/inc/nvrangetypes.h
aba0bd796d932fa19e8fad55ed683ae57d68bffb - NVIDIA-kernel-module-source-TempVersion/src/nvidia/arch/nvalloc/unix/include/nv-priv.h
1d8b347e4b92c340a0e9eac77e0f63b9fb4ae977 - NVIDIA-kernel-module-source-TempVersion/src/nvidia/arch/nvalloc/unix/include/nv-ioctl-numbers.h
499e72dad20bcc283ee307471f8539b315211da4 - NVIDIA-kernel-module-source-TempVersion/src/nvidia/arch/nvalloc/unix/include/nv-unix-nvos-params-wrappers.h
40cb3c112bbcb6ae83a9186d0c9fa1857cf6a126 - NVIDIA-kernel-module-source-TempVersion/src/nvidia/arch/nvalloc/unix/include/os-interface.h
1b53bbf5f8452b8057ff2dd7828947a047db38d0 - NVIDIA-kernel-module-source-TempVersion/src/nvidia/arch/nvalloc/unix/include/nv_escape.h
3a26838c4edd3525daa68ac6fc7b06842dc6fc07 - NVIDIA-kernel-module-source-TempVersion/src/nvidia/arch/nvalloc/unix/include/nv-gpu-info.h
e3679844971ecc4447259fb1bdf4fafbbdff2395 - NVIDIA-kernel-module-source-TempVersion/src/nvidia/arch/nvalloc/unix/include/osapi.h
4750735d6f3b334499c81d499a06a654a052713d - NVIDIA-kernel-module-source-TempVersion/src/nvidia/arch/nvalloc/unix/include/nv-caps.h
1e89b4a52a5cdc6cac511ff148c7448d53cf5d5c - NVIDIA-kernel-module-source-TempVersion/src/nvidia/arch/nvalloc/unix/include/os_custom.h
fbcbb81ae14e8bfde0d665ad20f9cab9b0bbd9c3 - NVIDIA-kernel-module-source-TempVersion/src/nvidia/arch/nvalloc/unix/include/nv.h
ddfedb3b81feb09ea9daadf1a7f63f6309ee6e3b - NVIDIA-kernel-module-source-TempVersion/src/nvidia/arch/nvalloc/unix/include/rmobjexportimport.h
9c7b09c55aabbd670c860bdaf8ec9e8ff254b5e9 - NVIDIA-kernel-module-source-TempVersion/src/nvidia/arch/nvalloc/unix/include/nv-kernel-rmapi-ops.h
cc3b2163238b2a8acb7e3ca213fb1ae6c5f0a409 - NVIDIA-kernel-module-source-TempVersion/src/nvidia/arch/nvalloc/unix/include/osfuncs.h
2f5fec803685c61c13f7955baaed056b5524652c - NVIDIA-kernel-module-source-TempVersion/src/nvidia/arch/nvalloc/unix/include/nv-ioctl.h
285ab886f5fad5caf3f6bd0b0c7102bd4c4300bd - NVIDIA-kernel-module-source-TempVersion/src/nvidia/arch/nvalloc/unix/include/nv-reg.h
6ebda7ea5b17b7b9bfa9387fc838db9f0c3405a5 - NVIDIA-kernel-module-source-TempVersion/src/nvidia/arch/nvalloc/unix/src/osinit.c
b5b409625fde1b640e4e93276e35248f0fccfa4c - NVIDIA-kernel-module-source-TempVersion/src/nvidia/arch/nvalloc/unix/src/gcc_helper.c
9d9035afd7af31f30cdbf2d4c75e5e09180f0981 - NVIDIA-kernel-module-source-TempVersion/src/nvidia/arch/nvalloc/unix/src/osunix.c
21ac9d6932199ce0755dbead297eb03c9900f8c9 - NVIDIA-kernel-module-source-TempVersion/src/nvidia/arch/nvalloc/unix/src/power-management-tegra.c
49dc935d4475b572478c63324f0832c972a4277d - NVIDIA-kernel-module-source-TempVersion/src/nvidia/arch/nvalloc/unix/src/os.c
532366fd9a288a812eca78b92b304ba3625f8c0a - NVIDIA-kernel-module-source-TempVersion/src/nvidia/arch/nvalloc/unix/src/exports-stubs.c
006e77a594ae98067059ad3d7e93821316859063 - NVIDIA-kernel-module-source-TempVersion/src/nvidia/arch/nvalloc/unix/src/os-hypervisor-stubs.c
f134270af5ecd7c5ba91bf5228fe3166b101dd6e - NVIDIA-kernel-module-source-TempVersion/src/nvidia/arch/nvalloc/unix/src/escape.c
690927567b5344c8030e2c52d91f824bb94e956c - NVIDIA-kernel-module-source-TempVersion/src/nvidia/arch/nvalloc/unix/src/registry.c
5940d8e83cd0014e3222952eab29eebaaad19b86 - NVIDIA-kernel-module-source-TempVersion/src/nvidia/arch/nvalloc/unix/src/osapi.c
54b912b640bdcae42f38c41694eb20abcaad61a7 - NVIDIA-kernel-module-source-TempVersion/src/nvidia/arch/nvalloc/unix/src/osmemdesc.c
fb5272f3d0e465aedbc99ddcabb1c6c428837a6e - NVIDIA-kernel-module-source-TempVersion/src/nvidia/arch/nvalloc/unix/src/rmobjexportimport.c
0cff83f4fdcc8d025cd68e0a12faaeead09fa03b - NVIDIA-kernel-module-source-TempVersion/src/nvidia/kernel/inc/tmr.h
7df66a87c9498ae73c986e60fcb9cb1cbcd19e19 - NVIDIA-kernel-module-source-TempVersion/src/nvidia/kernel/inc/objrpc.h
1feab39692ea8796ac7675f4780dfd51e6e16326 - NVIDIA-kernel-module-source-TempVersion/src/nvidia/kernel/inc/objtmr.h
28d6a6ae495d9bc032c084980ebf5d94448bcf29 - NVIDIA-kernel-module-source-TempVersion/src/nvidia/kernel/inc/vgpu/rpc_headers.h
31deee778df2651d3d21b4d9c8ab180b8dc1ff14 - NVIDIA-kernel-module-source-TempVersion/src/nvidia/kernel/inc/vgpu/rpc_vgpu.h
961ed81de50e67eadf163a3a8008ce1fde1d880c - NVIDIA-kernel-module-source-TempVersion/src/nvidia/kernel/inc/vgpu/rpc_hal_stubs.h
4db7387cc1ce08ccc62404b80b19c7f1b685e746 - NVIDIA-kernel-module-source-TempVersion/src/nvidia/kernel/inc/vgpu/rpc.h
e4d88af4eb51d32288f913d90e490e329884970b - NVIDIA-kernel-module-source-TempVersion/src/nvidia/kernel/inc/vgpu/rpc_global_enums.h
35da37c070544f565d0f1de82abc7569b5df06af - NVIDIA-kernel-module-source-TempVersion/src/nvidia/interface/nv_firmware_types.h
df4d313c66e75fa9f4a1ff8ea2c389a6ecd6eb3d - NVIDIA-kernel-module-source-TempVersion/src/nvidia/interface/acpigenfuncs.h
bff92c9767308a13df1d0858d5f9c82af155679a - NVIDIA-kernel-module-source-TempVersion/src/nvidia/interface/nvacpitypes.h
db0dc6915302888de06e3aa094d961cfe25e0059 - NVIDIA-kernel-module-source-TempVersion/src/nvidia/interface/nvrm_registry.h
059c1ab76a5f097593f0f8a79203e14a9cec6287 - NVIDIA-kernel-module-source-TempVersion/src/nvidia/interface/deprecated/rmapi_deprecated_utils.c
d50ff73efaf5bc7e9cb3f67ed07ede01e8fad6f6 - NVIDIA-kernel-module-source-TempVersion/src/nvidia/interface/deprecated/rmapi_deprecated.h
671286de97aa63201a363fd7a22c92ee8afe4c7c - NVIDIA-kernel-module-source-TempVersion/src/nvidia/src/kernel/gpu/eng_state.c
6fa4ba2da905692cd39ec09054f2bd6621aa2a7a - NVIDIA-kernel-module-source-TempVersion/src/nvidia/src/kernel/gpu/gpu_resource_desc.c
5a97d4f8ce101908f1a67ffe9cc8ed00b6bf43b2 - NVIDIA-kernel-module-source-TempVersion/src/nvidia/src/kernel/gpu/gpu_resource.c
1653c7b99cfc86db6692d9d8d6de19f1b24b9071 - NVIDIA-kernel-module-source-TempVersion/src/nvidia/src/kernel/gpu/gpu_uuid.c
caf2b80fa0f01b9a3efcd8326bf6375455f2e1b9 - NVIDIA-kernel-module-source-TempVersion/src/nvidia/src/kernel/gpu/gpu_access.c
4e1be780ac696a61f056933e5550040a2d42c6bd - NVIDIA-kernel-module-source-TempVersion/src/nvidia/src/kernel/gpu/gpu_device_mapping.c
0824d200569def5bf480f2a5127911ed0ea881e6 - NVIDIA-kernel-module-source-TempVersion/src/nvidia/src/kernel/gpu/device_share.c
f6b4e40b638faf9770b632b404170e1ceb949be5 - NVIDIA-kernel-module-source-TempVersion/src/nvidia/src/kernel/gpu/gpu_gspclient.c
db44a803d81d42bfaf84f7ea1e09dc53c662acef - NVIDIA-kernel-module-source-TempVersion/src/nvidia/src/kernel/gpu/gpu_timeout.c
9515ea68cdac85989e4d53d4c1251115291708dd - NVIDIA-kernel-module-source-TempVersion/src/nvidia/src/kernel/gpu/gpu.c
08be13ced6566aced2f3446bb657dae8efb41fbe - NVIDIA-kernel-module-source-TempVersion/src/nvidia/src/kernel/gpu/gpu_rmapi.c
77573c8518ac7622211c4bdd16524d369cc14b96 - NVIDIA-kernel-module-source-TempVersion/src/nvidia/src/kernel/gpu/device_ctrl.c
fa854efc5cdf4d167dee13302ee8377191624d95 - NVIDIA-kernel-module-source-TempVersion/src/nvidia/src/kernel/gpu/device.c
89543f7085fbc2ca01b5a8baae33b5de921c79e9 - NVIDIA-kernel-module-source-TempVersion/src/nvidia/src/kernel/gpu/gpu_t234d_kernel.c
0e4c2d88b61a0cf63045fe70e5ba2c81c44e37af - NVIDIA-kernel-module-source-TempVersion/src/nvidia/src/kernel/gpu/arch/t23x/kern_gpu_t234d.c
acb2a62fb60e08eb6d16518c43c974783139813b - NVIDIA-kernel-module-source-TempVersion/src/nvidia/src/kernel/gpu/timer/timer.c
834efbfff64c0d01272e49a08bd6196e341985a8 - NVIDIA-kernel-module-source-TempVersion/src/nvidia/src/kernel/gpu/timer/timer_ostimer.c
dd0bd914c6c7bfeabdd9fe87fb984702e0765624 - NVIDIA-kernel-module-source-TempVersion/src/nvidia/src/kernel/gpu/disp/disp_objs.c
19447ad30b3fc2ee308bcc45e3409bafa5defe0d - NVIDIA-kernel-module-source-TempVersion/src/nvidia/src/kernel/gpu/disp/disp_object_kern_ctrl_minimal.c
3abbef0a6fc95d6f7c7c5a16cbbbb51aaa457cc0 - NVIDIA-kernel-module-source-TempVersion/src/nvidia/src/kernel/gpu/disp/disp_sf_user.c
0918cada217ca1883527fe805fc30babf7b8038d - NVIDIA-kernel-module-source-TempVersion/src/nvidia/src/kernel/gpu/disp/disp_channel.c
e1a6dfb38025abeb5adfda929f61eb6ee44b5c84 - NVIDIA-kernel-module-source-TempVersion/src/nvidia/src/kernel/gpu/disp/disp_common_kern_ctrl_minimal.c
ed25b1e99b860468bbf22c10177e0ba99c73894f - NVIDIA-kernel-module-source-TempVersion/src/nvidia/src/kernel/gpu/disp/disp_capabilities.c
8cd12c2da71acede5046c772f14aff7cbd88af12 - NVIDIA-kernel-module-source-TempVersion/src/nvidia/src/kernel/gpu/disp/kern_disp.c
01e8b56f7677f5cb7f950d9aa9bd37d04153085b - NVIDIA-kernel-module-source-TempVersion/src/nvidia/src/kernel/gpu/disp/inst_mem/disp_inst_mem.c
629566bf98be863b12e6dc6aab53d8f5ea13988c - NVIDIA-kernel-module-source-TempVersion/src/nvidia/src/kernel/gpu/disp/inst_mem/arch/v03/disp_inst_mem_0300.c
b41502d73d7781496845377cebd0d445b8ca9dc6 - NVIDIA-kernel-module-source-TempVersion/src/nvidia/src/kernel/gpu/disp/arch/v03/kern_disp_0300.c
8a418dce9fbeb99d5d6e175ed8c88811866f3450 - NVIDIA-kernel-module-source-TempVersion/src/nvidia/src/kernel/gpu/disp/arch/v04/kern_disp_0402.c
e26ade846573c08f7494f17a233b8a9e14685329 - NVIDIA-kernel-module-source-TempVersion/src/nvidia/src/kernel/gpu/disp/head/kernel_head.c
d6e1bd038fa0eff5d3684a5a2c766fdac77f1198 - NVIDIA-kernel-module-source-TempVersion/src/nvidia/src/kernel/gpu/mem_mgr/mem_utils.c
d4a07d1c6beb7ddb229ed6e5374343b6ce916d84 - NVIDIA-kernel-module-source-TempVersion/src/nvidia/src/kernel/gpu/mem_mgr/mem_desc.c
bc2b57acc8fa8644615168e3ddbaf7ac161a7a04 - NVIDIA-kernel-module-source-TempVersion/src/nvidia/src/kernel/gpu/mem_mgr/context_dma.c
2bb921b462c4b50d1f42b39b4728374c7433c8cb - NVIDIA-kernel-module-source-TempVersion/src/nvidia/src/kernel/gpu/mem_mgr/arch/turing/mem_mgr_tu102_base.c
086e9a51757c3989dfe0bf89ca6c0b9c7734104a - NVIDIA-kernel-module-source-TempVersion/src/nvidia/src/kernel/gpu/subdevice/generic_engine.c
56be7a21457145c3c6b2df7beb4c828b7bd1a3b4 - NVIDIA-kernel-module-source-TempVersion/src/nvidia/src/kernel/gpu/subdevice/subdevice.c
5be208cc0e1eae1f85f00bb0b502fdba74d6656c - NVIDIA-kernel-module-source-TempVersion/src/nvidia/src/kernel/gpu/subdevice/subdevice_ctrl_timer_kernel.c
a64c51c515eb76208a822f1f623d11e2edd8d7ac - NVIDIA-kernel-module-source-TempVersion/src/nvidia/src/kernel/gpu/subdevice/subdevice_ctrl_gpu_kernel.c
a54628e9d2733c6d0470e1e73bca1573e6486ab3 - NVIDIA-kernel-module-source-TempVersion/src/nvidia/src/kernel/gpu/subdevice/subdevice_ctrl_event_kernel.c
1f4d15f959df38f4f6ea48c7b10fc859c6e04b12 - NVIDIA-kernel-module-source-TempVersion/src/nvidia/src/kernel/gpu/audio/hda_codec_api.c
ef2a3848e0302c09869a34eba1333d19a17acc56 - NVIDIA-kernel-module-source-TempVersion/src/nvidia/src/kernel/gpu/dce_client/dce_client_rpc.c
2c66e086bb149fb1b9ca8f860566a3f5e391b2f3 - NVIDIA-kernel-module-source-TempVersion/src/nvidia/src/kernel/gpu/dce_client/dce_client.c
f89e982b0e31a1898e1e4749c9a8ae9f0bb59a0c - NVIDIA-kernel-module-source-TempVersion/src/nvidia/src/kernel/rmapi/deprecated_context.c
d92267a3394ded5d7d218530fd16ce00a920b1d6 - NVIDIA-kernel-module-source-TempVersion/src/nvidia/src/kernel/rmapi/alloc_free.c
2279fd14aab9b5f20b8fc21f04dd0fca41e418c9 - NVIDIA-kernel-module-source-TempVersion/src/nvidia/src/kernel/rmapi/event_notification.c
11a547cbfdbce000a6e5edf48492f5b930ddbdca - NVIDIA-kernel-module-source-TempVersion/src/nvidia/src/kernel/rmapi/rs_utils.c
81f66675295315cfc52be225c2e9ee912b56fbac - NVIDIA-kernel-module-source-TempVersion/src/nvidia/src/kernel/rmapi/sharing.c
569f56831cde7bdc528ac2e543eea485025ec6f0 - NVIDIA-kernel-module-source-TempVersion/src/nvidia/src/kernel/rmapi/client.c
05669e008dfd89e5c81381e6c60230c1fe17a876 - NVIDIA-kernel-module-source-TempVersion/src/nvidia/src/kernel/rmapi/resource_desc.c
820b6e63c2b11b0764305c483142f626b6f72038 - NVIDIA-kernel-module-source-TempVersion/src/nvidia/src/kernel/rmapi/rpc_common.c
bc83726df04c30d02a1852a10a22c77fdb3ef7a7 - NVIDIA-kernel-module-source-TempVersion/src/nvidia/src/kernel/rmapi/resource_desc.h
5f194ba056b018a8194c16b0bbb6e49c1b80a996 - NVIDIA-kernel-module-source-TempVersion/src/nvidia/src/kernel/rmapi/param_copy.c
e40f6742084cd04252f3ec8b8499a26547b478bc - NVIDIA-kernel-module-source-TempVersion/src/nvidia/src/kernel/rmapi/mapping.c
ac6a5b3adf15eac4a7bd9ae24981f6f5fc727097 - NVIDIA-kernel-module-source-TempVersion/src/nvidia/src/kernel/rmapi/deprecated_context.h
3a0f999e390d93b0db8272f55fbec56f6b055fe4 - NVIDIA-kernel-module-source-TempVersion/src/nvidia/src/kernel/rmapi/rmapi_utils.c
78f1e379c3d1df9e34baba77f78f48b8585bdc74 - NVIDIA-kernel-module-source-TempVersion/src/nvidia/src/kernel/rmapi/event_buffer.c
8e40d2f35828468f34cf6863f9bf99c20dbfc827 - NVIDIA-kernel-module-source-TempVersion/src/nvidia/src/kernel/rmapi/rmapi_cache.c
b441ee824e9c15c82956254704949317024ceb41 - NVIDIA-kernel-module-source-TempVersion/src/nvidia/src/kernel/rmapi/entry_points.h
277441b3da96fc01199f1d2f5102490e2e6cd830 - NVIDIA-kernel-module-source-TempVersion/src/nvidia/src/kernel/rmapi/control.c
38d0205b68ea2c82709b42eb7e8b9cf92cec8828 - NVIDIA-kernel-module-source-TempVersion/src/nvidia/src/kernel/rmapi/rmapi_stubs.c
2f89b9059467e7f67a6a52c46aecae5cb0364ab6 - NVIDIA-kernel-module-source-TempVersion/src/nvidia/src/kernel/rmapi/binary_api.c
46aa43b18480d2eb7519b2dcd0fe6a68c79b8881 - NVIDIA-kernel-module-source-TempVersion/src/nvidia/src/kernel/rmapi/resource.c
f2c7d77e4183994d7ee414e2a87745fcd23d995e - NVIDIA-kernel-module-source-TempVersion/src/nvidia/src/kernel/rmapi/mapping_cpu.c
6f46dd43e4b3f2ad803a4c9492cb927aebffc1f0 - NVIDIA-kernel-module-source-TempVersion/src/nvidia/src/kernel/rmapi/client_resource.c
59d42b6a123b062237b3b6ca382211e35057ef1e - NVIDIA-kernel-module-source-TempVersion/src/nvidia/src/kernel/rmapi/resource_list.h
ddaf2b8e424df9147a4e2fecf3942b64b1d2b001 - NVIDIA-kernel-module-source-TempVersion/src/nvidia/src/kernel/rmapi/entry_points.c
68cc7b258f934097e9dc31a38e7e3bf2ce2fe5d1 - NVIDIA-kernel-module-source-TempVersion/src/nvidia/src/kernel/rmapi/event.c
c3820fa4bb1192a9317ca834aeee3434c7eb8059 - NVIDIA-kernel-module-source-TempVersion/src/nvidia/src/kernel/rmapi/rmapi.c
ea7be8a55a3310aa1c3926ed69c86a6491925e08 - NVIDIA-kernel-module-source-TempVersion/src/nvidia/src/kernel/diagnostics/nvlog.c
70507a8d43797eb3cdc13408ae8635f4a2eebce0 - NVIDIA-kernel-module-source-TempVersion/src/nvidia/src/kernel/diagnostics/nvlog_printf.c
b3a29311cc22e2dae686f8ed2df6bc828aa826cf - NVIDIA-kernel-module-source-TempVersion/src/nvidia/src/kernel/diagnostics/profiler.c
af4ffa4b423e07cf40eb863c11dbf515c7104874 - NVIDIA-kernel-module-source-TempVersion/src/nvidia/src/kernel/os/os_timer.c
1793e056a0afcc5e1f5bb58b207b49c5f1556eca - NVIDIA-kernel-module-source-TempVersion/src/nvidia/src/kernel/os/os_stubs.c
63e5e17280d865ace8cdd8eb8a2598d3d7830ad7 - NVIDIA-kernel-module-source-TempVersion/src/nvidia/src/kernel/os/os_sanity.c
8e5af753de1725dd919185c29d03ccb0934fab6e - NVIDIA-kernel-module-source-TempVersion/src/nvidia/src/kernel/os/os_init.c
fe91b43c37b64472450cc25329d2dea74d2a9fcf - NVIDIA-kernel-module-source-TempVersion/src/nvidia/src/kernel/core/locks_minimal.c
c0822891f614e6ec847acb971e68aad8847e0cd7 - NVIDIA-kernel-module-source-TempVersion/src/nvidia/src/kernel/core/locks_common.c
c68f2c96bfc6fce483a332a5824656d72986a145 - NVIDIA-kernel-module-source-TempVersion/src/nvidia/src/kernel/core/system.c
37000b419d23a8b052fc1218f09815fafb1d89c9 - NVIDIA-kernel-module-source-TempVersion/src/nvidia/src/kernel/core/hal_mgr.c
7b9c95f912b203c68b6ba1f62470dffee4b4efe3 - NVIDIA-kernel-module-source-TempVersion/src/nvidia/src/kernel/core/thread_state.c
677c655b0b8e86bdab13cdd4044de38647b00eec - NVIDIA-kernel-module-source-TempVersion/src/nvidia/src/kernel/core/hal/hal.c
8eac3ea49f9a53063f7106211e5236372d87bdaf - NVIDIA-kernel-module-source-TempVersion/src/nvidia/src/kernel/core/hal/info_block.c
b9eabee9140c62385d070628948af0dcda3b0b1a - NVIDIA-kernel-module-source-TempVersion/src/nvidia/src/kernel/core/hal/hals_all.c
003e3012e87b8f8f655749db88141d74660e8d8e - NVIDIA-kernel-module-source-TempVersion/src/nvidia/src/kernel/gpu_mgr/gpu_mgr.c
a5a31b9b62e6d19b934411995c315d4fdac71ca0 - NVIDIA-kernel-module-source-TempVersion/src/nvidia/src/kernel/gpu_mgr/gpu_db.c
37d1e3dd86e6409b8e461f90386e013194c9e4d1 - NVIDIA-kernel-module-source-TempVersion/src/nvidia/src/kernel/gpu_mgr/gpu_mgmt_api.c
ed24c0406c85dc27f0fca1bac8b0dcb7a60dca2d - NVIDIA-kernel-module-source-TempVersion/src/nvidia/src/kernel/gpu_mgr/gpu_group.c
6aa752ae480e883d077de842f02444151947f82f - NVIDIA-kernel-module-source-TempVersion/src/nvidia/src/kernel/mem_mgr/virt_mem_mgr.c
956b7871a267b7d381d1cd7d4689ef1aec1da415 - NVIDIA-kernel-module-source-TempVersion/src/nvidia/src/kernel/mem_mgr/mem.c
9d9fcd87d784a758659b6cc8a522eaf9beac4b6c - NVIDIA-kernel-module-source-TempVersion/src/nvidia/src/kernel/mem_mgr/standard_mem.c
15f3290908931a9e4d74b0c0ec9e460956e39089 - NVIDIA-kernel-module-source-TempVersion/src/nvidia/src/kernel/mem_mgr/system_mem.c
623dad3ec0172ed7b3818caece0db5687d587ff3 - NVIDIA-kernel-module-source-TempVersion/src/nvidia/src/kernel/mem_mgr/os_desc_mem.c
64bd2007101cbf718beb707898e85f40071ae405 - NVIDIA-kernel-module-source-TempVersion/src/nvidia/src/kernel/mem_mgr/syncpoint_mem.c
94acdcebee0cdcbf359b15803ec841e5284e1ff2 - NVIDIA-kernel-module-source-TempVersion/src/nvidia/src/kernel/mem_mgr/vaspace.c
079893039c2802e1b0e6fcab5d0ee0e4dc608c84 - NVIDIA-kernel-module-source-TempVersion/src/nvidia/src/kernel/mem_mgr/io_vaspace.c
5b9048e62581a3fbb0227d1a46c4ee8d8397bf5b - NVIDIA-kernel-module-source-TempVersion/src/nvidia/src/kernel/mem_mgr/mem_mgr_internal.h
78cbb6428372c25eba0ccf8c08e7d36d18e4bae8 - NVIDIA-kernel-module-source-TempVersion/src/nvidia/src/lib/base_utils.c
6d5915924b4e26a5e7592427e34b77596162d0fe - NVIDIA-kernel-module-source-TempVersion/src/nvidia/src/lib/zlib/inflate.c
cade0f7049cdb2ab423a073887ed20ba1abdb17e - NVIDIA-kernel-module-source-TempVersion/src/nvidia/src/libraries/utils/nvassert.c
8a4e2aec6fc01ce1133cfc7ef80b6363c5394208 - NVIDIA-kernel-module-source-TempVersion/src/nvidia/src/libraries/nvoc/src/runtime.c
8ed5171254e51e59fc5586e729793831165b8c0c - NVIDIA-kernel-module-source-TempVersion/src/nvidia/src/libraries/tls/tls.c
206dda159ecbc0340ac9329250302c76a504e5a8 - NVIDIA-kernel-module-source-TempVersion/src/nvidia/src/libraries/prereq_tracker/prereq_tracker.c
d48d51a880fced52ad6e323d984e872ccf9ef3bd - NVIDIA-kernel-module-source-TempVersion/src/nvidia/src/libraries/resserv/src/rs_client.c
d0ae6d7a363db3fdf54ae1a760630b52a2019637 - NVIDIA-kernel-module-source-TempVersion/src/nvidia/src/libraries/resserv/src/rs_resource.c
883ad1cf4ed1714eb74d44d3b9a41d6a4723b650 - NVIDIA-kernel-module-source-TempVersion/src/nvidia/src/libraries/resserv/src/rs_server.c
0c9581aa68a77cb9977a7fbcfd2077ccb618206e - NVIDIA-kernel-module-source-TempVersion/src/nvidia/src/libraries/resserv/src/rs_access_rights.c
dac54d97b38ad722198ec918668f175dc5122e4e - NVIDIA-kernel-module-source-TempVersion/src/nvidia/src/libraries/resserv/src/rs_access_map.c
1f2e9d09e658474b36d0b0ecd9380d0d2bcc86b2 - NVIDIA-kernel-module-source-TempVersion/src/nvidia/src/libraries/resserv/src/rs_domain.c
d3e5f13be70c8e458401ec9bdad007dfadedcc11 - NVIDIA-kernel-module-source-TempVersion/src/nvidia/src/libraries/nvbitvector/nvbitvector.c
836ba8b401fb6b6fcf4ccde1b644ebaefc3d8ee1 - NVIDIA-kernel-module-source-TempVersion/src/nvidia/src/libraries/ioaccess/ioaccess.c
9c40bfebe2c57b972683e45dc15f358aaa2280f8 - NVIDIA-kernel-module-source-TempVersion/src/nvidia/src/libraries/eventbuffer/eventbufferproducer.c
8f41e7127a65102f0035c03536c701b7ecdaa909 - NVIDIA-kernel-module-source-TempVersion/src/nvidia/src/libraries/nvport/string/string_generic.c
b528ef8e238dd2c22c6549057b54fe33039c6473 - NVIDIA-kernel-module-source-TempVersion/src/nvidia/src/libraries/nvport/memory/memory_tracking.c
b6d6074ca77856fc5fe4ff1534c08c023ee592a4 - NVIDIA-kernel-module-source-TempVersion/src/nvidia/src/libraries/nvport/memory/memory_unix_kernel_os.c
caff00b37e7f58fde886abcc2737c08526fa089e - NVIDIA-kernel-module-source-TempVersion/src/nvidia/src/libraries/nvport/memory/memory_generic.h
66e79047600e0a40c50e709c6c82402d9b205ad0 - NVIDIA-kernel-module-source-TempVersion/src/nvidia/src/libraries/nvport/crypto/crypto_random_xorshift.c
da86b765702196eb0011ac9d14873fbc1589d48b - NVIDIA-kernel-module-source-TempVersion/src/nvidia/src/libraries/nvport/thread/thread_unix_kernel_os.c
7cdc50ee31b9cde14c0ce6fcd390c5d4564e433d - NVIDIA-kernel-module-source-TempVersion/src/nvidia/src/libraries/nvport/cpu/cpu_common.c
a305654bafc883ad28a134a04e83bbd409e0fc06 - NVIDIA-kernel-module-source-TempVersion/src/nvidia/src/libraries/nvport/cpu/cpu_common.h
2fa76d2d5ba7212f826b656aa683223a470e484c - NVIDIA-kernel-module-source-TempVersion/src/nvidia/src/libraries/nvport/core/core.c
6f6c83e9ee6d91fc8700e5015440f2bc72e6600b - NVIDIA-kernel-module-source-TempVersion/src/nvidia/src/libraries/nvport/sync/sync_rwlock.c
9b69fbf3efea6ba58f9ba7cb0189c9264c994657 - NVIDIA-kernel-module-source-TempVersion/src/nvidia/src/libraries/nvport/sync/sync_common.h
b55b7b59f35d848d5a3b43d63da4d2f7b0af5d3e - NVIDIA-kernel-module-source-TempVersion/src/nvidia/src/libraries/nvport/sync/sync_unix_kernel_os.c
7416712aa964befcf8fede86e5a604871a2d00b8 - NVIDIA-kernel-module-source-TempVersion/src/nvidia/src/libraries/nvport/sync/inc/sync_rwlock_def.h
6dd0c5f2384610ea075642d8e403ddd8c8db371a - NVIDIA-kernel-module-source-TempVersion/src/nvidia/src/libraries/nvport/sync/inc/sync_unix_kernel_os_def.h
87ac95cf569bb550adb3577c6a6658d094c59999 - NVIDIA-kernel-module-source-TempVersion/src/nvidia/src/libraries/nvport/util/util_gcc_clang.c
a045a19d750d48387640ab659bb30f724c34b8c8 - NVIDIA-kernel-module-source-TempVersion/src/nvidia/src/libraries/nvport/util/util_unix_kernel_os.c
f0c486c1ad0f7d9516b13a02d52b4d857d8865b1 - NVIDIA-kernel-module-source-TempVersion/src/nvidia/src/libraries/nvport/util/util_compiler_switch.c
595a6238b9f04887dd418be43ff31f3e7ca6b121 - NVIDIA-kernel-module-source-TempVersion/src/nvidia/src/libraries/containers/map.c
4418c0344b64740050ff8ef6ee085f0687a323d4 - NVIDIA-kernel-module-source-TempVersion/src/nvidia/src/libraries/containers/list.c
057ad074f6252f7809a88f918986d7d5aacff568 - NVIDIA-kernel-module-source-TempVersion/src/nvidia/src/libraries/containers/queue.c
2389c9dd3b13fd2ff26d2d1342c515579079bc71 - NVIDIA-kernel-module-source-TempVersion/src/nvidia/src/libraries/containers/multimap.c
2975e5cecee2c1fd5f69a8ffc20a49016e83025c - NVIDIA-kernel-module-source-TempVersion/src/nvidia/src/libraries/containers/btree/btree.c
f0ce913eb568f85e6e1c1b8965f2cd2b98e81928 - NVIDIA-kernel-module-source-TempVersion/src/nvidia/src/libraries/containers/eheap/eheap_old.c
cba2c17804f6f2062dc5d75583e4a03e03016d1d - NVIDIA-kernel-module-source-TempVersion/src/nvidia/generated/g_disp_capabilities_nvoc.h
133e94f73c781709f407b03d8cdfdd8865c39b4b - NVIDIA-kernel-module-source-TempVersion/src/nvidia/generated/g_disp_sf_user_nvoc.c
801eb295d07258ad70b99cb0fe85f3421690e0c4 - NVIDIA-kernel-module-source-TempVersion/src/nvidia/generated/g_rmconfig_private.h
46c1a2066ead316ea69c60dc323bdb649bc11c0f - NVIDIA-kernel-module-source-TempVersion/src/nvidia/generated/g_binary_api_nvoc.c
f9bdef39159a8475626a0edcbc3a53505a0ff80a - NVIDIA-kernel-module-source-TempVersion/src/nvidia/generated/g_os_hal.h
958d9a2cddc91edfafb5c2f3d9622443ac49a6ef - NVIDIA-kernel-module-source-TempVersion/src/nvidia/generated/g_objtmr_nvoc.c
d405e01478d26ea99cc0012fa2d6e0021bbe6213 - NVIDIA-kernel-module-source-TempVersion/src/nvidia/generated/g_gpu_db_nvoc.c
182602832a033b3e2d5f88d4ba8febe63eeb2f9e - NVIDIA-kernel-module-source-TempVersion/src/nvidia/generated/g_client_resource_nvoc.c
376572489e0d4211663da22d5b0de7c7e740fb29 - NVIDIA-kernel-module-source-TempVersion/src/nvidia/generated/g_hal_mgr_nvoc.h
e3c4822ac998ab5c7946919c85011f6172dc35ee - NVIDIA-kernel-module-source-TempVersion/src/nvidia/generated/g_mem_nvoc.c
fa5e1c6001e60f77415d0a8f87c8b548b12e1217 - NVIDIA-kernel-module-source-TempVersion/src/nvidia/generated/g_mem_mgr_nvoc.c
ddc0ac4e1d8b8aef15e147f1f85f8df37c196763 - NVIDIA-kernel-module-source-TempVersion/src/nvidia/generated/g_hal_register.h
4fe5357eabd0c5e351fb965ceead308240f68eb1 - NVIDIA-kernel-module-source-TempVersion/src/nvidia/generated/g_objtmr_nvoc.h
4f4acfdefc7b9a0cdfe2d5840cc18c9c33366053 - NVIDIA-kernel-module-source-TempVersion/src/nvidia/generated/g_object_nvoc.h
1d66bab50a7d39faa2b0fec469a4512d2c7610d5 - NVIDIA-kernel-module-source-TempVersion/src/nvidia/generated/g_rmconfig_util.c
fbcbeb92e46ba11ac26c04c9688b3ffcf10f5c53 - NVIDIA-kernel-module-source-TempVersion/src/nvidia/generated/g_prereq_tracker_nvoc.h
e449382e19e4dcfcf0aec0babe5a1c8ce2f4249b - NVIDIA-kernel-module-source-TempVersion/src/nvidia/generated/g_kern_disp_nvoc.c
87a5ae8e07103074020ba052ca45ab39e918d3bd - NVIDIA-kernel-module-source-TempVersion/src/nvidia/generated/g_resource_nvoc.c
47b7744ddd01b821bf2fd25fdb25c8d6d55ee01d - NVIDIA-kernel-module-source-TempVersion/src/nvidia/generated/g_prereq_tracker_nvoc.c
c46cae4a17181c48bafc01237b83537df61c41ae - NVIDIA-kernel-module-source-TempVersion/src/nvidia/generated/g_hal_nvoc.c
f42bfa3b5a801358d30f852625d8456290550f46 - NVIDIA-kernel-module-source-TempVersion/src/nvidia/generated/g_disp_inst_mem_nvoc.h
59a87763c6abdc54828f2785a7d90e43e607bc87 - NVIDIA-kernel-module-source-TempVersion/src/nvidia/generated/g_disp_inst_mem_nvoc.c
da3cc08f12ccee23bcb1c0d0c757b8bbcb81e4fd - NVIDIA-kernel-module-source-TempVersion/src/nvidia/generated/g_rs_server_nvoc.h
6fd6953e4ae0af707376a40ea0e4f3e70872be7b - NVIDIA-kernel-module-source-TempVersion/src/nvidia/generated/g_os_desc_mem_nvoc.h
162777624d03af2f17dfdc28bc35143e2ec6cdee - NVIDIA-kernel-module-source-TempVersion/src/nvidia/generated/g_os_nvoc.c
b82e5db65ad41764f456d6f924c89d76c165e48d - NVIDIA-kernel-module-source-TempVersion/src/nvidia/generated/g_system_nvoc.h
63e9d0416d5ca1fdf547b5fba9ec76e54690c9dc - NVIDIA-kernel-module-source-TempVersion/src/nvidia/generated/g_ref_count_nvoc.h
b5ddae1e6960b13101aa38b2edc0610aed438ede - NVIDIA-kernel-module-source-TempVersion/src/nvidia/generated/g_gpu_nvoc.c
499a3d9c61a86b667cc77cf8653a71f7fe85078a - NVIDIA-kernel-module-source-TempVersion/src/nvidia/generated/g_nv_name_released.h
ac842d9de5eae74ef02b0a75259fb016b80c6eac - NVIDIA-kernel-module-source-TempVersion/src/nvidia/generated/g_disp_objs_nvoc.c
88d336f88c9b72ec2c1352d4ebe00c0831eafbca - NVIDIA-kernel-module-source-TempVersion/src/nvidia/generated/g_sdk-structures.h
fb78615cde6323784f51d33f2acd61fd4030fee0 - NVIDIA-kernel-module-source-TempVersion/src/nvidia/generated/g_device_nvoc.c
213ebb4fdfa3c2f64b5f998e2ad990e448d4a104 - NVIDIA-kernel-module-source-TempVersion/src/nvidia/generated/g_nv_debug_dump_nvoc.h
a6174ad345cfdf926cbb4c86c7e8eeadfccb0ddf - NVIDIA-kernel-module-source-TempVersion/src/nvidia/generated/g_gpu_class_list.c
fa785f8138598af783aefecf10b141d524e6bb42 - NVIDIA-kernel-module-source-TempVersion/src/nvidia/generated/g_virt_mem_mgr_nvoc.c
de97c5afdc34cb9aff23c3ba166e21f660cf1f47 - NVIDIA-kernel-module-source-TempVersion/src/nvidia/generated/g_hal.h
f9bdef39159a8475626a0edcbc3a53505a0ff80a - NVIDIA-kernel-module-source-TempVersion/src/nvidia/generated/g_os_private.h
53b2c39666e1da206d44d69d54009f20440503bc - NVIDIA-kernel-module-source-TempVersion/src/nvidia/generated/g_eng_state_nvoc.h
93f9738c0e8aa715592306ddf023adf6b548dcc4 - NVIDIA-kernel-module-source-TempVersion/src/nvidia/generated/g_nvh_state.h
2b49950ba8f540ed4231c3334810edbb212bb859 - NVIDIA-kernel-module-source-TempVersion/src/nvidia/generated/g_client_resource_nvoc.h
d614f90730e2ee78bc3aae47b4e7976500e166e7 - NVIDIA-kernel-module-source-TempVersion/src/nvidia/generated/g_io_vaspace_nvoc.h
4302502637f5c4146cb963801258444f2d8173e1 - NVIDIA-kernel-module-source-TempVersion/src/nvidia/generated/g_allclasses.h
7bb406aa863430507bdf07b5f3e519c0d756220a - NVIDIA-kernel-module-source-TempVersion/src/nvidia/generated/g_rs_resource_nvoc.c
6f3fc9676df77fa24c49140331b87ed5988ed57c - NVIDIA-kernel-module-source-TempVersion/src/nvidia/generated/rmconfig.h
cb02e66e5fc06aa340ab460c977961701e9ba295 - NVIDIA-kernel-module-source-TempVersion/src/nvidia/generated/g_subdevice_nvoc.c
079ac6d2a90bd2fc9413e092a729202dbc5f724a - NVIDIA-kernel-module-source-TempVersion/src/nvidia/generated/g_system_mem_nvoc.h
65d1ace1e68c9b39cce6db61aa8b86ee47a0ae4b - NVIDIA-kernel-module-source-TempVersion/src/nvidia/generated/g_gpu_halspec_nvoc.c
e0988b45cf712f1a7662b6f822eaed3ffd9938f3 - NVIDIA-kernel-module-source-TempVersion/src/nvidia/generated/g_gpu_mgmt_api_nvoc.h
40c937ca657bda9c0b67bd24c5047d39e596c16c - NVIDIA-kernel-module-source-TempVersion/src/nvidia/generated/g_disp_channel_nvoc.c
f8e842add67dc070cc011ea103fc56cfd81c8b9a - NVIDIA-kernel-module-source-TempVersion/src/nvidia/generated/g_chips2halspec_nvoc.c
3a5457a216d197af8f120c660690a55ee44bdd8e - NVIDIA-kernel-module-source-TempVersion/src/nvidia/generated/g_generic_engine_nvoc.c
21e3cf689d84b1a28e11f66cc68a0bc6713108b0 - NVIDIA-kernel-module-source-TempVersion/src/nvidia/generated/g_rs_server_nvoc.c
edead99d125425ddf8f2fa4e4261b8cc3bf566fc - NVIDIA-kernel-module-source-TempVersion/src/nvidia/generated/g_standard_mem_nvoc.c
b07c2c5e8df4de2bb9d242fd1606f1a57b8a742d - NVIDIA-kernel-module-source-TempVersion/src/nvidia/generated/g_io_vaspace_nvoc.c
bfabd5155af3172e1c0a5a0b66721ff830c7b68f - NVIDIA-kernel-module-source-TempVersion/src/nvidia/generated/g_hypervisor_nvoc.h
cc635daf3d7a9a176580951841b82e9eb0d6f5ad - NVIDIA-kernel-module-source-TempVersion/src/nvidia/generated/g_kernel_head_nvoc.c
757b3ecf94d0c8914a32c4bd302f8ccfa4027856 - NVIDIA-kernel-module-source-TempVersion/src/nvidia/generated/g_syncpoint_mem_nvoc.c
6263c1ceca0797d34a102f9846acd1fdef06fb60 - NVIDIA-kernel-module-source-TempVersion/src/nvidia/generated/g_resserv_nvoc.h
3b0e038829647cfe0d8807579db33416a420d1d2 - NVIDIA-kernel-module-source-TempVersion/src/nvidia/generated/g_chips2halspec.h
abda8536d885be1422810c184b936bbc880972eb - NVIDIA-kernel-module-source-TempVersion/src/nvidia/generated/g_os_desc_mem_nvoc.c
f6f40d568bcf2ae89547ad054f9b5357bac366ab - NVIDIA-kernel-module-source-TempVersion/src/nvidia/generated/g_event_nvoc.h
ceb4dd72148dfe4a0581631147e8d7636abfd61f - NVIDIA-kernel-module-source-TempVersion/src/nvidia/generated/g_chips2halspec_nvoc.h
41784541b2e9ee778b52e686288fe492c0276fec - NVIDIA-kernel-module-source-TempVersion/src/nvidia/generated/g_hal_mgr_nvoc.c
d32d0b65f5f76cb56ca7cd83c0adfe5cb5330924 - NVIDIA-kernel-module-source-TempVersion/src/nvidia/generated/g_resource_nvoc.h
d04adc777f547ae6d1369cf4c94963e5abf90b86 - NVIDIA-kernel-module-source-TempVersion/src/nvidia/generated/g_context_dma_nvoc.c
ac3965eea078f1998c3a3041f14212578682e599 - NVIDIA-kernel-module-source-TempVersion/src/nvidia/generated/g_vaspace_nvoc.c
0dae533422e24d91a29c82d7be619160bbb6f6be - NVIDIA-kernel-module-source-TempVersion/src/nvidia/generated/g_context_dma_nvoc.h
3f5a391895fc900396bae68761fe9b4dcb382ec0 - NVIDIA-kernel-module-source-TempVersion/src/nvidia/generated/g_event_buffer_nvoc.h
c3b4c6a1b90a1547e229bb2973eb19c01e1d0055 - NVIDIA-kernel-module-source-TempVersion/src/nvidia/generated/g_dce_client_nvoc.h
285af0d0517cb191387a05ad596f74291ec81737 - NVIDIA-kernel-module-source-TempVersion/src/nvidia/generated/g_mem_desc_nvoc.h
9646d1c4d472ad800c7c93eec15cc03dd9201073 - NVIDIA-kernel-module-source-TempVersion/src/nvidia/generated/g_disp_objs_nvoc.h
c370a103a4c1c9cf2df3763988e77ef8f7bc6afb - NVIDIA-kernel-module-source-TempVersion/src/nvidia/generated/g_gpu_db_nvoc.h
2239839c8a780a87e786439a49ab63e25d25001a - NVIDIA-kernel-module-source-TempVersion/src/nvidia/generated/g_rmconfig_util.h
09597f23d6a5440258656be81e7e6709390128f8 - NVIDIA-kernel-module-source-TempVersion/src/nvidia/generated/g_hal_private.h
8e0e60f6d30bbed679c43b4997875989314ee88c - NVIDIA-kernel-module-source-TempVersion/src/nvidia/generated/g_dce_client_nvoc.c
dec0f585ca46dc8e1aae49c8ea58db5a415de65c - NVIDIA-kernel-module-source-TempVersion/src/nvidia/generated/g_rpc-message-header.h
871fd0260ab9c164b8f6a7d1aba4563af622f1ac - NVIDIA-kernel-module-source-TempVersion/src/nvidia/generated/g_disp_channel_nvoc.h
205490d6651110f28009e752fa286f818bed22fb - NVIDIA-kernel-module-source-TempVersion/src/nvidia/generated/g_syncpoint_mem_nvoc.h
07a37ff685e68a703455e0ed7db7940697487ed2 - NVIDIA-kernel-module-source-TempVersion/src/nvidia/generated/g_system_nvoc.c
cc71518b4151dc2ee0592bbd2866d437043d0e1a - NVIDIA-kernel-module-source-TempVersion/src/nvidia/generated/g_kernel_head_nvoc.h
2c28d729456749f16ae03fb48b1e416706762805 - NVIDIA-kernel-module-source-TempVersion/src/nvidia/generated/g_resource_fwd_decls_nvoc.h
59c3612a596ad6b996c9d1506f9893bd1b5effee - NVIDIA-kernel-module-source-TempVersion/src/nvidia/generated/g_gpu_mgr_nvoc.c
81a6a28692f50efeebecad125de0585dd711ff36 - NVIDIA-kernel-module-source-TempVersion/src/nvidia/generated/g_device_nvoc.h
3f581df19314b273244c4c42ea915ec8ef0d8ce2 - NVIDIA-kernel-module-source-TempVersion/src/nvidia/generated/g_rs_client_nvoc.h
e839f8a5ebef5f28818bb5824bd7c52320db9a74 - NVIDIA-kernel-module-source-TempVersion/src/nvidia/generated/g_disp_sf_user_nvoc.h
e0b8f64c042dcbb6340552cb3517dabdeb490f1b - NVIDIA-kernel-module-source-TempVersion/src/nvidia/generated/g_hal_nvoc.h
7523c2ee9228ad0e2fb3566b23b9720d7896afae - NVIDIA-kernel-module-source-TempVersion/src/nvidia/generated/g_eng_state_nvoc.c
ad50b3dbe1685eefe51c4fc296f3eade70789dfb - NVIDIA-kernel-module-source-TempVersion/src/nvidia/generated/g_gpu_resource_nvoc.h
ca042cfcdfe8cc8a141f8bb5c9e6c05d8a71b707 - NVIDIA-kernel-module-source-TempVersion/src/nvidia/generated/g_hda_codec_api_nvoc.h
2ab6933e07a84c64dfcbeef3b3f4e3f14249d8c8 - NVIDIA-kernel-module-source-TempVersion/src/nvidia/generated/g_tmr_nvoc.h
ffd4f01212709e321d4097e424fe5d32038f5d8b - NVIDIA-kernel-module-source-TempVersion/src/nvidia/generated/g_gpu_mgmt_api_nvoc.c
12776c69191b583ffcf0914697cf41802f52ef01 - NVIDIA-kernel-module-source-TempVersion/src/nvidia/generated/g_hal_archimpl.h
05cb2fed8648f07b54dc2e8bacbafb323ea8262e - NVIDIA-kernel-module-source-TempVersion/src/nvidia/generated/g_standard_mem_nvoc.h
0b15dd4515c5e436a659883a48e62bf3c68bf439 - NVIDIA-kernel-module-source-TempVersion/src/nvidia/generated/g_gpu_nvoc.h
0269da77a8db8efde1debc8236f2b3de2cd2597e - NVIDIA-kernel-module-source-TempVersion/src/nvidia/generated/g_eng_desc_nvoc.h
1bdccdbabf5ae52fd65b829c35079bb7a8734939 - NVIDIA-kernel-module-source-TempVersion/src/nvidia/generated/g_tmr_nvoc.c
410a759c949904b7ae1eecafb31143fad579c0a1 - NVIDIA-kernel-module-source-TempVersion/src/nvidia/generated/g_rs_client_nvoc.c
73c598515eb7985c8f4cace0946ec9613960be6c - NVIDIA-kernel-module-source-TempVersion/src/nvidia/generated/g_gpu_group_nvoc.c
73a37ad59b9b13b61eb944748b6c2ba3cad7b630 - NVIDIA-kernel-module-source-TempVersion/src/nvidia/generated/g_traceable_nvoc.h
8915f69e67e1f3a809a5479e36280df06ce8dd90 - NVIDIA-kernel-module-source-TempVersion/src/nvidia/generated/g_system_mem_nvoc.c
d792fbb20b6ca5f2d62addf6a94b0c5027ae15fe - NVIDIA-kernel-module-source-TempVersion/src/nvidia/generated/g_subdevice_nvoc.h
6124890a54e529dff8b9d6ecf8f4bebe1e10a8a2 - NVIDIA-kernel-module-source-TempVersion/src/nvidia/generated/g_os_nvoc.h
cb03502bf603c88b709ec803b60efd1d6f8e5ee1 - NVIDIA-kernel-module-source-TempVersion/src/nvidia/generated/g_rpc-structures.h
b378d336af4d5cb4b1fb13b85042fad1fe02f4cc - NVIDIA-kernel-module-source-TempVersion/src/nvidia/generated/g_journal_nvoc.h
7c1b36cca9e8bf1fe18284685a6a80620df348cb - NVIDIA-kernel-module-source-TempVersion/src/nvidia/generated/g_client_nvoc.h
cd833a822c1ce96c79135ba7221d24f347ceadb1 - NVIDIA-kernel-module-source-TempVersion/src/nvidia/generated/g_mem_mgr_nvoc.h
a016a7d8e07389736c388cb973f3b2a177ea917d - NVIDIA-kernel-module-source-TempVersion/src/nvidia/generated/g_disp_capabilities_nvoc.c
42d784e8b478bbf48293a805aa227f0abdf1923b - NVIDIA-kernel-module-source-TempVersion/src/nvidia/generated/g_event_nvoc.c
b29061454e7d8daa0cef0787f12726d105faf5c4 - NVIDIA-kernel-module-source-TempVersion/src/nvidia/generated/g_gpu_resource_nvoc.c
4b9f2ee66b59181f226e1af5087db6ea80f1ee27 - NVIDIA-kernel-module-source-TempVersion/src/nvidia/generated/g_virt_mem_mgr_nvoc.h
23d16b4534103f24fac5bb86eb8bab40e5bcba57 - NVIDIA-kernel-module-source-TempVersion/src/nvidia/generated/g_hda_codec_api_nvoc.c
e48b8b6ba9da5630a7ade526acbb94e50d9b636d - NVIDIA-kernel-module-source-TempVersion/src/nvidia/generated/g_vaspace_nvoc.h
b86536778197748c707c3e9e4c73c5fbcb037e32 - NVIDIA-kernel-module-source-TempVersion/src/nvidia/generated/g_generic_engine_nvoc.h
07fd5f5534a6d751107f582ba187c7a53a139954 - NVIDIA-kernel-module-source-TempVersion/src/nvidia/generated/g_rs_resource_nvoc.h
f4a5684d5a877b90c7ae7b66436117c6feb65f91 - NVIDIA-kernel-module-source-TempVersion/src/nvidia/generated/g_gpu_mgr_nvoc.h
ab79a1418b65b9d65081456583169f516dd510c9 - NVIDIA-kernel-module-source-TempVersion/src/nvidia/generated/g_event_buffer_nvoc.c
bd048add5f0781d90b55a5293881a2f59ace3070 - NVIDIA-kernel-module-source-TempVersion/src/nvidia/generated/g_binary_api_nvoc.h
e50c91a674508b23b072e0dd2edbf743f24b333d - NVIDIA-kernel-module-source-TempVersion/src/nvidia/generated/g_object_nvoc.c
df070e15630a11b2f4b64d52228fa5a6e7ab2aa9 - NVIDIA-kernel-module-source-TempVersion/src/nvidia/generated/g_gpu_halspec_nvoc.h
0f3140b5eae77a6055f32a91cb13b026bbb23905 - NVIDIA-kernel-module-source-TempVersion/src/nvidia/generated/g_kern_disp_nvoc.h
76b1f545e3712a2f8e7c31b101acd9dd682c52f8 - NVIDIA-kernel-module-source-TempVersion/src/nvidia/generated/g_traceable_nvoc.c
14450b18d002d4e1786d4630ef4f1994c07ef188 - NVIDIA-kernel-module-source-TempVersion/src/nvidia/generated/g_odb.h
7b0201852361118f277ee7cc6dd16212c0192f71 - NVIDIA-kernel-module-source-TempVersion/src/nvidia/generated/g_gpu_group_nvoc.h
3d3385445934719abda1fefd4eb0762937be0e61 - NVIDIA-kernel-module-source-TempVersion/src/nvidia/generated/g_client_nvoc.c
c4fde03d5939b0eef108fde9c2f10661568f22a9 - NVIDIA-kernel-module-source-TempVersion/src/nvidia/generated/g_mem_nvoc.h
5fd1da24ae8263c43dc5dada4702564b6f0ca3d9 - NVIDIA-kernel-module-source-TempVersion/src/nvidia/inc/os/dce_rm_client_ipc.h
76b24227c65570898c19e16bf35b2cad143f3d05 - NVIDIA-kernel-module-source-TempVersion/src/nvidia/inc/kernel/gpu/gpu.h
61c7d3ac2dc61ee81abd743a6536a439592ee162 - NVIDIA-kernel-module-source-TempVersion/src/nvidia/inc/kernel/gpu/gpu_child_list.h
bf894a769c46d5d173e3875cd9667bb3fe82feb9 - NVIDIA-kernel-module-source-TempVersion/src/nvidia/inc/kernel/gpu/gpu_timeout.h
f17b704f2489ffedcc057d4a6da77c42ece42923 - NVIDIA-kernel-module-source-TempVersion/src/nvidia/inc/kernel/gpu/gpu_resource.h
0e8353854e837f0ef0fbf0d5ff5d7a25aa1eef7c - NVIDIA-kernel-module-source-TempVersion/src/nvidia/inc/kernel/gpu/eng_state.h
426c6ab6cecc3b1ba540b01309d1603301a86db1 - NVIDIA-kernel-module-source-TempVersion/src/nvidia/inc/kernel/gpu/eng_desc.h
c33ab6494c9423c327707fce2bcb771328984a3c - NVIDIA-kernel-module-source-TempVersion/src/nvidia/inc/kernel/gpu/gpu_halspec.h
6b27c9edf93f29a31787d9acaaefb2cefc31e7d4 - NVIDIA-kernel-module-source-TempVersion/src/nvidia/inc/kernel/gpu/gpu_device_mapping.h
1938fd2511213c8003864d879cf1c41ae1169a5f - NVIDIA-kernel-module-source-TempVersion/src/nvidia/inc/kernel/gpu/gpu_uuid.h
cf3d1427394c425c543e253adf443192ca613762 - NVIDIA-kernel-module-source-TempVersion/src/nvidia/inc/kernel/gpu/gpu_access.h
ce3302c1890e2f7990434f7335cb619b12dee854 - NVIDIA-kernel-module-source-TempVersion/src/nvidia/inc/kernel/gpu/gpu_resource_desc.h
97d0a067e89251672f191788abe81cf26dcb335f - NVIDIA-kernel-module-source-TempVersion/src/nvidia/inc/kernel/gpu/device/device.h
61711ed293ee6974a6ed9a8a3732ae5fedcdc666 - NVIDIA-kernel-module-source-TempVersion/src/nvidia/inc/kernel/gpu/disp/kern_disp_max.h
b39826404d84e0850aa3385691d8dde6e30d70d4 - NVIDIA-kernel-module-source-TempVersion/src/nvidia/inc/kernel/gpu/disp/disp_sf_user.h
51a209575d3e3fe8feb7269ece7df0846e18ca2a - NVIDIA-kernel-module-source-TempVersion/src/nvidia/inc/kernel/gpu/disp/kern_disp_type.h
277a2719f8c063037c6a9ed55ade2b1cb17f48ae - NVIDIA-kernel-module-source-TempVersion/src/nvidia/inc/kernel/gpu/disp/disp_capabilities.h
74bc902cd00b17da3a1dfa7fd3ebc058de439b76 - NVIDIA-kernel-module-source-TempVersion/src/nvidia/inc/kernel/gpu/disp/disp_channel.h
be7da8d1106ee14ff808d86abffb86794299b2df - NVIDIA-kernel-module-source-TempVersion/src/nvidia/inc/kernel/gpu/disp/disp_objs.h
576216219d27aa887beeccefc22bcead4d1234d7 - NVIDIA-kernel-module-source-TempVersion/src/nvidia/inc/kernel/gpu/disp/kern_disp.h
5179f01acf7e9e251552dc17c0dcd84f7d341d82 - NVIDIA-kernel-module-source-TempVersion/src/nvidia/inc/kernel/gpu/disp/inst_mem/disp_inst_mem.h
9a33a37c6cea9bad513aa14c942c689f28f7c0d8 - NVIDIA-kernel-module-source-TempVersion/src/nvidia/inc/kernel/gpu/disp/head/kernel_head.h
f758ea5f9cbd23a678290ef0b8d98d470e3499e0 - NVIDIA-kernel-module-source-TempVersion/src/nvidia/inc/kernel/gpu/disp/vblank_callback/vblank.h
6756126ddd616d6393037bebf371fceacaf3a9f1 - NVIDIA-kernel-module-source-TempVersion/src/nvidia/inc/kernel/gpu/mem_mgr/context_dma.h
20416f7239833dcaa743bbf988702610e9251289 - NVIDIA-kernel-module-source-TempVersion/src/nvidia/inc/kernel/gpu/mem_mgr/mem_mgr.h
a29f55d5fbc90dade83df3ef3263018633675284 - NVIDIA-kernel-module-source-TempVersion/src/nvidia/inc/kernel/gpu/mem_mgr/virt_mem_allocator_common.h
82abc2458910250c1a912e023f37e87c1c9bbb9e - NVIDIA-kernel-module-source-TempVersion/src/nvidia/inc/kernel/gpu/mem_mgr/heap_base.h
889ba18a43cc2b5c5e970a90ddcb770ce873b785 - NVIDIA-kernel-module-source-TempVersion/src/nvidia/inc/kernel/gpu/mem_mgr/mem_desc.h
b52e6a0499640e651aa4200b2c8a1653df04a420 - NVIDIA-kernel-module-source-TempVersion/src/nvidia/inc/kernel/gpu/mem_mgr/mem_utils.h
24d01769b39a6dd62574a95fad64443b05872151 - NVIDIA-kernel-module-source-TempVersion/src/nvidia/inc/kernel/gpu/subdevice/subdevice.h
efc50bb2ff6ccf1b7715fd413ca680034920758e - NVIDIA-kernel-module-source-TempVersion/src/nvidia/inc/kernel/gpu/subdevice/generic_engine.h
ccca322d29ae171ee81c95d58e31f1c109429ae7 - NVIDIA-kernel-module-source-TempVersion/src/nvidia/inc/kernel/gpu/gsp/message_queue.h
1e3bebe46b7f2f542eedace554a4156b3afb51f1 - NVIDIA-kernel-module-source-TempVersion/src/nvidia/inc/kernel/gpu/audio/hda_codec_api.h
ce4e0f7177f46f4fc507a68b635e5395a3f7dde6 - NVIDIA-kernel-module-source-TempVersion/src/nvidia/inc/kernel/gpu/dce_client/dce_client.h
5f60ac544252b894ac7ecc0c6dc4446e6275eae5 - NVIDIA-kernel-module-source-TempVersion/src/nvidia/inc/kernel/rmapi/rmapi.h
2baec15f4c68a9c59dd107a0db288e39914e6737 - NVIDIA-kernel-module-source-TempVersion/src/nvidia/inc/kernel/rmapi/client.h
a92dbf2870fe0df245ea8967f2f6a68f5075ecaf - NVIDIA-kernel-module-source-TempVersion/src/nvidia/inc/kernel/rmapi/resource_fwd_decls.h
61e3704cd51161c9804cb168d5ce4553b7311973 - NVIDIA-kernel-module-source-TempVersion/src/nvidia/inc/kernel/rmapi/resource.h
99a27d87c7f1487f8df5781d284c2e9a83525892 - NVIDIA-kernel-module-source-TempVersion/src/nvidia/inc/kernel/rmapi/binary_api.h
497492340cea19a93b62da69ca2000b811c8f5d6 - NVIDIA-kernel-module-source-TempVersion/src/nvidia/inc/kernel/rmapi/event_buffer.h
f3028fbcafe73212a94d295951122b532ff5445b - NVIDIA-kernel-module-source-TempVersion/src/nvidia/inc/kernel/rmapi/rs_utils.h
b4bae9ea958b4d014908459e08c93319784c47dd - NVIDIA-kernel-module-source-TempVersion/src/nvidia/inc/kernel/rmapi/event.h
ac9288d75555180c1d5dd6dd7e0e11fb57a967f2 - NVIDIA-kernel-module-source-TempVersion/src/nvidia/inc/kernel/rmapi/exports.h
2b23f2dbd8f3f63a17a1b63ebb40a2fd7fd8801a - NVIDIA-kernel-module-source-TempVersion/src/nvidia/inc/kernel/rmapi/alloc_size.h
c9cb08c7c73c0bdd75a320640d16bf4b4defe873 - NVIDIA-kernel-module-source-TempVersion/src/nvidia/inc/kernel/rmapi/mapping_list.h
f19dad1746e639d866c700c2f871fcc0144f2e5e - NVIDIA-kernel-module-source-TempVersion/src/nvidia/inc/kernel/rmapi/control.h
f1713ecc0b3e58e46c346409dbf4630aa6f7f3ed - NVIDIA-kernel-module-source-TempVersion/src/nvidia/inc/kernel/rmapi/param_copy.h
255c28b9bd27098382bace05af3ad7f195d12895 - NVIDIA-kernel-module-source-TempVersion/src/nvidia/inc/kernel/rmapi/rmapi_utils.h
4453fe6463e3155063f2bdbf36f44697606a80a5 - NVIDIA-kernel-module-source-TempVersion/src/nvidia/inc/kernel/rmapi/client_resource.h
7615ac3a83d0ad23b2160ff8ad90bec9eb1f3c6c - NVIDIA-kernel-module-source-TempVersion/src/nvidia/inc/kernel/diagnostics/journal.h
b259f23312abe56d34a8f0da36ef549ef60ba5b0 - NVIDIA-kernel-module-source-TempVersion/src/nvidia/inc/kernel/diagnostics/nv_debug_dump.h
c6efd51b8b8447829a0867cd7fb7a5a5a2fb1e3d - NVIDIA-kernel-module-source-TempVersion/src/nvidia/inc/kernel/diagnostics/traceable.h
7e75b5d99376fba058b31996d49449f8fe62d3f0 - NVIDIA-kernel-module-source-TempVersion/src/nvidia/inc/kernel/diagnostics/profiler.h
fd780f85cb1cd0fd3914fa31d1bd4933437b791d - NVIDIA-kernel-module-source-TempVersion/src/nvidia/inc/kernel/diagnostics/tracer.h
3a28bf1692efb34d2161907c3781401951cc2d4f - NVIDIA-kernel-module-source-TempVersion/src/nvidia/inc/kernel/diagnostics/journal_structs.h
c8496199cd808ed4c79d8e149961e721ad96714e - NVIDIA-kernel-module-source-TempVersion/src/nvidia/inc/kernel/os/capability.h
e5b881419bc00d925eba9f8493f6b36cf3ce7ca7 - NVIDIA-kernel-module-source-TempVersion/src/nvidia/inc/kernel/os/os_stub.h
408c0340350b813c3cba17fd36171075e156df72 - NVIDIA-kernel-module-source-TempVersion/src/nvidia/inc/kernel/os/os.h
cda75171ca7d8bf920aab6d56ef9aadec16fd15d - NVIDIA-kernel-module-source-TempVersion/src/nvidia/inc/kernel/os/nv_memory_type.h
af25180a08db4d5d20afd09f948b15d8c4d2d738 - NVIDIA-kernel-module-source-TempVersion/src/nvidia/inc/kernel/os/os_fixed_mode_timings_props.h
457c02092adfc1587d6e3cd866e28c567acbc43a - NVIDIA-kernel-module-source-TempVersion/src/nvidia/inc/kernel/core/info_block.h
bffae4da6a1f9b7dc7c879587fd674b49b46dac1 - NVIDIA-kernel-module-source-TempVersion/src/nvidia/inc/kernel/core/core.h
cbfff1f06eecc99fb5a1c82d43397043058f02fc - NVIDIA-kernel-module-source-TempVersion/src/nvidia/inc/kernel/core/printf.h
f929d43974893cd155ab2f5f77606f0040fe3e39 - NVIDIA-kernel-module-source-TempVersion/src/nvidia/inc/kernel/core/locks.h
b5859c7862fb3eeb266f7213845885789801194a - NVIDIA-kernel-module-source-TempVersion/src/nvidia/inc/kernel/core/system.h
37f267155ddfc3db38f110dbb0397f0463d055ff - NVIDIA-kernel-module-source-TempVersion/src/nvidia/inc/kernel/core/strict.h
bdc4ab675c6f6c4bd77c3aaf08aa5c865b186802 - NVIDIA-kernel-module-source-TempVersion/src/nvidia/inc/kernel/core/hal.h
ed496ab6e8b64d3398f929146e908c5a453a03d9 - NVIDIA-kernel-module-source-TempVersion/src/nvidia/inc/kernel/core/prelude.h
b319914c97f9978488e8fb049d39c72ed64fd4d2 - NVIDIA-kernel-module-source-TempVersion/src/nvidia/inc/kernel/core/thread_state.h
b00302aec7e4f4e3b89a2f699f8b1f18fc17b1ba - NVIDIA-kernel-module-source-TempVersion/src/nvidia/inc/kernel/core/hal_mgr.h
8ef620afdf720259cead00d20fae73d31e59c2f7 - NVIDIA-kernel-module-source-TempVersion/src/nvidia/inc/kernel/virtualization/hypervisor/hypervisor.h
2c48d7335bdb0b7ea88b78216c0aeab2e11e00c1 - NVIDIA-kernel-module-source-TempVersion/src/nvidia/inc/kernel/gpu_mgr/gpu_mgmt_api.h
e188d9f2d042ffe029b96d8fbb16c79a0fc0fb01 - NVIDIA-kernel-module-source-TempVersion/src/nvidia/inc/kernel/gpu_mgr/gpu_db.h
ea32018e3464bb1ac792e39227badf482fa2dc67 - NVIDIA-kernel-module-source-TempVersion/src/nvidia/inc/kernel/gpu_mgr/gpu_group.h
5b151d0d97b83c9fb76b76c476947f9e15e774ad - NVIDIA-kernel-module-source-TempVersion/src/nvidia/inc/kernel/gpu_mgr/gpu_mgr.h
0ce5d6370c086d2944b2e8d31ff72a510d98dc8f - NVIDIA-kernel-module-source-TempVersion/src/nvidia/inc/kernel/mem_mgr/virt_mem_mgr.h
4c386104eaead66c66df11258c3f1182b46e96ee - NVIDIA-kernel-module-source-TempVersion/src/nvidia/inc/kernel/mem_mgr/syncpoint_mem.h
a5f49a031db4171228a27482d091283e84632ace - NVIDIA-kernel-module-source-TempVersion/src/nvidia/inc/kernel/mem_mgr/system_mem.h
d15991bc770c5ab41fe746995294c5213efa056b - NVIDIA-kernel-module-source-TempVersion/src/nvidia/inc/kernel/mem_mgr/io_vaspace.h
5ae08b2077506cbc41e40e1b3672e615ce9d910f - NVIDIA-kernel-module-source-TempVersion/src/nvidia/inc/kernel/mem_mgr/vaspace.h
02d6a37ef1bb057604cb98a905fa02429f200c96 - NVIDIA-kernel-module-source-TempVersion/src/nvidia/inc/kernel/mem_mgr/mem.h
1a08e83fd6f0a072d6887c60c529e29211bcd007 - NVIDIA-kernel-module-source-TempVersion/src/nvidia/inc/kernel/mem_mgr/os_desc_mem.h
2d4afabd63699feec3aea5e89601db009fc51a08 - NVIDIA-kernel-module-source-TempVersion/src/nvidia/inc/kernel/mem_mgr/standard_mem.h
5e9928552086947b10092792db4a8c4c57a84adf - NVIDIA-kernel-module-source-TempVersion/src/nvidia/inc/kernel/platform/acpi_common.h
2f05394872ffa95d700b7822489fa59f74ad5819 - NVIDIA-kernel-module-source-TempVersion/src/nvidia/inc/kernel/platform/sli/sli.h
fff3ebc8527b34f8c463daad4d20ee5e33321344 - NVIDIA-kernel-module-source-TempVersion/src/nvidia/inc/lib/ref_count.h
04dba2b7a6a360f3e855a7d6a7484ddcdfb90c19 - NVIDIA-kernel-module-source-TempVersion/src/nvidia/inc/lib/base_utils.h
f8d9eb5f6a6883de962b63b4b7de35c01b20182f - NVIDIA-kernel-module-source-TempVersion/src/nvidia/inc/lib/protobuf/prb.h
601edb7333b87349d791d430f1cac84fb6fbb919 - NVIDIA-kernel-module-source-TempVersion/src/nvidia/inc/lib/zlib/inflate.h
9255fff39d7422ca4a56ba5ab60866779201d3e8 - NVIDIA-kernel-module-source-TempVersion/src/nvidia/inc/libraries/poolalloc.h
8dd7f2d9956278ed036bbc288bff4dde86a9b509 - NVIDIA-kernel-module-source-TempVersion/src/nvidia/inc/libraries/eventbufferproducer.h
e53d5fc9b66dbec4c947224050866cec30b2f537 - NVIDIA-kernel-module-source-TempVersion/src/nvidia/inc/libraries/utils/nvrange.h
398e4cd63852a18da6e42b920eacd927a2c38bc0 - NVIDIA-kernel-module-source-TempVersion/src/nvidia/inc/libraries/utils/nv_enum.h
ba3c81e9eae32eefbf81818b48fdf6ccd7e73163 - NVIDIA-kernel-module-source-TempVersion/src/nvidia/inc/libraries/utils/nvmacro.h
18321894aa7631b491ea39edc2d45d1028cdc9c6 - NVIDIA-kernel-module-source-TempVersion/src/nvidia/inc/libraries/utils/nvprintf.h
167f49cccc912430bb6b3cb77395f665a32cc8be - NVIDIA-kernel-module-source-TempVersion/src/nvidia/inc/libraries/utils/nvbitvector.h
1ed5d8ae82f37112b163187fa48d2720957e6bdf - NVIDIA-kernel-module-source-TempVersion/src/nvidia/inc/libraries/utils/nvassert.h
62a18f19f79512ebccdf286068e0b557c7926e13 - NVIDIA-kernel-module-source-TempVersion/src/nvidia/inc/libraries/nvoc/runtime.h
00433b51c4d6254fd4dfc3dcd9b4ad59e485e7c0 - NVIDIA-kernel-module-source-TempVersion/src/nvidia/inc/libraries/nvoc/object.h
1b28bd0ee2e560ca2854a73a3ee5fb1cf713d013 - NVIDIA-kernel-module-source-TempVersion/src/nvidia/inc/libraries/nvoc/utility.h
5cadc87ba685991c7d4c6d453dcc9a2cca4398bf - NVIDIA-kernel-module-source-TempVersion/src/nvidia/inc/libraries/nvoc/prelude.h
664ff0e10e893923b70425fa49c9c48ed0735573 - NVIDIA-kernel-module-source-TempVersion/src/nvidia/inc/libraries/nvoc/rtti.h
bdb558ee8f782e6be06fc262820f6bd9ce75bd51 - NVIDIA-kernel-module-source-TempVersion/src/nvidia/inc/libraries/tls/tls.h
56b8bae7756ed36d0831f76f95033f74eaab01db - NVIDIA-kernel-module-source-TempVersion/src/nvidia/inc/libraries/prereq_tracker/prereq_tracker.h
7239704e6fe88b9d75984fb5e9f4b5706502d7f3 - NVIDIA-kernel-module-source-TempVersion/src/nvidia/inc/libraries/nvlog/nvlog_printf.h
e08146f5de1596f5337c49cfbe180e30e880dedb - NVIDIA-kernel-module-source-TempVersion/src/nvidia/inc/libraries/nvlog/nvlog.h
d2c035e67e295b8f33f0fc52d9c30e43c5d7c2ba - NVIDIA-kernel-module-source-TempVersion/src/nvidia/inc/libraries/nvlog/internal/nvlog_printf_internal.h
cd033fe116a41285a979e629a2ee7b11ec99369f - NVIDIA-kernel-module-source-TempVersion/src/nvidia/inc/libraries/resserv/rs_access_rights.h
2dec1c73507f66736674d203cc4a00813ccb11bc - NVIDIA-kernel-module-source-TempVersion/src/nvidia/inc/libraries/resserv/rs_domain.h
a0d3d164eb92280353cdc4458d2561aae8a68c1d - NVIDIA-kernel-module-source-TempVersion/src/nvidia/inc/libraries/resserv/rs_server.h
89ece4711626bf1e4197c69bd5754e2798214d76 - NVIDIA-kernel-module-source-TempVersion/src/nvidia/inc/libraries/resserv/resserv.h
bacdb2c1a1dbf182a0a3be15efa0a5f83365118f - NVIDIA-kernel-module-source-TempVersion/src/nvidia/inc/libraries/resserv/rs_resource.h
df174d6b4f718ef699ca6f38c16aaeffa111ad3c - NVIDIA-kernel-module-source-TempVersion/src/nvidia/inc/libraries/resserv/rs_access_map.h
841ddca998b570feb1d59b50d644c8f2b59ae8e9 - NVIDIA-kernel-module-source-TempVersion/src/nvidia/inc/libraries/resserv/rs_client.h
b795f5cb77ecd2cc407102900b63977cfb34bbfd - NVIDIA-kernel-module-source-TempVersion/src/nvidia/inc/libraries/ioaccess/ioaccess.h
3dcee4e110f4c571e7f49fae2f2d0630d008a906 - NVIDIA-kernel-module-source-TempVersion/src/nvidia/inc/libraries/nvport/nvport.h
46345715dde843be2890b33f191b2f3b69385e0d - NVIDIA-kernel-module-source-TempVersion/src/nvidia/inc/libraries/nvport/memory.h
a1d93b6ec8ff01a3c2651e772a826ee11a7781d7 - NVIDIA-kernel-module-source-TempVersion/src/nvidia/inc/libraries/nvport/util.h
b93c2532babf176f7b91735682e7d7cdc41f96f8 - NVIDIA-kernel-module-source-TempVersion/src/nvidia/inc/libraries/nvport/debug.h
147d47ef4bd860394d1d8ae82c68d97887e2898b - NVIDIA-kernel-module-source-TempVersion/src/nvidia/inc/libraries/nvport/core.h
6d698ca4fc5e48c525f214a57e1de0cc4aa9e36b - NVIDIA-kernel-module-source-TempVersion/src/nvidia/inc/libraries/nvport/thread.h
3e656d5ed1f5df898ec444921ce77a40ead66b28 - NVIDIA-kernel-module-source-TempVersion/src/nvidia/inc/libraries/nvport/atomic.h
3ac7ddf3d402f3fd20cffe9d4e93f457de319605 - NVIDIA-kernel-module-source-TempVersion/src/nvidia/inc/libraries/nvport/sync.h
2487ffc1eb1e50b27ba07e0581da543d80bdaa72 - NVIDIA-kernel-module-source-TempVersion/src/nvidia/inc/libraries/nvport/safe.h
22420ad669a9809602f111385b7840556e58ecff - NVIDIA-kernel-module-source-TempVersion/src/nvidia/inc/libraries/nvport/cpu.h
6ad1beaa2783a57330240d47b373930cd36ca5d0 - NVIDIA-kernel-module-source-TempVersion/src/nvidia/inc/libraries/nvport/crypto.h
2805fad632acad045044e0b8417de88032177300 - NVIDIA-kernel-module-source-TempVersion/src/nvidia/inc/libraries/nvport/string.h
23afbd04f4e4b3301edcfdec003c8e936d898e38 - NVIDIA-kernel-module-source-TempVersion/src/nvidia/inc/libraries/nvport/inline/debug_unix_kernel_os.h
eedda5c4b0611c3b95f726b0a2db4b0a23b7b1cf - NVIDIA-kernel-module-source-TempVersion/src/nvidia/inc/libraries/nvport/inline/atomic_gcc.h
a8c9b83169aceb5f97d9f7a411db449496dc18f6 - NVIDIA-kernel-module-source-TempVersion/src/nvidia/inc/libraries/nvport/inline/util_generic.h
aafca30178f49676f640be9c6d34f623a3e3a9a4 - NVIDIA-kernel-module-source-TempVersion/src/nvidia/inc/libraries/nvport/inline/safe_generic.h
600ad8781585e87df49ab1aaa39a07c8e8de74f5 - NVIDIA-kernel-module-source-TempVersion/src/nvidia/inc/libraries/nvport/inline/util_gcc_clang.h
0747ee16c7e6c726f568867d0fbbad411c8795c8 - NVIDIA-kernel-module-source-TempVersion/src/nvidia/inc/libraries/nvport/inline/sync_tracking.h
2a76929dc6b0e8624d02002600bc454cc851dee4 - NVIDIA-kernel-module-source-TempVersion/src/nvidia/inc/libraries/nvport/inline/atomic_clang.h
1d6a239ed6c8dab1397f056a81ff456141ec7f9c - NVIDIA-kernel-module-source-TempVersion/src/nvidia/inc/libraries/nvport/inline/util_valist.h
31f2042e852f074970644903335af5ffa2b59c38 - NVIDIA-kernel-module-source-TempVersion/src/nvidia/inc/libraries/nvport/inline/memory_tracking.h
65a237b66732aafe39bc4a14d87debd2b094fb83 - NVIDIA-kernel-module-source-TempVersion/src/nvidia/inc/libraries/containers/map.h
c9e75f7b02241ededa5328a4f559e70dec60d159 - NVIDIA-kernel-module-source-TempVersion/src/nvidia/inc/libraries/containers/type_safety.h
3924b67e6d63e9a15876331c695daaf679454b05 - NVIDIA-kernel-module-source-TempVersion/src/nvidia/inc/libraries/containers/list.h
a28ab42de95e4878fb46e19d7b965c23f92b3213 - NVIDIA-kernel-module-source-TempVersion/src/nvidia/inc/libraries/containers/btree.h
4cd6b110470da3aee29e999e096ca582104fab21 - NVIDIA-kernel-module-source-TempVersion/src/nvidia/inc/libraries/containers/queue.h
1dacc1c1efc757c12e4c64eac171474a798b86fd - NVIDIA-kernel-module-source-TempVersion/src/nvidia/inc/libraries/containers/eheap_old.h
969cbac56935a80fafd7cceff157b27e623f9429 - NVIDIA-kernel-module-source-TempVersion/src/nvidia/inc/libraries/containers/multimap.h

Change-Id: I0561bddf423eb47180bdf85ccb3d24cafebfb44d

NVIDIA-kernel-module-source-TempVersion/kernel-open/nvidia-drm/nv-pci-table.c

@@ -0,0 +1,79 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2015 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#include <linux/kernel.h>
+#include <linux/module.h>
+
+#include "nv-pci-table.h"
+
+/* Devices supported by RM */
+struct pci_device_id nv_pci_table[] = {
+    {
+        .vendor      = PCI_VENDOR_ID_NVIDIA,
+        .device      = PCI_ANY_ID,
+        .subvendor   = PCI_ANY_ID,
+        .subdevice   = PCI_ANY_ID,
+        .class       = (PCI_CLASS_DISPLAY_VGA << 8),
+        .class_mask  = ~0
+    },
+    {
+        .vendor      = PCI_VENDOR_ID_NVIDIA,
+        .device      = PCI_ANY_ID,
+        .subvendor   = PCI_ANY_ID,
+        .subdevice   = PCI_ANY_ID,
+        .class       = (PCI_CLASS_DISPLAY_3D << 8),
+        .class_mask  = ~0
+    },
+    { }
+};
+
+/* Devices supported by all drivers in nvidia.ko */
+struct pci_device_id nv_module_device_table[] = {
+    {
+        .vendor      = PCI_VENDOR_ID_NVIDIA,
+        .device      = PCI_ANY_ID,
+        .subvendor   = PCI_ANY_ID,
+        .subdevice   = PCI_ANY_ID,
+        .class       = (PCI_CLASS_DISPLAY_VGA << 8),
+        .class_mask  = ~0
+    },
+    {
+        .vendor      = PCI_VENDOR_ID_NVIDIA,
+        .device      = PCI_ANY_ID,
+        .subvendor   = PCI_ANY_ID,
+        .subdevice   = PCI_ANY_ID,
+        .class       = (PCI_CLASS_DISPLAY_3D << 8),
+        .class_mask  = ~0
+    },
+    {
+        .vendor      = PCI_VENDOR_ID_NVIDIA,
+        .device      = PCI_ANY_ID,
+        .subvendor   = PCI_ANY_ID,
+        .subdevice   = PCI_ANY_ID,
+        .class       = (PCI_CLASS_BRIDGE_OTHER << 8),
+        .class_mask  = ~0
+    },
+    { }
+};
+
+MODULE_DEVICE_TABLE(pci, nv_module_device_table);

NVIDIA-kernel-module-source-TempVersion/kernel-open/nvidia-drm/nv-pci-table.h

@@ -0,0 +1,31 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2015 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef _NV_PCI_TABLE_H_
+#define _NV_PCI_TABLE_H_
+
+#include <linux/pci.h>
+
+extern struct pci_device_id nv_pci_table[];
+
+#endif /* _NV_PCI_TABLE_H_ */

NVIDIA-kernel-module-source-TempVersion/kernel-open/nvidia-drm/nvidia-dma-fence-helper.h

@@ -0,0 +1,121 @@
+/*
+ * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef __NVIDIA_DMA_FENCE_HELPER_H__
+#define __NVIDIA_DMA_FENCE_HELPER_H__
+
+#include "nvidia-drm-conftest.h"
+
+#if defined(NV_DRM_FENCE_AVAILABLE)
+
+/*
+ * Fence headers are moved to file dma-fence.h and struct fence has
+ * been renamed to dma_fence by commit -
+ *
+ *      2016-10-25 : f54d1867005c3323f5d8ad83eed823e84226c429
+ */
+
+#if defined(NV_LINUX_FENCE_H_PRESENT)
+#include <linux/fence.h>
+#else
+#include <linux/dma-fence.h>
+#endif
+
+#if defined(NV_LINUX_FENCE_H_PRESENT)
+typedef struct fence nv_dma_fence_t;
+typedef struct fence_ops nv_dma_fence_ops_t;
+#else
+typedef struct dma_fence nv_dma_fence_t;
+typedef struct dma_fence_ops nv_dma_fence_ops_t;
+#endif
+
+#if defined(NV_LINUX_FENCE_H_PRESENT)
+#define NV_DMA_FENCE_FLAG_ENABLE_SIGNAL_BIT FENCE_FLAG_ENABLE_SIGNAL_BIT
+#else
+#define NV_DMA_FENCE_FLAG_ENABLE_SIGNAL_BIT DMA_FENCE_FLAG_ENABLE_SIGNAL_BIT
+#endif
+
+static inline bool nv_dma_fence_is_signaled(nv_dma_fence_t *fence) {
+#if defined(NV_LINUX_FENCE_H_PRESENT)
+    return fence_is_signaled(fence);
+#else
+    return dma_fence_is_signaled(fence);
+#endif
+}
+
+static inline nv_dma_fence_t *nv_dma_fence_get(nv_dma_fence_t *fence)
+{
+#if defined(NV_LINUX_FENCE_H_PRESENT)
+    return fence_get(fence);
+#else
+    return dma_fence_get(fence);
+#endif
+}
+
+static inline void nv_dma_fence_put(nv_dma_fence_t *fence) {
+#if defined(NV_LINUX_FENCE_H_PRESENT)
+    fence_put(fence);
+#else
+    dma_fence_put(fence);
+#endif
+}
+
+static inline signed long
+nv_dma_fence_default_wait(nv_dma_fence_t *fence,
+                          bool intr, signed long timeout) {
+#if defined(NV_LINUX_FENCE_H_PRESENT)
+    return fence_default_wait(fence, intr, timeout);
+#else
+    return dma_fence_default_wait(fence, intr, timeout);
+#endif
+}
+
+static inline int nv_dma_fence_signal(nv_dma_fence_t *fence) {
+#if defined(NV_LINUX_FENCE_H_PRESENT)
+    return fence_signal(fence);
+#else
+    return dma_fence_signal(fence);
+#endif
+}
+
+static inline u64 nv_dma_fence_context_alloc(unsigned num) {
+#if defined(NV_LINUX_FENCE_H_PRESENT)
+    return fence_context_alloc(num);
+#else
+    return dma_fence_context_alloc(num);
+#endif
+}
+
+static inline void
+nv_dma_fence_init(nv_dma_fence_t *fence,
+                  const nv_dma_fence_ops_t *ops,
+                  spinlock_t *lock, u64 context, unsigned seqno) {
+#if defined(NV_LINUX_FENCE_H_PRESENT)
+    fence_init(fence, ops, lock, context, seqno);
+#else
+    dma_fence_init(fence, ops, lock, context, seqno);
+#endif
+}
+
+#endif /* defined(NV_DRM_FENCE_AVAILABLE) */
+
+#endif /* __NVIDIA_DMA_FENCE_HELPER_H__ */

NVIDIA-kernel-module-source-TempVersion/kernel-open/nvidia-drm/nvidia-dma-resv-helper.h

@@ -0,0 +1,126 @@
+/*
+ * Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef __NVIDIA_DMA_RESV_HELPER_H__
+#define __NVIDIA_DMA_RESV_HELPER_H__
+
+#include "nvidia-drm-conftest.h"
+
+#if defined(NV_DRM_FENCE_AVAILABLE)
+
+/*
+ * linux/reservation.h is renamed to linux/dma-resv.h, by commit
+ * 52791eeec1d9 (dma-buf: rename reservation_object to dma_resv)
+ * in v5.4.
+ */
+
+#if defined(NV_LINUX_DMA_RESV_H_PRESENT)
+#include <linux/dma-resv.h>
+#else
+#include <linux/reservation.h>
+#endif
+
+#include <nvidia-dma-fence-helper.h>
+
+#if defined(NV_LINUX_DMA_RESV_H_PRESENT)
+typedef struct dma_resv nv_dma_resv_t;
+#else
+typedef struct reservation_object nv_dma_resv_t;
+#endif
+
+static inline void nv_dma_resv_init(nv_dma_resv_t *obj)
+{
+#if defined(NV_LINUX_DMA_RESV_H_PRESENT)
+    dma_resv_init(obj);
+#else
+    reservation_object_init(obj);
+#endif
+}
+
+static inline void nv_dma_resv_fini(nv_dma_resv_t *obj)
+{
+#if defined(NV_LINUX_DMA_RESV_H_PRESENT)
+    dma_resv_fini(obj);
+#else
+    reservation_object_init(obj);
+#endif
+}
+
+static inline void nv_dma_resv_lock(nv_dma_resv_t *obj,
+                                    struct ww_acquire_ctx *ctx)
+{
+#if defined(NV_LINUX_DMA_RESV_H_PRESENT)
+    dma_resv_lock(obj, ctx);
+#else
+    ww_mutex_lock(&obj->lock, ctx);
+#endif
+}
+
+static inline void nv_dma_resv_unlock(nv_dma_resv_t *obj)
+{
+#if defined(NV_LINUX_DMA_RESV_H_PRESENT)
+    dma_resv_unlock(obj);
+#else
+    ww_mutex_unlock(&obj->lock);
+#endif
+}
+
+static inline int nv_dma_resv_reserve_fences(nv_dma_resv_t *obj,
+                                             unsigned int num_fences,
+                                             NvBool shared)
+{
+#if defined(NV_DMA_RESV_RESERVE_FENCES_PRESENT)
+    return dma_resv_reserve_fences(obj, num_fences);
+#else
+    if (shared) {
+#if defined(NV_LINUX_DMA_RESV_H_PRESENT)
+        return dma_resv_reserve_shared(obj, num_fences);
+#elif defined(NV_RESERVATION_OBJECT_RESERVE_SHARED_HAS_NUM_FENCES_ARG)
+        return reservation_object_reserve_shared(obj, num_fences);
+#else
+        unsigned int i;
+        for (i = 0; i < num_fences; i++) {
+            reservation_object_reserve_shared(obj);
+        }
+#endif
+    }
+    return 0;
+#endif
+}
+
+static inline void nv_dma_resv_add_excl_fence(nv_dma_resv_t *obj,
+                                              nv_dma_fence_t *fence)
+{
+#if defined(NV_LINUX_DMA_RESV_H_PRESENT)
+#if defined(NV_DMA_RESV_ADD_FENCE_PRESENT)
+    dma_resv_add_fence(obj, fence, DMA_RESV_USAGE_WRITE);
+#else
+    dma_resv_add_excl_fence(obj, fence);
+#endif
+#else
+    reservation_object_add_excl_fence(obj, fence);
+#endif
+}
+
+#endif /* defined(NV_DRM_FENCE_AVAILABLE) */
+
+#endif /* __NVIDIA_DMA_RESV_HELPER_H__ */

NVIDIA-kernel-module-source-TempVersion/kernel-open/nvidia-drm/nvidia-drm-conftest.h

@@ -0,0 +1,64 @@
+/*
+ * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef __NVIDIA_DRM_CONFTEST_H__
+#define __NVIDIA_DRM_CONFTEST_H__
+
+#include "conftest.h"
+
+/*
+ * NOTE: This file is expected to get included at the top before including any
+ * of linux/drm headers.
+ *
+ * The goal is to redefine refcount_dec_and_test and refcount_inc before
+ * including drm header files, so that the drm macro/inline calls to
+ * refcount_dec_and_test* and refcount_inc get redirected to
+ * alternate implementation in this file.
+ */
+
+#if NV_IS_EXPORT_SYMBOL_GPL_refcount_inc
+
+#include <linux/refcount.h>
+
+#define refcount_inc(__ptr)         \
+    do {                            \
+        atomic_inc(&(__ptr)->refs); \
+    } while(0)
+
+#endif
+
+#if NV_IS_EXPORT_SYMBOL_GPL_refcount_dec_and_test
+
+#include <linux/refcount.h>
+
+#define refcount_dec_and_test(__ptr) atomic_dec_and_test(&(__ptr)->refs)
+
+#endif
+
+#if defined(NV_DRM_DRIVER_HAS_GEM_PRIME_RES_OBJ) || \
+    defined(NV_DRM_GEM_OBJECT_HAS_RESV)
+#define NV_DRM_FENCE_AVAILABLE
+#else
+#undef NV_DRM_FENCE_AVAILABLE
+#endif
+
+#endif /* defined(__NVIDIA_DRM_CONFTEST_H__) */

NVIDIA-kernel-module-source-TempVersion/kernel-open/nvidia-drm/nvidia-drm-connector.c

@@ -0,0 +1,472 @@
+/*
+ * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#include "nvidia-drm-conftest.h" /* NV_DRM_ATOMIC_MODESET_AVAILABLE */
+
+#if defined(NV_DRM_ATOMIC_MODESET_AVAILABLE)
+
+#include "nvidia-drm-helper.h"
+#include "nvidia-drm-priv.h"
+#include "nvidia-drm-connector.h"
+#include "nvidia-drm-utils.h"
+#include "nvidia-drm-encoder.h"
+
+/*
+ * Commit fcd70cd36b9b ("drm: Split out drm_probe_helper.h")
+ * moves a number of helper function definitions from
+ * drm/drm_crtc_helper.h to a new drm_probe_helper.h.
+ */
+#if defined(NV_DRM_DRM_PROBE_HELPER_H_PRESENT)
+#include <drm/drm_probe_helper.h>
+#endif
+#include <drm/drm_crtc_helper.h>
+
+#include <drm/drm_atomic.h>
+#include <drm/drm_atomic_helper.h>
+#include <drm/drm_edid.h>
+
+static void nv_drm_connector_destroy(struct drm_connector *connector)
+{
+    struct nv_drm_connector *nv_connector = to_nv_connector(connector);
+
+    drm_connector_unregister(connector);
+
+    drm_connector_cleanup(connector);
+
+    if (nv_connector->edid != NULL) {
+        nv_drm_free(nv_connector->edid);
+    }
+
+    nv_drm_free(nv_connector);
+}
+
+static bool
+__nv_drm_detect_encoder(struct NvKmsKapiDynamicDisplayParams *pDetectParams,
+                        struct drm_connector *connector,
+                        struct drm_encoder *encoder)
+{
+    struct nv_drm_connector *nv_connector = to_nv_connector(connector);
+    struct drm_device *dev = connector->dev;
+    struct nv_drm_device *nv_dev = to_nv_device(dev);
+    struct nv_drm_encoder *nv_encoder;
+
+    /*
+     * DVI-I connectors can drive both digital and analog
+     * encoders.  If a digital connection has been forced then
+     * skip analog encoders.
+     */
+
+    if (connector->connector_type == DRM_MODE_CONNECTOR_DVII &&
+        connector->force == DRM_FORCE_ON_DIGITAL &&
+        encoder->encoder_type == DRM_MODE_ENCODER_DAC) {
+        return false;
+    }
+
+    nv_encoder = to_nv_encoder(encoder);
+
+    memset(pDetectParams, 0, sizeof(*pDetectParams));
+
+    pDetectParams->handle = nv_encoder->hDisplay;
+
+    switch (connector->force) {
+        case DRM_FORCE_ON:
+        case DRM_FORCE_ON_DIGITAL:
+            pDetectParams->forceConnected = NV_TRUE;
+            break;
+        case DRM_FORCE_OFF:
+            pDetectParams->forceDisconnected = NV_TRUE;
+            break;
+        case DRM_FORCE_UNSPECIFIED:
+            break;
+    }
+
+#if defined(NV_DRM_CONNECTOR_HAS_OVERRIDE_EDID)
+    if (connector->override_edid) {
+#else
+    if (drm_edid_override_connector_update(connector) > 0) {
+#endif
+        const struct drm_property_blob *edid = connector->edid_blob_ptr;
+
+        if (edid->length <= sizeof(pDetectParams->edid.buffer)) {
+            memcpy(pDetectParams->edid.buffer, edid->data, edid->length);
+            pDetectParams->edid.bufferSize = edid->length;
+            pDetectParams->overrideEdid = NV_TRUE;
+        } else {
+            WARN_ON(edid->length >
+                    sizeof(pDetectParams->edid.buffer));
+        }
+    }
+
+    if (!nvKms->getDynamicDisplayInfo(nv_dev->pDevice, pDetectParams)) {
+        NV_DRM_DEV_LOG_ERR(
+            nv_dev,
+            "Failed to detect display state");
+        return false;
+    }
+
+    if (pDetectParams->connected) {
+        if (!pDetectParams->overrideEdid && pDetectParams->edid.bufferSize) {
+
+            if ((nv_connector->edid = nv_drm_calloc(
+                        1,
+                        pDetectParams->edid.bufferSize)) != NULL) {
+
+                memcpy(nv_connector->edid,
+                       pDetectParams->edid.buffer,
+                       pDetectParams->edid.bufferSize);
+            } else {
+                NV_DRM_LOG_ERR("Out of Memory");
+            }
+        }
+
+        return true;
+    }
+
+    return false;
+}
+
+static enum drm_connector_status __nv_drm_connector_detect_internal(
+    struct drm_connector *connector)
+{
+    struct drm_device *dev = connector->dev;
+    struct nv_drm_connector *nv_connector = to_nv_connector(connector);
+
+    enum drm_connector_status status = connector_status_disconnected;
+
+    struct drm_encoder *detected_encoder = NULL;
+    struct nv_drm_encoder *nv_detected_encoder = NULL;
+    struct drm_encoder *encoder;
+
+    struct NvKmsKapiDynamicDisplayParams *pDetectParams = NULL;
+
+    BUG_ON(!mutex_is_locked(&dev->mode_config.mutex));
+
+    if (nv_connector->edid != NULL) {
+        nv_drm_free(nv_connector->edid);
+        nv_connector->edid = NULL;
+    }
+
+    if ((pDetectParams = nv_drm_calloc(
+                1,
+                sizeof(*pDetectParams))) == NULL) {
+        WARN_ON(pDetectParams == NULL);
+        goto done;
+    }
+
+    nv_drm_connector_for_each_possible_encoder(connector, encoder) {
+        if (__nv_drm_detect_encoder(pDetectParams, connector, encoder)) {
+            detected_encoder = encoder;
+            break;
+        }
+    } nv_drm_connector_for_each_possible_encoder_end;
+
+    if (detected_encoder == NULL) {
+        goto done;
+    }
+
+    nv_detected_encoder = to_nv_encoder(detected_encoder);
+
+    status = connector_status_connected;
+
+    nv_connector->nv_detected_encoder = nv_detected_encoder;
+
+    if (nv_connector->type == NVKMS_CONNECTOR_TYPE_DVI_I) {
+        drm_object_property_set_value(
+            &connector->base,
+            dev->mode_config.dvi_i_subconnector_property,
+            detected_encoder->encoder_type == DRM_MODE_ENCODER_DAC ?
+                DRM_MODE_SUBCONNECTOR_DVIA :
+                DRM_MODE_SUBCONNECTOR_DVID);
+    }
+
+done:
+
+    nv_drm_free(pDetectParams);
+
+    return status;
+}
+
+static void __nv_drm_connector_force(struct drm_connector *connector)
+{
+    __nv_drm_connector_detect_internal(connector);
+}
+
+static enum drm_connector_status
+nv_drm_connector_detect(struct drm_connector *connector, bool force)
+{
+    return __nv_drm_connector_detect_internal(connector);
+}
+
+static struct drm_connector_funcs nv_connector_funcs = {
+#if defined NV_DRM_ATOMIC_HELPER_CONNECTOR_DPMS_PRESENT
+    .dpms                   = drm_atomic_helper_connector_dpms,
+#endif
+    .destroy                = nv_drm_connector_destroy,
+    .reset                  = drm_atomic_helper_connector_reset,
+    .force                  = __nv_drm_connector_force,
+    .detect                 = nv_drm_connector_detect,
+    .fill_modes             = drm_helper_probe_single_connector_modes,
+    .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
+    .atomic_destroy_state   = drm_atomic_helper_connector_destroy_state,
+};
+
+static int nv_drm_connector_get_modes(struct drm_connector *connector)
+{
+    struct drm_device *dev = connector->dev;
+    struct nv_drm_device *nv_dev = to_nv_device(dev);
+    struct nv_drm_connector *nv_connector = to_nv_connector(connector);
+    struct nv_drm_encoder *nv_detected_encoder =
+                           nv_connector->nv_detected_encoder;
+    NvU32 modeIndex = 0;
+    int   count = 0;
+
+
+    if (nv_connector->edid != NULL) {
+        nv_drm_connector_update_edid_property(connector, nv_connector->edid);
+    }
+
+    while (1) {
+        struct drm_display_mode *mode;
+        struct NvKmsKapiDisplayMode displayMode;
+        NvBool valid = 0;
+        NvBool preferredMode = NV_FALSE;
+        int ret;
+
+        ret = nvKms->getDisplayMode(nv_dev->pDevice,
+                                    nv_detected_encoder->hDisplay,
+                                    modeIndex++, &displayMode, &valid,
+                                    &preferredMode);
+
+        if (ret < 0) {
+            NV_DRM_DEV_LOG_ERR(
+                nv_dev,
+                "Failed to get mode at modeIndex %d of NvKmsKapiDisplay 0x%08x",
+                modeIndex, nv_detected_encoder->hDisplay);
+            break;
+        }
+
+        /* Is end of mode-list */
+
+        if (ret == 0) {
+            break;
+        }
+
+        /* Ignore invalid modes */
+
+        if (!valid) {
+            continue;
+        }
+
+        mode = drm_mode_create(connector->dev);
+
+        if (mode == NULL) {
+            NV_DRM_DEV_LOG_ERR(
+                nv_dev,
+                "Failed to create mode for NvKmsKapiDisplay 0x%08x",
+                nv_detected_encoder->hDisplay);
+            continue;
+        }
+
+        nvkms_display_mode_to_drm_mode(&displayMode, mode);
+
+        if (preferredMode) {
+            mode->type |= DRM_MODE_TYPE_PREFERRED;
+        }
+
+        /* Add a mode to a connector's probed_mode list */
+
+        drm_mode_probed_add(connector, mode);
+
+        count++;
+    }
+
+    return count;
+}
+
+static int nv_drm_connector_mode_valid(struct drm_connector    *connector,
+                                       struct drm_display_mode *mode)
+{
+    struct drm_device *dev = connector->dev;
+    struct nv_drm_device *nv_dev = to_nv_device(dev);
+    struct nv_drm_encoder *nv_detected_encoder =
+                           to_nv_connector(connector)->nv_detected_encoder;
+    struct NvKmsKapiDisplayMode displayMode;
+
+    if (nv_detected_encoder == NULL) {
+        return MODE_BAD;
+    }
+
+    drm_mode_to_nvkms_display_mode(mode, &displayMode);
+
+    if (!nvKms->validateDisplayMode(nv_dev->pDevice,
+                                    nv_detected_encoder->hDisplay,
+                                    &displayMode)) {
+        return MODE_BAD;
+    }
+
+    return MODE_OK;
+}
+
+static struct drm_encoder*
+nv_drm_connector_best_encoder(struct drm_connector *connector)
+{
+    struct nv_drm_connector *nv_connector = to_nv_connector(connector);
+
+    if (nv_connector->nv_detected_encoder != NULL) {
+        return &nv_connector->nv_detected_encoder->base;
+    }
+
+    return NULL;
+}
+
+static const struct drm_connector_helper_funcs nv_connector_helper_funcs = {
+    .get_modes    = nv_drm_connector_get_modes,
+    .mode_valid   = nv_drm_connector_mode_valid,
+    .best_encoder = nv_drm_connector_best_encoder,
+};
+
+static struct drm_connector*
+nv_drm_connector_new(struct drm_device *dev,
+                     NvU32 physicalIndex, NvKmsConnectorType type,
+                     NvBool internal,
+                     char dpAddress[NVKMS_DP_ADDRESS_STRING_LENGTH])
+{
+    struct nv_drm_device *nv_dev = to_nv_device(dev);
+    struct nv_drm_connector *nv_connector = NULL;
+    int ret = -ENOMEM;
+
+    if ((nv_connector = nv_drm_calloc(1, sizeof(*nv_connector))) == NULL) {
+        goto failed;
+    }
+
+    if ((nv_connector->base.state =
+            nv_drm_calloc(1, sizeof(*nv_connector->base.state))) == NULL) {
+        goto failed_state_alloc;
+    }
+    nv_connector->base.state->connector = &nv_connector->base;
+
+    nv_connector->physicalIndex = physicalIndex;
+    nv_connector->type     = type;
+    nv_connector->internal = internal;
+
+    strcpy(nv_connector->dpAddress, dpAddress);
+
+    ret = drm_connector_init(
+        dev,
+        &nv_connector->base, &nv_connector_funcs,
+        nvkms_connector_type_to_drm_connector_type(type, internal));
+
+    if (ret != 0) {
+        NV_DRM_DEV_LOG_ERR(
+            nv_dev,
+            "Failed to initialize connector created from physical index %u",
+            nv_connector->physicalIndex);
+        goto failed_connector_init;
+    }
+
+    drm_connector_helper_add(&nv_connector->base, &nv_connector_helper_funcs);
+
+    nv_connector->base.polled = DRM_CONNECTOR_POLL_HPD;
+
+    if (nv_connector->type == NVKMS_CONNECTOR_TYPE_VGA) {
+        nv_connector->base.polled =
+            DRM_CONNECTOR_POLL_CONNECT | DRM_CONNECTOR_POLL_DISCONNECT;
+    }
+
+    /* Register connector with DRM subsystem */
+
+    ret = drm_connector_register(&nv_connector->base);
+
+    if (ret != 0) {
+        NV_DRM_DEV_LOG_ERR(
+            nv_dev,
+            "Failed to register connector created from physical index %u",
+            nv_connector->physicalIndex);
+        goto failed_connector_register;
+    }
+
+    return &nv_connector->base;
+
+failed_connector_register:
+    drm_connector_cleanup(&nv_connector->base);
+
+failed_connector_init:
+    nv_drm_free(nv_connector->base.state);
+
+failed_state_alloc:
+    nv_drm_free(nv_connector);
+
+failed:
+    return ERR_PTR(ret);
+}
+
+/*
+ * Get connector with given physical index one exists. Otherwise, create and
+ * return a new connector.
+ */
+struct drm_connector*
+nv_drm_get_connector(struct drm_device *dev,
+                     NvU32 physicalIndex, NvKmsConnectorType type,
+                     NvBool internal,
+                     char dpAddress[NVKMS_DP_ADDRESS_STRING_LENGTH])
+{
+    struct drm_connector *connector = NULL;
+#if defined(NV_DRM_CONNECTOR_LIST_ITER_PRESENT)
+    struct drm_connector_list_iter conn_iter;
+    nv_drm_connector_list_iter_begin(dev, &conn_iter);
+#else
+    struct drm_mode_config *config = &dev->mode_config;
+    mutex_lock(&config->mutex);
+#endif
+
+    /* Lookup for existing connector with same physical index */
+    nv_drm_for_each_connector(connector, &conn_iter, dev) {
+        struct nv_drm_connector *nv_connector = to_nv_connector(connector);
+
+        if (nv_connector->physicalIndex == physicalIndex) {
+            BUG_ON(nv_connector->type != type ||
+                   nv_connector->internal != internal);
+
+            if (strcmp(nv_connector->dpAddress, dpAddress) == 0) {
+                goto done;
+            }
+        }
+    }
+    connector = NULL;
+
+done:
+#if defined(NV_DRM_CONNECTOR_LIST_ITER_PRESENT)
+    nv_drm_connector_list_iter_end(&conn_iter);
+#else
+    mutex_unlock(&config->mutex);
+#endif
+
+    if (!connector) {
+        connector = nv_drm_connector_new(dev,
+                                         physicalIndex, type, internal,
+                                         dpAddress);
+    }
+
+    return connector;
+}
+
+#endif

NVIDIA-kernel-module-source-TempVersion/kernel-open/nvidia-drm/nvidia-drm-connector.h

@@ -0,0 +1,89 @@
+/*
+ * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef __NVIDIA_DRM_CONNECTOR_H__
+#define __NVIDIA_DRM_CONNECTOR_H__
+
+#include "nvidia-drm-conftest.h"
+
+#if defined(NV_DRM_ATOMIC_MODESET_AVAILABLE)
+
+#if defined(NV_DRM_DRMP_H_PRESENT)
+#include <drm/drmP.h>
+#endif
+
+#if defined(NV_DRM_DRM_CONNECTOR_H_PRESENT)
+#include <drm/drm_connector.h>
+#endif
+
+#include "nvtypes.h"
+#include "nvkms-api-types.h"
+
+struct nv_drm_connector {
+    NvU32 physicalIndex;
+
+    NvBool internal;
+    NvKmsConnectorType type;
+
+    char dpAddress[NVKMS_DP_ADDRESS_STRING_LENGTH];
+
+    struct nv_drm_encoder *nv_detected_encoder;
+    struct edid *edid;
+
+    atomic_t connection_status_dirty;
+
+    struct drm_connector base;
+};
+
+static inline struct nv_drm_connector *to_nv_connector(
+    struct drm_connector *connector)
+{
+    if (connector == NULL) {
+        return NULL;
+    }
+    return container_of(connector, struct nv_drm_connector, base);
+}
+
+static inline void nv_drm_connector_mark_connection_status_dirty(
+    struct nv_drm_connector *nv_connector)
+{
+    atomic_cmpxchg(&nv_connector->connection_status_dirty, false, true);
+}
+
+static inline bool nv_drm_connector_check_connection_status_dirty_and_clear(
+    struct nv_drm_connector *nv_connector)
+{
+    return atomic_cmpxchg(
+            &nv_connector->connection_status_dirty,
+            true,
+            false) == true;
+}
+
+struct drm_connector*
+nv_drm_get_connector(struct drm_device *dev,
+                     NvU32 physicalIndex, NvKmsConnectorType type,
+                     NvBool internal,
+                     char dpAddress[NVKMS_DP_ADDRESS_STRING_LENGTH]);
+
+#endif /* NV_DRM_ATOMIC_MODESET_AVAILABLE */
+
+#endif /* __NVIDIA_DRM_CONNECTOR_H__ */

NVIDIA-kernel-module-source-TempVersion/kernel-open/nvidia-drm/nvidia-drm-crtc.h

@@ -0,0 +1,300 @@
+/*
+ * Copyright (c) 2016-2022, NVIDIA CORPORATION. All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef __NVIDIA_DRM_CRTC_H__
+#define __NVIDIA_DRM_CRTC_H__
+
+#include "nvidia-drm-conftest.h"
+
+#if defined(NV_DRM_ATOMIC_MODESET_AVAILABLE)
+
+#include "nvidia-drm-helper.h"
+
+#if defined(NV_DRM_DRMP_H_PRESENT)
+#include <drm/drmP.h>
+#endif
+
+#include <drm/drm_crtc.h>
+
+#if defined(NV_DRM_ALPHA_BLENDING_AVAILABLE) || defined(NV_DRM_ROTATION_AVAILABLE)
+/* For DRM_ROTATE_* , DRM_REFLECT_* */
+#include <drm/drm_blend.h>
+#endif
+
+#if defined(NV_DRM_ROTATION_AVAILABLE)
+/* For DRM_MODE_ROTATE_* and DRM_MODE_REFLECT_* */
+#include <uapi/drm/drm_mode.h>
+#endif
+
+#include "nvtypes.h"
+#include "nvkms-kapi.h"
+
+#if defined(NV_DRM_ROTATION_AVAILABLE)
+/*
+ * 19-05-2017 c2c446ad29437bb92b157423c632286608ebd3ec has added
+ * DRM_MODE_ROTATE_* and DRM_MODE_REFLECT_* to UAPI and removed
+ * DRM_ROTATE_* and DRM_MODE_REFLECT_*
+ */
+#if !defined(DRM_MODE_ROTATE_0)
+#define DRM_MODE_ROTATE_0       DRM_ROTATE_0
+#define DRM_MODE_ROTATE_90      DRM_ROTATE_90
+#define DRM_MODE_ROTATE_180     DRM_ROTATE_180
+#define DRM_MODE_ROTATE_270     DRM_ROTATE_270
+#define DRM_MODE_REFLECT_X      DRM_REFLECT_X
+#define DRM_MODE_REFLECT_Y      DRM_REFLECT_Y
+#define DRM_MODE_ROTATE_MASK    DRM_ROTATE_MASK
+#define DRM_MODE_REFLECT_MASK   DRM_REFLECT_MASK
+#endif
+
+#endif //NV_DRM_ROTATION_AVAILABLE
+
+struct nv_drm_crtc {
+    NvU32 head;
+
+    /**
+     * @flip_list:
+     *
+     * List of flips pending to get processed by __nv_drm_handle_flip_event().
+     * Protected by @flip_list_lock.
+     */
+    struct list_head flip_list;
+
+    /**
+     * @flip_list_lock:
+     *
+     * Spinlock to protect @flip_list.
+     */
+    spinlock_t flip_list_lock;
+
+    struct drm_crtc base;
+};
+
+/**
+ * struct nv_drm_flip - flip state
+ *
+ * This state is getting used to consume DRM completion event associated
+ * with each crtc state from atomic commit.
+ *
+ * Function nv_drm_atomic_apply_modeset_config() consumes DRM completion
+ * event, save it into flip state associated with crtc and queue flip state into
+ * crtc's flip list and commits atomic update to hardware.
+ */
+struct nv_drm_flip {
+    /**
+     * @event:
+     *
+     * Optional pointer to a DRM event to signal upon completion of
+     * the state update.
+     */
+    struct drm_pending_vblank_event *event;
+
+    /**
+     * @pending_events
+     *
+     * Number of HW events pending to signal completion of the state
+     * update.
+     */
+    uint32_t pending_events;
+
+    /**
+     * @list_entry:
+     *
+     * Entry on the per-CRTC &nv_drm_crtc.flip_list. Protected by
+     * &nv_drm_crtc.flip_list_lock.
+     */
+    struct list_head list_entry;
+
+    /**
+     * @deferred_flip_list
+     *
+     * List flip objects whose processing is deferred until processing of
+     * this flip object. Protected by &nv_drm_crtc.flip_list_lock.
+     * nv_drm_atomic_commit() gets last flip object from
+     * nv_drm_crtc:flip_list and add deferred flip objects into
+     * @deferred_flip_list, __nv_drm_handle_flip_event() processes
+     * @deferred_flip_list.
+     */
+    struct list_head deferred_flip_list;
+};
+
+struct nv_drm_crtc_state {
+    /**
+     * @base:
+     *
+     * Base DRM crtc state object for this.
+     */
+    struct drm_crtc_state base;
+
+    /**
+     * @head_req_config:
+     *
+     * Requested head's modeset configuration corresponding to this crtc state.
+     */
+    struct NvKmsKapiHeadRequestedConfig req_config;
+
+    /**
+     * @nv_flip:
+     *
+     * Flip state associated with this crtc state, gets allocated
+     * by nv_drm_atomic_crtc_duplicate_state(), on successful commit it gets
+     * consumed and queued into flip list by
+     * nv_drm_atomic_apply_modeset_config() and finally gets destroyed
+     * by __nv_drm_handle_flip_event() after getting processed.
+     *
+     * In case of failure of atomic commit, this flip state getting destroyed by
+     * nv_drm_atomic_crtc_destroy_state().
+     */
+    struct nv_drm_flip *nv_flip;
+};
+
+static inline struct nv_drm_crtc_state *to_nv_crtc_state(struct drm_crtc_state *state)
+{
+    return container_of(state, struct nv_drm_crtc_state, base);
+}
+
+struct nv_drm_plane {
+    /**
+     * @base:
+     *
+     * Base DRM plane object for this plane.
+     */
+    struct drm_plane base;
+
+    /**
+     * @defaultCompositionMode:
+     *
+     * Default composition blending mode of this plane.
+     */
+    enum NvKmsCompositionBlendingMode defaultCompositionMode;
+
+    /**
+     * @layer_idx
+     *
+     * Index of this plane in the per head array of layers.
+     */
+    uint32_t layer_idx;
+};
+
+static inline struct nv_drm_plane *to_nv_plane(struct drm_plane *plane)
+{
+    if (plane == NULL) {
+        return NULL;
+    }
+    return container_of(plane, struct nv_drm_plane, base);
+}
+
+struct nv_drm_plane_state {
+    struct drm_plane_state base;
+    s32 __user *fd_user_ptr;
+    enum NvKmsInputColorSpace input_colorspace;
+#if defined(NV_DRM_HAS_HDR_OUTPUT_METADATA)
+    struct drm_property_blob *hdr_output_metadata;
+#endif
+};
+
+static inline struct nv_drm_plane_state *to_nv_drm_plane_state(struct drm_plane_state *state)
+{
+    return container_of(state, struct nv_drm_plane_state, base);
+}
+
+static inline struct nv_drm_crtc *to_nv_crtc(struct drm_crtc *crtc)
+{
+    if (crtc == NULL) {
+        return NULL;
+    }
+    return container_of(crtc, struct nv_drm_crtc, base);
+}
+
+/*
+ * CRTCs are static objects, list does not change once after initialization and
+ * before teardown of device. Initialization/teardown paths are single
+ * threaded, so no locking required.
+ */
+static inline
+struct nv_drm_crtc *nv_drm_crtc_lookup(struct nv_drm_device *nv_dev, NvU32 head)
+{
+    struct drm_crtc *crtc;
+    nv_drm_for_each_crtc(crtc, nv_dev->dev) {
+        struct nv_drm_crtc *nv_crtc = to_nv_crtc(crtc);
+
+        if (nv_crtc->head == head)  {
+            return nv_crtc;
+        }
+    }
+    return NULL;
+}
+
+/**
+ * nv_drm_crtc_enqueue_flip - Enqueue nv_drm_flip object to flip_list of crtc.
+ */
+static inline void nv_drm_crtc_enqueue_flip(struct nv_drm_crtc *nv_crtc,
+                                            struct nv_drm_flip *nv_flip)
+{
+    spin_lock(&nv_crtc->flip_list_lock);
+    list_add(&nv_flip->list_entry, &nv_crtc->flip_list);
+    spin_unlock(&nv_crtc->flip_list_lock);
+}
+
+/**
+ * nv_drm_crtc_dequeue_flip - Dequeue nv_drm_flip object to flip_list of crtc.
+ */
+static inline
+struct nv_drm_flip *nv_drm_crtc_dequeue_flip(struct nv_drm_crtc *nv_crtc)
+{
+    struct nv_drm_flip *nv_flip = NULL;
+    uint32_t pending_events = 0;
+
+    spin_lock(&nv_crtc->flip_list_lock);
+    nv_flip = list_first_entry_or_null(&nv_crtc->flip_list,
+                                       struct nv_drm_flip, list_entry);
+    if (likely(nv_flip != NULL)) {
+        /*
+         * Decrement pending_event count and dequeue flip object if
+         * pending_event count becomes 0.
+         */
+        pending_events = --nv_flip->pending_events;
+        if (!pending_events) {
+            list_del(&nv_flip->list_entry);
+        }
+    }
+    spin_unlock(&nv_crtc->flip_list_lock);
+
+    if (WARN_ON(nv_flip == NULL) || pending_events) {
+        return NULL;
+    }
+
+    return nv_flip;
+}
+
+void nv_drm_enumerate_crtcs_and_planes(
+    struct nv_drm_device *nv_dev,
+    const struct NvKmsKapiDeviceResourcesInfo *pResInfo);
+
+int nv_drm_get_crtc_crc32_ioctl(struct drm_device *dev,
+                                void *data, struct drm_file *filep);
+
+int nv_drm_get_crtc_crc32_v2_ioctl(struct drm_device *dev,
+                                   void *data, struct drm_file *filep);
+
+#endif /* NV_DRM_ATOMIC_MODESET_AVAILABLE */
+
+#endif /* __NVIDIA_DRM_CRTC_H__ */

NVIDIA-kernel-module-source-TempVersion/kernel-open/nvidia-drm/nvidia-drm-drv.h

@@ -0,0 +1,36 @@
+/*
+ * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef __NVIDIA_DRM_DRV_H__
+#define __NVIDIA_DRM_DRV_H__
+
+#include "nvidia-drm-conftest.h"
+
+#if defined(NV_DRM_AVAILABLE)
+
+int nv_drm_probe_devices(void);
+
+void nv_drm_remove_devices(void);
+
+#endif /* defined(NV_DRM_AVAILABLE) */
+
+#endif /* __NVIDIA_DRM_DRV_H__ */

NVIDIA-kernel-module-source-TempVersion/kernel-open/nvidia-drm/nvidia-drm-encoder.c

@@ -0,0 +1,352 @@
+/*
+ * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#include "nvidia-drm-conftest.h" /* NV_DRM_ATOMIC_MODESET_AVAILABLE */
+
+#if defined(NV_DRM_ATOMIC_MODESET_AVAILABLE)
+
+#include "nvidia-drm-priv.h"
+#include "nvidia-drm-encoder.h"
+#include "nvidia-drm-utils.h"
+#include "nvidia-drm-connector.h"
+#include "nvidia-drm-crtc.h"
+#include "nvidia-drm-helper.h"
+
+#include "nvmisc.h"
+
+/*
+ * Commit fcd70cd36b9b ("drm: Split out drm_probe_helper.h")
+ * moves a number of helper function definitions from
+ * drm/drm_crtc_helper.h to a new drm_probe_helper.h.
+ */
+#if defined(NV_DRM_DRM_PROBE_HELPER_H_PRESENT)
+#include <drm/drm_probe_helper.h>
+#endif
+#include <drm/drm_crtc_helper.h>
+
+#include <drm/drm_atomic.h>
+#include <drm/drm_atomic_helper.h>
+
+static void nv_drm_encoder_destroy(struct drm_encoder *encoder)
+{
+    struct nv_drm_encoder *nv_encoder = to_nv_encoder(encoder);
+
+    drm_encoder_cleanup(encoder);
+
+    nv_drm_free(nv_encoder);
+}
+
+static const struct drm_encoder_funcs nv_encoder_funcs = {
+    .destroy = nv_drm_encoder_destroy,
+};
+
+static bool nv_drm_encoder_mode_fixup(struct drm_encoder *encoder,
+                                      const struct drm_display_mode *mode,
+                                      struct drm_display_mode *adjusted_mode)
+{
+    return true;
+}
+
+static void nv_drm_encoder_prepare(struct drm_encoder *encoder)
+{
+
+}
+
+static void nv_drm_encoder_commit(struct drm_encoder *encoder)
+{
+
+}
+
+static void nv_drm_encoder_mode_set(struct drm_encoder *encoder,
+                                    struct drm_display_mode *mode,
+                                    struct drm_display_mode *adjusted_mode)
+{
+
+}
+
+static const struct drm_encoder_helper_funcs nv_encoder_helper_funcs = {
+    .mode_fixup = nv_drm_encoder_mode_fixup,
+    .prepare    = nv_drm_encoder_prepare,
+    .commit     = nv_drm_encoder_commit,
+    .mode_set   = nv_drm_encoder_mode_set,
+};
+
+static uint32_t get_crtc_mask(struct drm_device *dev, uint32_t headMask)
+{
+    struct drm_crtc *crtc = NULL;
+    uint32_t crtc_mask = 0x0;
+
+    nv_drm_for_each_crtc(crtc, dev) {
+        struct nv_drm_crtc *nv_crtc = to_nv_crtc(crtc);
+
+        if (headMask & NVBIT(nv_crtc->head)) {
+            crtc_mask |= drm_crtc_mask(crtc);
+        }
+    }
+
+    return crtc_mask;
+}
+
+/*
+ * Helper function to create new encoder for given NvKmsKapiDisplay
+ * with given signal format.
+ */
+static struct drm_encoder*
+nv_drm_encoder_new(struct drm_device *dev,
+                   NvKmsKapiDisplay hDisplay,
+                   NvKmsConnectorSignalFormat format,
+                   unsigned int crtc_mask)
+{
+    struct nv_drm_device *nv_dev = to_nv_device(dev);
+
+    struct nv_drm_encoder *nv_encoder = NULL;
+
+    int ret = 0;
+
+    /* Allocate an NVIDIA encoder object */
+
+    nv_encoder = nv_drm_calloc(1, sizeof(*nv_encoder));
+
+    if (nv_encoder == NULL) {
+        NV_DRM_DEV_LOG_ERR(
+            nv_dev,
+            "Failed to allocate memory for NVIDIA-DRM encoder object");
+        return ERR_PTR(-ENOMEM);
+    }
+
+    nv_encoder->hDisplay = hDisplay;
+
+    /* Initialize the base encoder object and add it to the drm subsystem */
+
+    ret = drm_encoder_init(dev,
+                           &nv_encoder->base, &nv_encoder_funcs,
+                           nvkms_connector_signal_to_drm_encoder_signal(format)
+#if defined(NV_DRM_ENCODER_INIT_HAS_NAME_ARG)
+                           , NULL
+#endif
+                           );
+
+    if (ret != 0) {
+        nv_drm_free(nv_encoder);
+
+        NV_DRM_DEV_LOG_ERR(
+            nv_dev,
+            "Failed to initialize encoder created from NvKmsKapiDisplay 0x%08x",
+            hDisplay);
+        return ERR_PTR(ret);
+    }
+
+    nv_encoder->base.possible_crtcs = crtc_mask;
+
+    drm_encoder_helper_add(&nv_encoder->base, &nv_encoder_helper_funcs);
+
+    return &nv_encoder->base;
+}
+
+/*
+ * Add encoder for given NvKmsKapiDisplay
+ */
+struct drm_encoder*
+nv_drm_add_encoder(struct drm_device *dev, NvKmsKapiDisplay hDisplay)
+{
+    struct nv_drm_device *nv_dev = to_nv_device(dev);
+
+    struct NvKmsKapiStaticDisplayInfo *displayInfo = NULL;
+    struct NvKmsKapiConnectorInfo *connectorInfo = NULL;
+
+    struct drm_encoder *encoder = NULL;
+    struct nv_drm_encoder *nv_encoder = NULL;
+
+    struct drm_connector *connector = NULL;
+
+    int ret = 0;
+
+    /* Query NvKmsKapiStaticDisplayInfo and NvKmsKapiConnectorInfo */
+
+    if ((displayInfo = nv_drm_calloc(1, sizeof(*displayInfo))) == NULL) {
+        ret = -ENOMEM;
+        goto done;
+    }
+
+    if (!nvKms->getStaticDisplayInfo(nv_dev->pDevice, hDisplay, displayInfo)) {
+        ret = -EINVAL;
+        goto done;
+    }
+
+    connectorInfo = nvkms_get_connector_info(nv_dev->pDevice,
+                                             displayInfo->connectorHandle);
+
+    if (IS_ERR(connectorInfo)) {
+        ret = PTR_ERR(connectorInfo);
+        goto done;
+    }
+
+    /* Create and add drm encoder */
+
+    encoder = nv_drm_encoder_new(dev,
+                                 displayInfo->handle,
+                                 connectorInfo->signalFormat,
+                                 get_crtc_mask(dev, connectorInfo->headMask));
+
+    if (IS_ERR(encoder)) {
+        ret = PTR_ERR(encoder);
+        goto done;
+    }
+
+    /* Get connector from respective physical index */
+
+    connector =
+        nv_drm_get_connector(dev,
+                                 connectorInfo->physicalIndex,
+                                 connectorInfo->type,
+                                 displayInfo->internal, displayInfo->dpAddress);
+
+    if (IS_ERR(connector)) {
+        ret = PTR_ERR(connector);
+        goto failed_connector_encoder_attach;
+    }
+
+    /* Attach encoder and connector */
+
+    ret = nv_drm_connector_attach_encoder(connector, encoder);
+
+    if (ret != 0) {
+        NV_DRM_DEV_LOG_ERR(
+            nv_dev,
+            "Failed to attach encoder created from NvKmsKapiDisplay 0x%08x "
+            "to connector",
+            hDisplay);
+        goto failed_connector_encoder_attach;
+    }
+
+    nv_encoder = to_nv_encoder(encoder);
+
+    mutex_lock(&dev->mode_config.mutex);
+
+    nv_encoder->nv_connector = to_nv_connector(connector);
+
+    nv_drm_connector_mark_connection_status_dirty(nv_encoder->nv_connector);
+
+    mutex_unlock(&dev->mode_config.mutex);
+
+    goto done;
+
+failed_connector_encoder_attach:
+
+    drm_encoder_cleanup(encoder);
+
+    nv_drm_free(encoder);
+
+done:
+
+    nv_drm_free(displayInfo);
+
+    nv_drm_free(connectorInfo);
+
+    return ret != 0 ? ERR_PTR(ret) : encoder;
+}
+
+static inline struct nv_drm_encoder*
+get_nv_encoder_from_nvkms_display(struct drm_device *dev,
+                                  NvKmsKapiDisplay hDisplay)
+{
+    struct drm_encoder *encoder;
+
+    nv_drm_for_each_encoder(encoder, dev) {
+        struct nv_drm_encoder *nv_encoder = to_nv_encoder(encoder);
+
+        if (nv_encoder->hDisplay == hDisplay) {
+            return nv_encoder;
+        }
+    }
+
+    return NULL;
+}
+
+void nv_drm_handle_display_change(struct nv_drm_device *nv_dev,
+                                  NvKmsKapiDisplay hDisplay)
+{
+    struct drm_device *dev = nv_dev->dev;
+    struct nv_drm_encoder *nv_encoder = NULL;
+
+    mutex_lock(&dev->mode_config.mutex);
+
+    nv_encoder = get_nv_encoder_from_nvkms_display(dev, hDisplay);
+
+    mutex_unlock(&dev->mode_config.mutex);
+
+    if (nv_encoder == NULL) {
+        return;
+    }
+
+    nv_drm_connector_mark_connection_status_dirty(nv_encoder->nv_connector);
+
+    drm_kms_helper_hotplug_event(dev);
+}
+
+void nv_drm_handle_dynamic_display_connected(struct nv_drm_device *nv_dev,
+                                             NvKmsKapiDisplay hDisplay)
+{
+    struct drm_device *dev = nv_dev->dev;
+
+    struct drm_encoder *encoder = NULL;
+    struct nv_drm_encoder *nv_encoder = NULL;
+
+    /*
+     * Look for an existing encoder with the same hDisplay and
+     * use it if available.
+     */
+
+    nv_encoder = get_nv_encoder_from_nvkms_display(dev, hDisplay);
+
+    if (nv_encoder != NULL) {
+        NV_DRM_DEV_LOG_ERR(
+            nv_dev,
+            "Encoder with NvKmsKapiDisplay 0x%08x already exists.",
+            hDisplay);
+        return;
+    }
+
+    encoder = nv_drm_add_encoder(dev, hDisplay);
+
+    if (IS_ERR(encoder)) {
+        NV_DRM_DEV_LOG_ERR(
+            nv_dev,
+            "Failed to add encoder for NvKmsKapiDisplay 0x%08x",
+            hDisplay);
+        return;
+    }
+
+    /*
+     * On some kernels, DRM has the notion of a "primary group" that
+     * tracks the global mode setting state for the device.
+     *
+     * On kernels where DRM has a primary group, we need to reinitialize
+     * after adding encoders and connectors.
+     */
+#if defined(NV_DRM_REINIT_PRIMARY_MODE_GROUP_PRESENT)
+    drm_reinit_primary_mode_group(dev);
+#endif
+
+    drm_kms_helper_hotplug_event(dev);
+}
+#endif

NVIDIA-kernel-module-source-TempVersion/kernel-open/nvidia-drm/nvidia-drm-encoder.h

@@ -0,0 +1,68 @@
+/*
+ * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef __NVIDIA_DRM_ENCODER_H__
+#define __NVIDIA_DRM_ENCODER_H__
+
+#include "nvidia-drm-conftest.h"
+
+#if defined(NV_DRM_ATOMIC_MODESET_AVAILABLE)
+
+#include "nvidia-drm-priv.h"
+
+#if defined(NV_DRM_DRM_ENCODER_H_PRESENT)
+#include <drm/drm_encoder.h>
+#else
+#include <drm/drmP.h>
+#endif
+
+#include "nvkms-kapi.h"
+
+struct nv_drm_encoder {
+    NvKmsKapiDisplay hDisplay;
+
+    struct nv_drm_connector *nv_connector;
+
+    struct drm_encoder base;
+};
+
+static inline struct nv_drm_encoder *to_nv_encoder(
+    struct drm_encoder *encoder)
+{
+    if (encoder == NULL) {
+        return NULL;
+    }
+    return container_of(encoder, struct nv_drm_encoder, base);
+}
+
+struct drm_encoder*
+nv_drm_add_encoder(struct drm_device *dev, NvKmsKapiDisplay hDisplay);
+
+void nv_drm_handle_display_change(struct nv_drm_device *nv_dev,
+                                  NvKmsKapiDisplay hDisplay);
+
+void nv_drm_handle_dynamic_display_connected(struct nv_drm_device *nv_dev,
+                                             NvKmsKapiDisplay hDisplay);
+
+#endif /* NV_DRM_ATOMIC_MODESET_AVAILABLE */
+
+#endif /* __NVIDIA_DRM_ENCODER_H__ */

NVIDIA-kernel-module-source-TempVersion/kernel-open/nvidia-drm/nvidia-drm-fb.c

@@ -0,0 +1,257 @@
+/*
+ * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#include "nvidia-drm-conftest.h" /* NV_DRM_ATOMIC_MODESET_AVAILABLE */
+
+#if defined(NV_DRM_ATOMIC_MODESET_AVAILABLE)
+
+#include "nvidia-drm-priv.h"
+#include "nvidia-drm-ioctl.h"
+#include "nvidia-drm-fb.h"
+#include "nvidia-drm-utils.h"
+#include "nvidia-drm-gem.h"
+#include "nvidia-drm-helper.h"
+#include "nvidia-drm-format.h"
+
+#include <drm/drm_crtc_helper.h>
+
+static void __nv_drm_framebuffer_free(struct nv_drm_framebuffer *nv_fb)
+{
+    uint32_t i;
+
+    /* Unreference gem object */
+    for (i = 0; i < ARRAY_SIZE(nv_fb->nv_gem); i++) {
+        if (nv_fb->nv_gem[i] != NULL) {
+            nv_drm_gem_object_unreference_unlocked(nv_fb->nv_gem[i]);
+        }
+    }
+
+    /* Free framebuffer */
+    nv_drm_free(nv_fb);
+}
+
+static void nv_drm_framebuffer_destroy(struct drm_framebuffer *fb)
+{
+    struct nv_drm_device *nv_dev = to_nv_device(fb->dev);
+    struct nv_drm_framebuffer *nv_fb = to_nv_framebuffer(fb);
+
+    /* Cleaup core framebuffer object */
+
+    drm_framebuffer_cleanup(fb);
+
+    /* Free NvKmsKapiSurface associated with this framebuffer object */
+
+    nvKms->destroySurface(nv_dev->pDevice, nv_fb->pSurface);
+
+    __nv_drm_framebuffer_free(nv_fb);
+}
+
+static int
+nv_drm_framebuffer_create_handle(struct drm_framebuffer *fb,
+                                 struct drm_file *file, unsigned int *handle)
+{
+    struct nv_drm_framebuffer *nv_fb = to_nv_framebuffer(fb);
+
+    return nv_drm_gem_handle_create(file,
+                                    nv_fb->nv_gem[0],
+                                    handle);
+}
+
+static struct drm_framebuffer_funcs nv_framebuffer_funcs = {
+    .destroy       = nv_drm_framebuffer_destroy,
+    .create_handle = nv_drm_framebuffer_create_handle,
+};
+
+static struct nv_drm_framebuffer *nv_drm_framebuffer_alloc(
+    struct drm_device *dev,
+    struct drm_file *file,
+    struct drm_mode_fb_cmd2 *cmd)
+{
+    struct nv_drm_device *nv_dev = to_nv_device(dev);
+    struct nv_drm_framebuffer *nv_fb;
+    const int num_planes = nv_drm_format_num_planes(cmd->pixel_format);
+    uint32_t i;
+
+    /* Allocate memory for the framebuffer object */
+    nv_fb = nv_drm_calloc(1, sizeof(*nv_fb));
+
+    if (nv_fb == NULL) {
+        NV_DRM_DEV_DEBUG_DRIVER(
+            nv_dev,
+            "Failed to allocate memory for framebuffer object");
+        return ERR_PTR(-ENOMEM);
+    }
+
+    if (num_planes > ARRAY_SIZE(nv_fb->nv_gem)) {
+        NV_DRM_DEV_DEBUG_DRIVER(nv_dev, "Unsupported number of planes");
+        goto failed;
+    }
+
+    for (i = 0; i < num_planes; i++) {
+        if ((nv_fb->nv_gem[i] = nv_drm_gem_object_lookup(
+                        dev,
+                        file,
+                        cmd->handles[i])) == NULL) {
+            NV_DRM_DEV_DEBUG_DRIVER(
+                nv_dev,
+                "Failed to find gem object of type nvkms memory");
+            goto failed;
+        }
+    }
+
+     return nv_fb;
+
+failed:
+
+    __nv_drm_framebuffer_free(nv_fb);
+
+    return ERR_PTR(-ENOENT);
+}
+
+static int nv_drm_framebuffer_init(struct drm_device *dev,
+                                   struct nv_drm_framebuffer *nv_fb,
+                                   enum NvKmsSurfaceMemoryFormat format,
+                                   bool have_modifier,
+                                   uint64_t modifier)
+{
+    struct nv_drm_device *nv_dev = to_nv_device(dev);
+    struct NvKmsKapiCreateSurfaceParams params = { };
+    uint32_t i;
+    int ret;
+
+    /* Initialize the base framebuffer object and add it to drm subsystem */
+
+    ret = drm_framebuffer_init(dev, &nv_fb->base, &nv_framebuffer_funcs);
+    if (ret != 0) {
+        NV_DRM_DEV_DEBUG_DRIVER(
+            nv_dev,
+            "Failed to initialize framebuffer object");
+        return ret;
+    }
+
+    for (i = 0; i < ARRAY_SIZE(nv_fb->nv_gem); i++) {
+        if (nv_fb->nv_gem[i] != NULL) {
+            params.planes[i].memory = nv_fb->nv_gem[i]->pMemory;
+            params.planes[i].offset = nv_fb->base.offsets[i];
+            params.planes[i].pitch = nv_fb->base.pitches[i];
+        }
+    }
+    params.height = nv_fb->base.height;
+    params.width = nv_fb->base.width;
+    params.format = format;
+
+    if (have_modifier) {
+        params.explicit_layout = true;
+        params.layout = (modifier & 0x10) ?
+            NvKmsSurfaceMemoryLayoutBlockLinear :
+            NvKmsSurfaceMemoryLayoutPitch;
+        params.log2GobsPerBlockY = modifier & 0xf;
+    } else {
+        params.explicit_layout = false;
+    }
+
+    /* Create NvKmsKapiSurface */
+
+    nv_fb->pSurface = nvKms->createSurface(nv_dev->pDevice, &params);
+    if (nv_fb->pSurface == NULL) {
+        NV_DRM_DEV_DEBUG_DRIVER(nv_dev, "Failed to create NvKmsKapiSurface");
+        drm_framebuffer_cleanup(&nv_fb->base);
+        return -EINVAL;
+    }
+
+    return 0;
+}
+
+struct drm_framebuffer *nv_drm_internal_framebuffer_create(
+    struct drm_device *dev,
+    struct drm_file *file,
+    struct drm_mode_fb_cmd2 *cmd)
+{
+    struct nv_drm_device *nv_dev = to_nv_device(dev);
+    struct nv_drm_framebuffer *nv_fb;
+    uint64_t modifier = 0;
+    int ret;
+    enum NvKmsSurfaceMemoryFormat format;
+#if defined(NV_DRM_FORMAT_MODIFIERS_PRESENT)
+    int i;
+#endif
+    bool have_modifier = false;
+
+    /* Check whether NvKms supports the given pixel format */
+    if (!nv_drm_format_to_nvkms_format(cmd->pixel_format, &format)) {
+        NV_DRM_DEV_DEBUG_DRIVER(
+            nv_dev,
+            "Unsupported drm pixel format 0x%08x", cmd->pixel_format);
+        return ERR_PTR(-EINVAL);
+    }
+
+#if defined(NV_DRM_FORMAT_MODIFIERS_PRESENT)
+    if (cmd->flags & DRM_MODE_FB_MODIFIERS) {
+        have_modifier = true;
+        modifier = cmd->modifier[0];
+
+        for (i = 0; nv_dev->modifiers[i] != DRM_FORMAT_MOD_INVALID; i++) {
+            if (nv_dev->modifiers[i] == modifier) {
+                break;
+            }
+        }
+
+        if (nv_dev->modifiers[i] == DRM_FORMAT_MOD_INVALID) {
+            NV_DRM_DEV_DEBUG_DRIVER(
+                nv_dev,
+                "Invalid format modifier for framebuffer object: 0x%016llx",
+                modifier);
+            return ERR_PTR(-EINVAL);
+        }
+    }
+#endif
+
+    nv_fb = nv_drm_framebuffer_alloc(dev, file, cmd);
+    if (IS_ERR(nv_fb)) {
+        return (struct drm_framebuffer *)nv_fb;
+    }
+
+    /* Fill out framebuffer metadata from the userspace fb creation request */
+
+    drm_helper_mode_fill_fb_struct(
+        #if defined(NV_DRM_HELPER_MODE_FILL_FB_STRUCT_HAS_DEV_ARG)
+        dev,
+        #endif
+        &nv_fb->base,
+        cmd);
+
+    /*
+     * Finish up FB initialization by creating the backing NVKMS surface and
+     * publishing the DRM fb
+     */
+
+    ret = nv_drm_framebuffer_init(dev, nv_fb, format, have_modifier, modifier);
+
+    if (ret != 0) {
+        __nv_drm_framebuffer_free(nv_fb);
+        return ERR_PTR(ret);
+    }
+
+    return &nv_fb->base;
+}
+
+#endif

NVIDIA-kernel-module-source-TempVersion/kernel-open/nvidia-drm/nvidia-drm-fb.h

@@ -0,0 +1,66 @@
+/*
+ * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef __NVIDIA_DRM_FB_H__
+#define __NVIDIA_DRM_FB_H__
+
+#include "nvidia-drm-conftest.h"
+
+#if defined(NV_DRM_ATOMIC_MODESET_AVAILABLE)
+
+#if defined(NV_DRM_DRMP_H_PRESENT)
+#include <drm/drmP.h>
+#endif
+
+#if defined(NV_DRM_DRM_FRAMEBUFFER_H_PRESENT)
+#include <drm/drm_framebuffer.h>
+#endif
+
+#include "nvidia-drm-gem-nvkms-memory.h"
+#include "nvkms-kapi.h"
+
+struct nv_drm_framebuffer {
+    struct NvKmsKapiSurface *pSurface;
+
+    struct nv_drm_gem_object*
+        nv_gem[NVKMS_MAX_PLANES_PER_SURFACE];
+
+    struct drm_framebuffer base;
+};
+
+static inline struct nv_drm_framebuffer *to_nv_framebuffer(
+    struct drm_framebuffer *fb)
+{
+    if (fb == NULL) {
+        return NULL;
+    }
+    return container_of(fb, struct nv_drm_framebuffer, base);
+}
+
+struct drm_framebuffer *nv_drm_internal_framebuffer_create(
+    struct drm_device *dev,
+    struct drm_file *file,
+    struct drm_mode_fb_cmd2 *cmd);
+
+#endif /* NV_DRM_ATOMIC_MODESET_AVAILABLE */
+
+#endif /* __NVIDIA_DRM_FB_H__ */

NVIDIA-kernel-module-source-TempVersion/kernel-open/nvidia-drm/nvidia-drm-format.c

@@ -0,0 +1,163 @@
+/*
+ * Copyright (c) 2019-2022, NVIDIA CORPORATION. All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#include "nvidia-drm-conftest.h" /* NV_DRM_ATOMIC_MODESET_AVAILABLE */
+
+#if defined(NV_DRM_ATOMIC_MODESET_AVAILABLE)
+
+#if defined(NV_DRM_DRMP_H_PRESENT)
+#include <drm/drmP.h>
+#endif
+#include <linux/kernel.h>
+#include <linux/bitmap.h>
+
+#include "nvidia-drm-format.h"
+#include "nvidia-drm-os-interface.h"
+
+static const u32  nvkms_to_drm_format[] = {
+    /* RGB formats */
+    [NvKmsSurfaceMemoryFormatA1R5G5B5]    = DRM_FORMAT_ARGB1555,
+    [NvKmsSurfaceMemoryFormatX1R5G5B5]    = DRM_FORMAT_XRGB1555,
+    [NvKmsSurfaceMemoryFormatR5G6B5]      = DRM_FORMAT_RGB565,
+    [NvKmsSurfaceMemoryFormatA8R8G8B8]    = DRM_FORMAT_ARGB8888,
+    [NvKmsSurfaceMemoryFormatX8R8G8B8]    = DRM_FORMAT_XRGB8888,
+    [NvKmsSurfaceMemoryFormatX8B8G8R8]    = DRM_FORMAT_XBGR8888,
+    [NvKmsSurfaceMemoryFormatA2B10G10R10] = DRM_FORMAT_ABGR2101010,
+    [NvKmsSurfaceMemoryFormatX2B10G10R10] = DRM_FORMAT_XBGR2101010,
+    [NvKmsSurfaceMemoryFormatA8B8G8R8]    = DRM_FORMAT_ABGR8888,
+
+    [NvKmsSurfaceMemoryFormatY8_U8__Y8_V8_N422] = DRM_FORMAT_YUYV,
+    [NvKmsSurfaceMemoryFormatU8_Y8__V8_Y8_N422] = DRM_FORMAT_UYVY,
+
+    /* YUV semi-planar formats
+     *
+     * NVKMS YUV semi-planar formats are MSB aligned. Yx__UxVx means
+     * that the UV components are packed like UUUUUVVVVV (MSB to LSB)
+     * and Yx_VxUx means VVVVVUUUUU (MSB to LSB).
+     */
+
+    /*
+     * 2 plane YCbCr
+     * index 0 = Y plane, [7:0] Y
+     * index 1 = Cr:Cb plane, [15:0] Cr:Cb little endian
+     * or
+     * index 1 = Cb:Cr plane, [15:0] Cb:Cr little endian
+     */
+    [NvKmsSurfaceMemoryFormatY8___V8U8_N444]    = DRM_FORMAT_NV24, /* non-subsampled Cr:Cb plane */
+    [NvKmsSurfaceMemoryFormatY8___U8V8_N444]    = DRM_FORMAT_NV42, /* non-subsampled Cb:Cr plane */
+    [NvKmsSurfaceMemoryFormatY8___V8U8_N422]    = DRM_FORMAT_NV16, /* 2x1 subsampled Cr:Cb plane */
+    [NvKmsSurfaceMemoryFormatY8___U8V8_N422]    = DRM_FORMAT_NV61, /* 2x1 subsampled Cb:Cr plane */
+    [NvKmsSurfaceMemoryFormatY8___V8U8_N420]    = DRM_FORMAT_NV12, /* 2x2 subsampled Cr:Cb plane */
+    [NvKmsSurfaceMemoryFormatY8___U8V8_N420]    = DRM_FORMAT_NV21, /* 2x2 subsampled Cb:Cr plane */
+
+#if defined(DRM_FORMAT_P210)
+    /*
+     * 2 plane YCbCr MSB aligned
+     * index 0 = Y plane, [15:0] Y:x [10:6] little endian
+     * index 1 = Cr:Cb plane, [31:0] Cr:x:Cb:x [10:6:10:6] little endian
+     *
+     * 2x1 subsampled Cr:Cb plane, 10 bit per channel
+     */
+    [NvKmsSurfaceMemoryFormatY10___V10U10_N422] = DRM_FORMAT_P210,
+#endif
+
+#if defined(DRM_FORMAT_P010)
+    /*
+     * 2 plane YCbCr MSB aligned
+     * index 0 = Y plane, [15:0] Y:x [10:6] little endian
+     * index 1 = Cr:Cb plane, [31:0] Cr:x:Cb:x [10:6:10:6] little endian
+     *
+     * 2x2 subsampled Cr:Cb plane 10 bits per channel
+     */
+    [NvKmsSurfaceMemoryFormatY10___V10U10_N420] = DRM_FORMAT_P010,
+#endif
+
+#if defined(DRM_FORMAT_P012)
+    /*
+     * 2 plane YCbCr MSB aligned
+     * index 0 = Y plane, [15:0] Y:x [12:4] little endian
+     * index 1 = Cr:Cb plane, [31:0] Cr:x:Cb:x [12:4:12:4] little endian
+     *
+     * 2x2 subsampled Cr:Cb plane 12 bits per channel
+     */
+    [NvKmsSurfaceMemoryFormatY12___V12U12_N420] = DRM_FORMAT_P012,
+#endif
+};
+
+bool nv_drm_format_to_nvkms_format(u32 format,
+                                   enum NvKmsSurfaceMemoryFormat *nvkms_format)
+{
+    enum NvKmsSurfaceMemoryFormat i;
+    for (i = 0; i < ARRAY_SIZE(nvkms_to_drm_format); i++) {
+        /*
+         * Note nvkms_to_drm_format[] is sparsely populated: it doesn't
+         * handle all NvKmsSurfaceMemoryFormat values, so be sure to skip 0
+         * entries when iterating through it.
+         */
+        if (nvkms_to_drm_format[i] != 0 && nvkms_to_drm_format[i] == format) {
+            *nvkms_format = i;
+            return true;
+        }
+    }
+    return false;
+}
+
+uint32_t *nv_drm_format_array_alloc(
+    unsigned int *count,
+    const long unsigned int nvkms_format_mask)
+{
+    enum NvKmsSurfaceMemoryFormat i;
+    unsigned int max_count = hweight64(nvkms_format_mask);
+    uint32_t *array = nv_drm_calloc(1, sizeof(uint32_t) * max_count);
+
+    if (array == NULL) {
+        return NULL;
+    }
+
+    *count = 0;
+    for_each_set_bit(i, &nvkms_format_mask,
+        sizeof(nvkms_format_mask) * BITS_PER_BYTE) {
+
+        if (i >= ARRAY_SIZE(nvkms_to_drm_format)) {
+            break;
+        }
+
+        /*
+         * Note nvkms_to_drm_format[] is sparsely populated: it doesn't
+         * handle all NvKmsSurfaceMemoryFormat values, so be sure to skip 0
+         * entries when iterating through it.
+         */
+        if (nvkms_to_drm_format[i] == 0) {
+            continue;
+        }
+        array[(*count)++] = nvkms_to_drm_format[i];
+    }
+
+    if (*count == 0) {
+        nv_drm_free(array);
+        return NULL;
+    }
+
+    return array;
+}
+
+#endif

NVIDIA-kernel-module-source-TempVersion/kernel-open/nvidia-drm/nvidia-drm-format.h

@@ -0,0 +1,43 @@
+/*
+ * Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef __NVIDIA_DRM_FORMAT_H__
+#define __NVIDIA_DRM_FORMAT_H__
+
+#include "nvidia-drm-conftest.h"
+
+#if defined(NV_DRM_ATOMIC_MODESET_AVAILABLE)
+
+#include <drm/drm_fourcc.h>
+
+#include "nvkms-format.h"
+
+bool nv_drm_format_to_nvkms_format(u32 format,
+                                   enum NvKmsSurfaceMemoryFormat *nvkms_format);
+
+uint32_t *nv_drm_format_array_alloc(
+    unsigned int *count,
+    const long unsigned int nvkms_format_mask);
+
+#endif /* NV_DRM_ATOMIC_MODESET_AVAILABLE */
+
+#endif /* __NVIDIA_DRM_FORMAT_H__ */

NVIDIA-kernel-module-source-TempVersion/kernel-open/nvidia-drm/nvidia-drm-gem-dma-buf.c

@@ -0,0 +1,228 @@
+/*
+ * Copyright (c) 2020, NVIDIA CORPORATION. All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#include "nvidia-drm-conftest.h"
+
+#if defined(NV_DRM_AVAILABLE)
+
+#if defined(NV_DRM_DRM_PRIME_H_PRESENT)
+#include <drm/drm_prime.h>
+#endif
+
+#if defined(NV_DRM_DRMP_H_PRESENT)
+#include <drm/drmP.h>
+#endif
+
+#if defined(NV_DRM_DRM_DRV_H_PRESENT)
+#include <drm/drm_drv.h>
+#endif
+
+#include "nvidia-drm-gem-dma-buf.h"
+#include "nvidia-drm-ioctl.h"
+
+#include "linux/dma-buf.h"
+
+static inline
+void __nv_drm_gem_dma_buf_free(struct nv_drm_gem_object *nv_gem)
+{
+    struct nv_drm_device *nv_dev = nv_gem->nv_dev;
+    struct nv_drm_gem_dma_buf *nv_dma_buf = to_nv_dma_buf(nv_gem);
+
+#if defined(NV_DRM_ATOMIC_MODESET_AVAILABLE)
+    if (nv_dma_buf->base.pMemory) {
+        /* Free NvKmsKapiMemory handle associated with this gem object */
+        nvKms->freeMemory(nv_dev->pDevice, nv_dma_buf->base.pMemory);
+    }
+#endif
+
+    drm_prime_gem_destroy(&nv_gem->base, nv_dma_buf->sgt);
+
+    nv_drm_free(nv_dma_buf);
+}
+
+static int __nv_drm_gem_dma_buf_create_mmap_offset(
+    struct nv_drm_device *nv_dev,
+    struct nv_drm_gem_object *nv_gem,
+    uint64_t *offset)
+{
+    (void)nv_dev;
+    return nv_drm_gem_create_mmap_offset(nv_gem, offset);
+}
+
+static int __nv_drm_gem_dma_buf_mmap(struct nv_drm_gem_object *nv_gem,
+                                     struct vm_area_struct *vma)
+{
+    struct dma_buf_attachment *attach = nv_gem->base.import_attach;
+    struct dma_buf *dma_buf = attach->dmabuf;
+    struct file *old_file;
+    int ret;
+
+    /* check if buffer supports mmap */
+    if (!dma_buf->file->f_op->mmap)
+        return -EINVAL;
+
+    /* readjust the vma */
+    get_file(dma_buf->file);
+    old_file = vma->vm_file;
+    vma->vm_file = dma_buf->file;
+    vma->vm_pgoff -= drm_vma_node_start(&nv_gem->base.vma_node);;
+
+    ret = dma_buf->file->f_op->mmap(dma_buf->file, vma);
+
+    if (ret) {
+        /* restore old parameters on failure */
+        vma->vm_file = old_file;
+        fput(dma_buf->file);
+    } else {
+        if (old_file)
+            fput(old_file);
+    }
+
+    return ret;
+}
+
+const struct nv_drm_gem_object_funcs __nv_gem_dma_buf_ops = {
+    .free = __nv_drm_gem_dma_buf_free,
+    .create_mmap_offset = __nv_drm_gem_dma_buf_create_mmap_offset,
+    .mmap = __nv_drm_gem_dma_buf_mmap,
+};
+
+struct drm_gem_object*
+nv_drm_gem_prime_import_sg_table(struct drm_device *dev,
+                                 struct dma_buf_attachment *attach,
+                                 struct sg_table *sgt)
+{
+    struct nv_drm_device *nv_dev = to_nv_device(dev);
+    struct dma_buf *dma_buf = attach->dmabuf;
+    struct nv_drm_gem_dma_buf *nv_dma_buf;
+    struct NvKmsKapiMemory *pMemory;
+
+    if ((nv_dma_buf =
+            nv_drm_calloc(1, sizeof(*nv_dma_buf))) == NULL) {
+        return NULL;
+    }
+
+    // dma_buf->size must be a multiple of PAGE_SIZE
+    BUG_ON(dma_buf->size % PAGE_SIZE);
+
+    pMemory = NULL;
+#if defined(NV_DRM_ATOMIC_MODESET_AVAILABLE)
+    if (drm_core_check_feature(dev, DRIVER_MODESET)) {
+        pMemory = nvKms->getSystemMemoryHandleFromDmaBuf(nv_dev->pDevice,
+                                                  (NvP64)(NvUPtr)dma_buf,
+                                                  dma_buf->size - 1);
+    }
+#endif
+
+    nv_drm_gem_object_init(nv_dev, &nv_dma_buf->base,
+                           &__nv_gem_dma_buf_ops, dma_buf->size, pMemory);
+
+    nv_dma_buf->sgt = sgt;
+
+    return &nv_dma_buf->base.base;
+}
+
+int nv_drm_gem_export_dmabuf_memory_ioctl(struct drm_device *dev,
+                                          void *data, struct drm_file *filep)
+{
+    struct nv_drm_device *nv_dev = to_nv_device(dev);
+    struct drm_nvidia_gem_export_dmabuf_memory_params *p = data;
+    struct nv_drm_gem_dma_buf *nv_dma_buf = NULL;
+    int ret = 0;
+    struct NvKmsKapiMemory *pTmpMemory = NULL;
+
+    if (!drm_core_check_feature(dev, DRIVER_MODESET)) {
+        ret = -EINVAL;
+        goto done;
+    }
+
+    if (p->__pad != 0) {
+        ret = -EINVAL;
+        NV_DRM_DEV_LOG_ERR(nv_dev, "Padding fields must be zeroed");
+        goto done;
+    }
+
+    if ((nv_dma_buf = nv_drm_gem_object_dma_buf_lookup(
+             dev, filep, p->handle)) == NULL) {
+        ret = -EINVAL;
+        NV_DRM_DEV_LOG_ERR(
+            nv_dev,
+            "Failed to lookup DMA-BUF GEM object for export: 0x%08x",
+            p->handle);
+        goto done;
+    }
+
+#if defined(NV_DRM_ATOMIC_MODESET_AVAILABLE)
+    if (drm_core_check_feature(dev, DRIVER_MODESET)) {
+        if (!nv_dma_buf->base.pMemory) {
+            /*
+             * Get RM system memory handle from SGT - RM will take a reference
+             * on this GEM object to prevent the DMA-BUF from being unpinned
+             * prematurely.
+             */
+            pTmpMemory = nvKms->getSystemMemoryHandleFromSgt(
+                             nv_dev->pDevice,
+                             (NvP64)(NvUPtr)nv_dma_buf->sgt,
+                             (NvP64)(NvUPtr)&nv_dma_buf->base.base,
+                             nv_dma_buf->base.base.size - 1);
+        }
+    }
+#endif
+
+    if (!nv_dma_buf->base.pMemory && !pTmpMemory) {
+        ret = -ENOMEM;
+        NV_DRM_DEV_LOG_ERR(
+            nv_dev,
+            "Failed to get memory to export from DMA-BUF GEM object: 0x%08x",
+            p->handle);
+        goto done;
+    }
+
+    if (!nvKms->exportMemory(nv_dev->pDevice,
+                             nv_dma_buf->base.pMemory ?
+                                nv_dma_buf->base.pMemory : pTmpMemory,
+                             p->nvkms_params_ptr,
+                             p->nvkms_params_size)) {
+        ret = -EINVAL;
+        NV_DRM_DEV_LOG_ERR(
+            nv_dev,
+            "Failed to export memory from DMA-BUF GEM object: 0x%08x",
+            p->handle);
+        goto done;
+    }
+
+done:
+    if (pTmpMemory) {
+        /*
+         * Release reference on RM system memory to prevent circular
+         * refcounting. Another refcount will still be held by RM FD.
+         */
+        nvKms->freeMemory(nv_dev->pDevice, pTmpMemory);
+    }
+
+    if (nv_dma_buf != NULL) {
+        nv_drm_gem_object_unreference_unlocked(&nv_dma_buf->base);
+    }
+
+    return ret;
+}
+#endif

NVIDIA-kernel-module-source-TempVersion/kernel-open/nvidia-drm/nvidia-drm-gem-dma-buf.h

@@ -0,0 +1,76 @@
+/*
+ * Copyright (c) 2020, NVIDIA CORPORATION. All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef __NVIDIA_DRM_GEM_DMA_BUF_H__
+#define __NVIDIA_DRM_GEM_DMA_BUF_H__
+
+#include "nvidia-drm-conftest.h"
+
+#if defined(NV_DRM_AVAILABLE)
+
+#include "nvidia-drm-gem.h"
+
+struct nv_drm_gem_dma_buf {
+    struct nv_drm_gem_object base;
+    struct sg_table *sgt;
+};
+
+extern const struct nv_drm_gem_object_funcs __nv_gem_dma_buf_ops;
+
+static inline struct nv_drm_gem_dma_buf *to_nv_dma_buf(
+    struct nv_drm_gem_object *nv_gem)
+{
+    if (nv_gem != NULL) {
+        return container_of(nv_gem, struct nv_drm_gem_dma_buf, base);
+    }
+
+    return NULL;
+}
+
+static inline
+struct nv_drm_gem_dma_buf *nv_drm_gem_object_dma_buf_lookup(
+    struct drm_device *dev,
+    struct drm_file *filp,
+    u32 handle)
+{
+    struct nv_drm_gem_object *nv_gem =
+            nv_drm_gem_object_lookup(dev, filp, handle);
+
+    if (nv_gem != NULL && nv_gem->ops != &__nv_gem_dma_buf_ops) {
+        nv_drm_gem_object_unreference_unlocked(nv_gem);
+        return NULL;
+    }
+
+    return to_nv_dma_buf(nv_gem);
+}
+
+struct drm_gem_object*
+nv_drm_gem_prime_import_sg_table(struct drm_device *dev,
+                                 struct dma_buf_attachment *attach,
+                                 struct sg_table *sgt);
+
+int nv_drm_gem_export_dmabuf_memory_ioctl(struct drm_device *dev,
+                                          void *data, struct drm_file *filep);
+
+#endif
+
+#endif /* __NVIDIA_DRM_GEM_DMA_BUF_H__ */

NVIDIA-kernel-module-source-TempVersion/kernel-open/nvidia-drm/nvidia-drm-gem-nvkms-memory.c

@@ -0,0 +1,592 @@
+/*
+ * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#include "nvidia-drm-conftest.h"
+
+#if defined(NV_DRM_ATOMIC_MODESET_AVAILABLE)
+
+#include "nvidia-drm-gem-nvkms-memory.h"
+#include "nvidia-drm-helper.h"
+#include "nvidia-drm-ioctl.h"
+
+#if defined(NV_DRM_DRM_DRV_H_PRESENT)
+#include <drm/drm_drv.h>
+#endif
+
+#if defined(NV_DRM_DRM_PRIME_H_PRESENT)
+#include <drm/drm_prime.h>
+#endif
+
+#include <linux/io.h>
+
+#include "nv-mm.h"
+
+static void __nv_drm_gem_nvkms_memory_free(struct nv_drm_gem_object *nv_gem)
+{
+    struct nv_drm_device *nv_dev = nv_gem->nv_dev;
+    struct nv_drm_gem_nvkms_memory *nv_nvkms_memory =
+        to_nv_nvkms_memory(nv_gem);
+
+    if (nv_nvkms_memory->physically_mapped) {
+        if (nv_nvkms_memory->pWriteCombinedIORemapAddress != NULL) {
+            iounmap(nv_nvkms_memory->pWriteCombinedIORemapAddress);
+        }
+
+        nvKms->unmapMemory(nv_dev->pDevice,
+                           nv_nvkms_memory->base.pMemory,
+                           NVKMS_KAPI_MAPPING_TYPE_USER,
+                           nv_nvkms_memory->pPhysicalAddress);
+    }
+
+    if (nv_nvkms_memory->pages_count != 0) {
+        nvKms->freeMemoryPages((NvU64 *)nv_nvkms_memory->pages);
+    }
+
+    /* Free NvKmsKapiMemory handle associated with this gem object */
+
+    nvKms->freeMemory(nv_dev->pDevice, nv_nvkms_memory->base.pMemory);
+
+    nv_drm_free(nv_nvkms_memory);
+}
+
+static int __nv_drm_gem_nvkms_mmap(struct nv_drm_gem_object *nv_gem,
+                                   struct vm_area_struct *vma)
+{
+    return drm_gem_mmap_obj(&nv_gem->base,
+                drm_vma_node_size(&nv_gem->base.vma_node) << PAGE_SHIFT, vma);
+}
+
+static vm_fault_t __nv_drm_gem_nvkms_handle_vma_fault(
+    struct nv_drm_gem_object *nv_gem,
+    struct vm_area_struct *vma,
+    struct vm_fault *vmf)
+{
+#if defined(NV_DRM_ATOMIC_MODESET_AVAILABLE)
+    struct nv_drm_gem_nvkms_memory *nv_nvkms_memory =
+        to_nv_nvkms_memory(nv_gem);
+    unsigned long address = nv_page_fault_va(vmf);
+    struct drm_gem_object *gem = vma->vm_private_data;
+    unsigned long page_offset, pfn;
+    vm_fault_t ret;
+
+    page_offset = vmf->pgoff - drm_vma_node_start(&gem->vma_node);
+
+    if (nv_nvkms_memory->pages_count == 0) {
+        pfn = (unsigned long)(uintptr_t)nv_nvkms_memory->pPhysicalAddress;
+        pfn >>= PAGE_SHIFT;
+        pfn += page_offset;
+    } else {
+        BUG_ON(page_offset > nv_nvkms_memory->pages_count);
+        pfn = page_to_pfn(nv_nvkms_memory->pages[page_offset]);
+    }
+
+#if defined(NV_VMF_INSERT_PFN_PRESENT)
+    ret = vmf_insert_pfn(vma, address, pfn);
+#else
+    ret = vm_insert_pfn(vma, address, pfn);
+    switch (ret) {
+        case 0:
+        case -EBUSY:
+            /*
+             * EBUSY indicates that another thread already handled
+             * the faulted range.
+             */
+            ret = VM_FAULT_NOPAGE;
+            break;
+        case -ENOMEM:
+            ret = VM_FAULT_OOM;
+            break;
+        default:
+            WARN_ONCE(1, "Unhandled error in %s: %d\n", __FUNCTION__, ret);
+            ret = VM_FAULT_SIGBUS;
+            break;
+    }
+#endif /* defined(NV_VMF_INSERT_PFN_PRESENT) */
+    return ret;
+#endif /* defined(NV_DRM_ATOMIC_MODESET_AVAILABLE) */
+    return VM_FAULT_SIGBUS;
+}
+
+static struct drm_gem_object *__nv_drm_gem_nvkms_prime_dup(
+    struct drm_device *dev,
+    const struct nv_drm_gem_object *nv_gem_src);
+
+static int __nv_drm_gem_nvkms_map(
+    struct nv_drm_device *nv_dev,
+    struct NvKmsKapiMemory *pMemory,
+    struct nv_drm_gem_nvkms_memory *nv_nvkms_memory,
+    uint64_t size)
+{
+    if (!nv_dev->hasVideoMemory) {
+        return 0;
+    }
+
+    if (!nvKms->mapMemory(nv_dev->pDevice,
+                          pMemory,
+                          NVKMS_KAPI_MAPPING_TYPE_USER,
+                          &nv_nvkms_memory->pPhysicalAddress)) {
+        NV_DRM_DEV_LOG_ERR(
+            nv_dev,
+            "Failed to map NvKmsKapiMemory 0x%p",
+            pMemory);
+        return -ENOMEM;
+    }
+
+    nv_nvkms_memory->pWriteCombinedIORemapAddress = ioremap_wc(
+            (uintptr_t)nv_nvkms_memory->pPhysicalAddress,
+            size);
+
+    if (!nv_nvkms_memory->pWriteCombinedIORemapAddress) {
+        NV_DRM_DEV_LOG_INFO(
+            nv_dev,
+            "Failed to ioremap_wc NvKmsKapiMemory 0x%p",
+            pMemory);
+    }
+
+    nv_nvkms_memory->physically_mapped = true;
+
+    return 0;
+}
+
+static int __nv_drm_gem_map_nvkms_memory_offset(
+    struct nv_drm_device *nv_dev,
+    struct nv_drm_gem_object *nv_gem,
+    uint64_t *offset)
+{
+    struct nv_drm_gem_nvkms_memory *nv_nvkms_memory =
+        to_nv_nvkms_memory(nv_gem);
+
+    if (!nv_nvkms_memory->physically_mapped) {
+        int ret = __nv_drm_gem_nvkms_map(nv_dev,
+                                         nv_nvkms_memory->base.pMemory,
+                                         nv_nvkms_memory,
+                                         nv_nvkms_memory->base.base.size);
+        if (ret) {
+           return ret;
+        }
+    }
+
+    return nv_drm_gem_create_mmap_offset(&nv_nvkms_memory->base, offset);
+}
+
+static struct sg_table *__nv_drm_gem_nvkms_memory_prime_get_sg_table(
+    struct nv_drm_gem_object *nv_gem)
+{
+    struct nv_drm_device *nv_dev = nv_gem->nv_dev;
+    struct nv_drm_gem_nvkms_memory *nv_nvkms_memory =
+        to_nv_nvkms_memory(nv_gem);
+    struct sg_table *sg_table;
+
+    if (nv_nvkms_memory->pages_count == 0) {
+        NV_DRM_DEV_LOG_ERR(
+                nv_dev,
+                "Cannot create sg_table for NvKmsKapiMemory 0x%p",
+                nv_gem->pMemory);
+        return NULL;
+    }
+
+    sg_table = nv_drm_prime_pages_to_sg(nv_dev->dev,
+                                        nv_nvkms_memory->pages,
+                                        nv_nvkms_memory->pages_count);
+
+    return sg_table;
+}
+
+const struct nv_drm_gem_object_funcs nv_gem_nvkms_memory_ops = {
+    .free = __nv_drm_gem_nvkms_memory_free,
+    .prime_dup = __nv_drm_gem_nvkms_prime_dup,
+    .mmap = __nv_drm_gem_nvkms_mmap,
+    .handle_vma_fault = __nv_drm_gem_nvkms_handle_vma_fault,
+    .create_mmap_offset = __nv_drm_gem_map_nvkms_memory_offset,
+    .prime_get_sg_table = __nv_drm_gem_nvkms_memory_prime_get_sg_table,
+};
+
+static int __nv_drm_nvkms_gem_obj_init(
+    struct nv_drm_device *nv_dev,
+    struct nv_drm_gem_nvkms_memory *nv_nvkms_memory,
+    struct NvKmsKapiMemory *pMemory,
+    uint64_t size)
+{
+    NvU64 *pages = NULL;
+    NvU32 numPages = 0;
+
+    nv_nvkms_memory->pPhysicalAddress = NULL;
+    nv_nvkms_memory->pWriteCombinedIORemapAddress = NULL;
+    nv_nvkms_memory->physically_mapped = false;
+
+    if (!nvKms->getMemoryPages(nv_dev->pDevice,
+                               pMemory,
+                               &pages,
+                               &numPages) &&
+        !nv_dev->hasVideoMemory) {
+        /* GetMemoryPages may fail for vidmem allocations,
+         * but it should not fail for sysmem allocations. */
+        NV_DRM_DEV_LOG_ERR(nv_dev,
+            "Failed to get memory pages for NvKmsKapiMemory 0x%p",
+            pMemory);
+        return -ENOMEM;
+    }
+    nv_nvkms_memory->pages_count = numPages;
+    nv_nvkms_memory->pages = (struct page **)pages;
+
+    nv_drm_gem_object_init(nv_dev,
+                           &nv_nvkms_memory->base,
+                           &nv_gem_nvkms_memory_ops,
+                           size,
+                           pMemory);
+
+    return 0;
+}
+
+int nv_drm_dumb_create(
+    struct drm_file *file_priv,
+    struct drm_device *dev, struct drm_mode_create_dumb *args)
+{
+    struct nv_drm_device *nv_dev = to_nv_device(dev);
+    struct nv_drm_gem_nvkms_memory *nv_nvkms_memory;
+    uint8_t compressible = 0;
+    struct NvKmsKapiMemory *pMemory;
+    int ret = 0;
+
+    args->pitch = roundup(args->width * ((args->bpp + 7) >> 3),
+                          nv_dev->pitchAlignment);
+
+    args->size = args->height * args->pitch;
+
+    /* Core DRM requires gem object size to be aligned with PAGE_SIZE */
+
+    args->size = roundup(args->size, PAGE_SIZE);
+
+    if ((nv_nvkms_memory =
+            nv_drm_calloc(1, sizeof(*nv_nvkms_memory))) == NULL) {
+        ret = -ENOMEM;
+        goto fail;
+    }
+
+    if (nv_dev->hasVideoMemory) {
+        pMemory = nvKms->allocateVideoMemory(nv_dev->pDevice,
+                                             NvKmsSurfaceMemoryLayoutPitch,
+                                             NVKMS_KAPI_ALLOCATION_TYPE_SCANOUT,
+                                             args->size,
+                                             &compressible);
+    } else {
+        pMemory = nvKms->allocateSystemMemory(nv_dev->pDevice,
+                                              NvKmsSurfaceMemoryLayoutPitch,
+                                              NVKMS_KAPI_ALLOCATION_TYPE_SCANOUT,
+                                              args->size,
+                                              &compressible);
+    }
+
+    if (pMemory == NULL) {
+        ret = -ENOMEM;
+        NV_DRM_DEV_LOG_ERR(
+            nv_dev,
+            "Failed to allocate NvKmsKapiMemory for dumb object of size %llu",
+            args->size);
+        goto nvkms_alloc_memory_failed;
+    }
+
+    ret = __nv_drm_nvkms_gem_obj_init(nv_dev, nv_nvkms_memory, pMemory, args->size);
+    if (ret) {
+        goto nvkms_gem_obj_init_failed;
+    }
+
+    /* Always map dumb buffer memory up front.  Clients are only expected
+     * to use dumb buffers for software rendering, so they're not much use
+     * without a CPU mapping.
+     */
+    ret = __nv_drm_gem_nvkms_map(nv_dev, pMemory, nv_nvkms_memory, args->size);
+    if (ret) {
+        nv_drm_gem_object_unreference_unlocked(&nv_nvkms_memory->base);
+        goto fail;
+    }
+
+    return nv_drm_gem_handle_create_drop_reference(file_priv,
+                                                   &nv_nvkms_memory->base,
+                                                   &args->handle);
+
+nvkms_gem_obj_init_failed:
+    nvKms->freeMemory(nv_dev->pDevice, pMemory);
+
+nvkms_alloc_memory_failed:
+    nv_drm_free(nv_nvkms_memory);
+
+fail:
+    return ret;
+}
+
+int nv_drm_gem_import_nvkms_memory_ioctl(struct drm_device *dev,
+                                         void *data, struct drm_file *filep)
+{
+    struct nv_drm_device *nv_dev = to_nv_device(dev);
+    struct drm_nvidia_gem_import_nvkms_memory_params *p = data;
+    struct nv_drm_gem_nvkms_memory *nv_nvkms_memory;
+    struct NvKmsKapiMemory *pMemory;
+    int ret;
+
+    if (!drm_core_check_feature(dev, DRIVER_MODESET)) {
+        ret = -EINVAL;
+        goto failed;
+    }
+
+    if ((nv_nvkms_memory =
+            nv_drm_calloc(1, sizeof(*nv_nvkms_memory))) == NULL) {
+        ret = -ENOMEM;
+        goto failed;
+    }
+
+    pMemory = nvKms->importMemory(nv_dev->pDevice,
+                                  p->mem_size,
+                                  p->nvkms_params_ptr,
+                                  p->nvkms_params_size);
+
+    if (pMemory == NULL) {
+        ret = -EINVAL;
+        NV_DRM_DEV_LOG_ERR(
+            nv_dev,
+            "Failed to import NVKMS memory to GEM object");
+        goto nvkms_import_memory_failed;
+    }
+
+    ret = __nv_drm_nvkms_gem_obj_init(nv_dev, nv_nvkms_memory, pMemory, p->mem_size);
+    if (ret) {
+        goto nvkms_gem_obj_init_failed;
+    }
+
+    return nv_drm_gem_handle_create_drop_reference(filep,
+                                                   &nv_nvkms_memory->base,
+                                                   &p->handle);
+nvkms_gem_obj_init_failed:
+    nvKms->freeMemory(nv_dev->pDevice, pMemory);
+
+nvkms_import_memory_failed:
+    nv_drm_free(nv_nvkms_memory);
+
+failed:
+    return ret;
+}
+
+int nv_drm_gem_export_nvkms_memory_ioctl(struct drm_device *dev,
+                                         void *data, struct drm_file *filep)
+{
+    struct nv_drm_device *nv_dev = to_nv_device(dev);
+    struct drm_nvidia_gem_export_nvkms_memory_params *p = data;
+    struct nv_drm_gem_nvkms_memory *nv_nvkms_memory = NULL;
+    int ret = 0;
+
+    if (!drm_core_check_feature(dev, DRIVER_MODESET)) {
+        ret = -EINVAL;
+        goto done;
+    }
+
+    if (p->__pad != 0) {
+        ret = -EINVAL;
+        NV_DRM_DEV_LOG_ERR(nv_dev, "Padding fields must be zeroed");
+        goto done;
+    }
+
+    if ((nv_nvkms_memory = nv_drm_gem_object_nvkms_memory_lookup(
+                    dev,
+                    filep,
+                    p->handle)) == NULL) {
+        ret = -EINVAL;
+        NV_DRM_DEV_LOG_ERR(
+            nv_dev,
+            "Failed to lookup NVKMS gem object for export: 0x%08x",
+            p->handle);
+        goto done;
+    }
+
+    if (!nvKms->exportMemory(nv_dev->pDevice,
+                             nv_nvkms_memory->base.pMemory,
+                             p->nvkms_params_ptr,
+                             p->nvkms_params_size)) {
+        ret = -EINVAL;
+        NV_DRM_DEV_LOG_ERR(
+            nv_dev,
+            "Failed to export memory from NVKMS GEM object: 0x%08x", p->handle);
+        goto done;
+    }
+
+done:
+    if (nv_nvkms_memory != NULL) {
+        nv_drm_gem_object_unreference_unlocked(&nv_nvkms_memory->base);
+    }
+
+    return ret;
+}
+
+int nv_drm_gem_alloc_nvkms_memory_ioctl(struct drm_device *dev,
+                                        void *data, struct drm_file *filep)
+{
+    struct nv_drm_device *nv_dev = to_nv_device(dev);
+    struct drm_nvidia_gem_alloc_nvkms_memory_params *p = data;
+    struct nv_drm_gem_nvkms_memory *nv_nvkms_memory = NULL;
+    struct NvKmsKapiMemory *pMemory;
+    enum NvKmsSurfaceMemoryLayout layout;
+    enum NvKmsKapiAllocationType type;
+    int ret = 0;
+
+    if (!drm_core_check_feature(dev, DRIVER_MODESET)) {
+        ret = -EINVAL;
+        goto failed;
+    }
+
+    if (p->__pad != 0) {
+        NV_DRM_DEV_LOG_ERR(nv_dev, "non-zero value in padding field");
+        goto failed;
+    }
+
+    if ((nv_nvkms_memory =
+            nv_drm_calloc(1, sizeof(*nv_nvkms_memory))) == NULL) {
+        ret = -ENOMEM;
+        goto failed;
+    }
+
+    layout = p->block_linear ?
+        NvKmsSurfaceMemoryLayoutBlockLinear : NvKmsSurfaceMemoryLayoutPitch;
+    type = (p->flags & NV_GEM_ALLOC_NO_SCANOUT) ?
+        NVKMS_KAPI_ALLOCATION_TYPE_OFFSCREEN : NVKMS_KAPI_ALLOCATION_TYPE_SCANOUT;
+
+    if (nv_dev->hasVideoMemory) {
+        pMemory = nvKms->allocateVideoMemory(nv_dev->pDevice,
+                                             layout,
+                                             type,
+                                             p->memory_size,
+                                             &p->compressible);
+    } else {
+        pMemory = nvKms->allocateSystemMemory(nv_dev->pDevice,
+                                              layout,
+                                              type,
+                                              p->memory_size,
+                                              &p->compressible);
+    }
+
+    if (pMemory == NULL) {
+        ret = -EINVAL;
+        NV_DRM_DEV_LOG_ERR(nv_dev,
+                           "Failed to allocate NVKMS memory for GEM object");
+        goto nvkms_alloc_memory_failed;
+    }
+
+    ret = __nv_drm_nvkms_gem_obj_init(nv_dev, nv_nvkms_memory, pMemory,
+                                      p->memory_size);
+    if (ret) {
+        goto nvkms_gem_obj_init_failed;
+    }
+
+    return nv_drm_gem_handle_create_drop_reference(filep,
+                                                   &nv_nvkms_memory->base,
+                                                   &p->handle);
+
+nvkms_gem_obj_init_failed:
+    nvKms->freeMemory(nv_dev->pDevice, pMemory);
+
+nvkms_alloc_memory_failed:
+    nv_drm_free(nv_nvkms_memory);
+
+failed:
+    return ret;
+}
+
+static struct drm_gem_object *__nv_drm_gem_nvkms_prime_dup(
+    struct drm_device *dev,
+    const struct nv_drm_gem_object *nv_gem_src)
+{
+    struct nv_drm_device *nv_dev = to_nv_device(dev);
+    const struct nv_drm_device *nv_dev_src;
+    const struct nv_drm_gem_nvkms_memory *nv_nvkms_memory_src;
+    struct nv_drm_gem_nvkms_memory *nv_nvkms_memory;
+    struct NvKmsKapiMemory *pMemory;
+
+    BUG_ON(nv_gem_src == NULL || nv_gem_src->ops != &nv_gem_nvkms_memory_ops);
+
+    nv_dev_src = to_nv_device(nv_gem_src->base.dev);
+    nv_nvkms_memory_src = to_nv_nvkms_memory_const(nv_gem_src);
+
+    if ((nv_nvkms_memory =
+            nv_drm_calloc(1, sizeof(*nv_nvkms_memory))) == NULL) {
+        return NULL;
+    }
+
+    pMemory = nvKms->dupMemory(nv_dev->pDevice,
+                               nv_dev_src->pDevice, nv_gem_src->pMemory);
+    if (pMemory == NULL) {
+        NV_DRM_DEV_LOG_ERR(
+            nv_dev,
+            "Failed to import NVKMS memory to GEM object");
+        goto nvkms_dup_memory_failed;
+    }
+
+    if (__nv_drm_nvkms_gem_obj_init(nv_dev,
+                                    nv_nvkms_memory,
+                                    pMemory,
+                                    nv_gem_src->base.size)) {
+        goto nvkms_gem_obj_init_failed;
+    }
+
+    return &nv_nvkms_memory->base.base;
+
+nvkms_gem_obj_init_failed:
+    nvKms->freeMemory(nv_dev->pDevice, pMemory);
+
+nvkms_dup_memory_failed:
+    nv_drm_free(nv_nvkms_memory);
+
+    return NULL;
+}
+
+int nv_drm_dumb_map_offset(struct drm_file *file,
+                           struct drm_device *dev, uint32_t handle,
+                           uint64_t *offset)
+{
+    struct nv_drm_device *nv_dev = to_nv_device(dev);
+    struct nv_drm_gem_nvkms_memory *nv_nvkms_memory;
+    int ret = -EINVAL;
+
+    if ((nv_nvkms_memory = nv_drm_gem_object_nvkms_memory_lookup(
+                    dev,
+                    file,
+                    handle)) == NULL) {
+        NV_DRM_DEV_LOG_ERR(
+            nv_dev,
+            "Failed to lookup gem object for mapping: 0x%08x",
+            handle);
+        return ret;
+    }
+
+    ret = __nv_drm_gem_map_nvkms_memory_offset(nv_dev,
+                                               &nv_nvkms_memory->base, offset);
+
+    nv_drm_gem_object_unreference_unlocked(&nv_nvkms_memory->base);
+
+    return ret;
+}
+
+int nv_drm_dumb_destroy(struct drm_file *file,
+                        struct drm_device *dev,
+                        uint32_t handle)
+{
+    return drm_gem_handle_delete(file, handle);
+}
+
+#endif

NVIDIA-kernel-module-source-TempVersion/kernel-open/nvidia-drm/nvidia-drm-gem-nvkms-memory.h

@@ -0,0 +1,110 @@
+/*
+ * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef __NVIDIA_DRM_GEM_NVKMS_MEMORY_H__
+#define __NVIDIA_DRM_GEM_NVKMS_MEMORY_H__
+
+#include "nvidia-drm-conftest.h"
+
+#if defined(NV_DRM_ATOMIC_MODESET_AVAILABLE)
+
+#include "nvidia-drm-gem.h"
+
+struct nv_drm_gem_nvkms_memory {
+    struct nv_drm_gem_object base;
+
+    bool physically_mapped;
+
+    void *pPhysicalAddress;
+    void *pWriteCombinedIORemapAddress;
+
+    struct page **pages;
+    unsigned long pages_count;
+};
+
+extern const struct nv_drm_gem_object_funcs nv_gem_nvkms_memory_ops;
+
+static inline struct nv_drm_gem_nvkms_memory *to_nv_nvkms_memory(
+    struct nv_drm_gem_object *nv_gem)
+{
+    if (nv_gem != NULL) {
+        return container_of(nv_gem, struct nv_drm_gem_nvkms_memory, base);
+    }
+
+    return NULL;
+}
+
+static inline struct nv_drm_gem_nvkms_memory *to_nv_nvkms_memory_const(
+    const struct nv_drm_gem_object *nv_gem)
+{
+    if (nv_gem != NULL) {
+        return container_of(nv_gem, struct nv_drm_gem_nvkms_memory, base);
+    }
+
+    return NULL;
+}
+
+static inline
+struct nv_drm_gem_nvkms_memory *nv_drm_gem_object_nvkms_memory_lookup(
+    struct drm_device *dev,
+    struct drm_file *filp,
+    u32 handle)
+{
+    struct nv_drm_gem_object *nv_gem =
+            nv_drm_gem_object_lookup(dev, filp, handle);
+
+    if (nv_gem != NULL && nv_gem->ops != &nv_gem_nvkms_memory_ops) {
+        nv_drm_gem_object_unreference_unlocked(nv_gem);
+        return NULL;
+    }
+
+    return to_nv_nvkms_memory(nv_gem);
+}
+
+int nv_drm_dumb_create(
+    struct drm_file *file_priv,
+    struct drm_device *dev, struct drm_mode_create_dumb *args);
+
+int nv_drm_gem_import_nvkms_memory_ioctl(struct drm_device *dev,
+                                         void *data, struct drm_file *filep);
+
+int nv_drm_gem_export_nvkms_memory_ioctl(struct drm_device *dev,
+                                         void *data, struct drm_file *filep);
+
+int nv_drm_gem_alloc_nvkms_memory_ioctl(struct drm_device *dev,
+                                        void *data, struct drm_file *filep);
+
+int nv_drm_dumb_map_offset(struct drm_file *file,
+                           struct drm_device *dev, uint32_t handle,
+                           uint64_t *offset);
+
+int nv_drm_dumb_destroy(struct drm_file *file,
+                        struct drm_device *dev,
+                        uint32_t handle);
+
+struct drm_gem_object *nv_drm_gem_nvkms_prime_import(
+    struct drm_device *dev,
+    struct drm_gem_object *gem);
+
+#endif
+
+#endif /* __NVIDIA_DRM_GEM_NVKMS_MEMORY_H__ */

NVIDIA-kernel-module-source-TempVersion/kernel-open/nvidia-drm/nvidia-drm-gem-user-memory.c

@@ -0,0 +1,217 @@
+/*
+ * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#include "nvidia-drm-conftest.h"
+
+#if defined(NV_DRM_AVAILABLE)
+
+#if defined(NV_DRM_DRM_PRIME_H_PRESENT)
+#include <drm/drm_prime.h>
+#endif
+
+#include "nvidia-drm-gem-user-memory.h"
+#include "nvidia-drm-helper.h"
+#include "nvidia-drm-ioctl.h"
+
+#include "linux/dma-buf.h"
+#include "linux/mm.h"
+#include "nv-mm.h"
+
+static inline
+void __nv_drm_gem_user_memory_free(struct nv_drm_gem_object *nv_gem)
+{
+    struct nv_drm_gem_user_memory *nv_user_memory = to_nv_user_memory(nv_gem);
+
+    nv_drm_unlock_user_pages(nv_user_memory->pages_count,
+                             nv_user_memory->pages);
+
+    nv_drm_free(nv_user_memory);
+}
+
+static struct sg_table *__nv_drm_gem_user_memory_prime_get_sg_table(
+    struct nv_drm_gem_object *nv_gem)
+{
+    struct nv_drm_gem_user_memory *nv_user_memory = to_nv_user_memory(nv_gem);
+    struct drm_gem_object *gem = &nv_gem->base;
+
+    return nv_drm_prime_pages_to_sg(gem->dev,
+                                    nv_user_memory->pages,
+                                    nv_user_memory->pages_count);
+}
+
+static void *__nv_drm_gem_user_memory_prime_vmap(
+    struct nv_drm_gem_object *nv_gem)
+{
+    struct nv_drm_gem_user_memory *nv_user_memory = to_nv_user_memory(nv_gem);
+
+    return nv_drm_vmap(nv_user_memory->pages,
+                           nv_user_memory->pages_count);
+}
+
+static void __nv_drm_gem_user_memory_prime_vunmap(
+    struct nv_drm_gem_object *gem,
+    void *address)
+{
+    nv_drm_vunmap(address);
+}
+
+static int __nv_drm_gem_user_memory_mmap(struct nv_drm_gem_object *nv_gem,
+                                         struct vm_area_struct *vma)
+{
+    int ret = drm_gem_mmap_obj(&nv_gem->base,
+                drm_vma_node_size(&nv_gem->base.vma_node) << PAGE_SHIFT, vma);
+
+    if (ret < 0) {
+        return ret;
+    }
+
+    /*
+     * Enforce that user-memory GEM mappings are MAP_SHARED, to prevent COW
+     * with MAP_PRIVATE and VM_MIXEDMAP
+     */
+    if (!(vma->vm_flags & VM_SHARED)) {
+        return -EINVAL;
+    }
+
+    vma->vm_flags &= ~VM_PFNMAP;
+    vma->vm_flags &= ~VM_IO;
+    vma->vm_flags |= VM_MIXEDMAP;
+
+    return 0;
+}
+
+static vm_fault_t __nv_drm_gem_user_memory_handle_vma_fault(
+    struct nv_drm_gem_object *nv_gem,
+    struct vm_area_struct *vma,
+    struct vm_fault *vmf)
+{
+    struct nv_drm_gem_user_memory *nv_user_memory = to_nv_user_memory(nv_gem);
+    unsigned long address = nv_page_fault_va(vmf);
+    struct drm_gem_object *gem = vma->vm_private_data;
+    unsigned long page_offset;
+    vm_fault_t ret;
+
+    page_offset = vmf->pgoff - drm_vma_node_start(&gem->vma_node);
+
+    BUG_ON(page_offset > nv_user_memory->pages_count);
+
+    ret = vm_insert_page(vma, address, nv_user_memory->pages[page_offset]);
+    switch (ret) {
+        case 0:
+        case -EBUSY:
+            /*
+             * EBUSY indicates that another thread already handled
+             * the faulted range.
+             */
+            ret = VM_FAULT_NOPAGE;
+            break;
+        case -ENOMEM:
+            ret = VM_FAULT_OOM;
+            break;
+        default:
+            WARN_ONCE(1, "Unhandled error in %s: %d\n", __FUNCTION__, ret);
+            ret = VM_FAULT_SIGBUS;
+            break;
+    }
+
+    return ret;
+}
+
+static int __nv_drm_gem_user_create_mmap_offset(
+    struct nv_drm_device *nv_dev,
+    struct nv_drm_gem_object *nv_gem,
+    uint64_t *offset)
+{
+    (void)nv_dev;
+    return nv_drm_gem_create_mmap_offset(nv_gem, offset);
+}
+
+const struct nv_drm_gem_object_funcs __nv_gem_user_memory_ops = {
+    .free = __nv_drm_gem_user_memory_free,
+    .prime_get_sg_table = __nv_drm_gem_user_memory_prime_get_sg_table,
+    .prime_vmap = __nv_drm_gem_user_memory_prime_vmap,
+    .prime_vunmap = __nv_drm_gem_user_memory_prime_vunmap,
+    .mmap = __nv_drm_gem_user_memory_mmap,
+    .handle_vma_fault = __nv_drm_gem_user_memory_handle_vma_fault,
+    .create_mmap_offset = __nv_drm_gem_user_create_mmap_offset,
+};
+
+int nv_drm_gem_import_userspace_memory_ioctl(struct drm_device *dev,
+                                             void *data, struct drm_file *filep)
+{
+    struct nv_drm_device *nv_dev = to_nv_device(dev);
+
+    struct drm_nvidia_gem_import_userspace_memory_params *params = data;
+    struct nv_drm_gem_user_memory *nv_user_memory;
+
+    struct page **pages = NULL;
+    unsigned long pages_count = 0;
+
+    int ret = 0;
+
+    if ((params->size % PAGE_SIZE) != 0) {
+        NV_DRM_DEV_LOG_ERR(
+            nv_dev,
+            "Userspace memory 0x%llx size should be in a multiple of page "
+            "size to create a gem object",
+            params->address);
+        return -EINVAL;
+    }
+
+    pages_count = params->size / PAGE_SIZE;
+
+    ret = nv_drm_lock_user_pages(params->address, pages_count, &pages);
+
+    if (ret != 0) {
+        NV_DRM_DEV_LOG_ERR(
+            nv_dev,
+            "Failed to lock user pages for address 0x%llx: %d",
+            params->address, ret);
+        return ret;
+    }
+
+    if ((nv_user_memory =
+            nv_drm_calloc(1, sizeof(*nv_user_memory))) == NULL) {
+        ret = -ENOMEM;
+        goto failed;
+    }
+
+    nv_user_memory->pages = pages;
+    nv_user_memory->pages_count = pages_count;
+
+    nv_drm_gem_object_init(nv_dev,
+                           &nv_user_memory->base,
+                           &__nv_gem_user_memory_ops,
+                           params->size,
+                           NULL /* pMemory */);
+
+    return nv_drm_gem_handle_create_drop_reference(filep,
+                                                   &nv_user_memory->base,
+                                                   &params->handle);
+
+failed:
+    nv_drm_unlock_user_pages(pages_count, pages);
+
+    return ret;
+}
+
+#endif

NVIDIA-kernel-module-source-TempVersion/kernel-open/nvidia-drm/nvidia-drm-gem-user-memory.h

@@ -0,0 +1,72 @@
+/*
+ * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef __NVIDIA_DRM_GEM_USER_MEMORY_H__
+#define __NVIDIA_DRM_GEM_USER_MEMORY_H__
+
+#include "nvidia-drm-conftest.h"
+
+#if defined(NV_DRM_AVAILABLE)
+
+#include "nvidia-drm-gem.h"
+
+struct nv_drm_gem_user_memory {
+    struct nv_drm_gem_object base;
+    struct page **pages;
+    unsigned long pages_count;
+};
+
+extern const struct nv_drm_gem_object_funcs __nv_gem_user_memory_ops;
+
+static inline struct nv_drm_gem_user_memory *to_nv_user_memory(
+    struct nv_drm_gem_object *nv_gem)
+{
+    if (nv_gem != NULL) {
+        return container_of(nv_gem, struct nv_drm_gem_user_memory, base);
+    }
+
+    return NULL;
+}
+
+int nv_drm_gem_import_userspace_memory_ioctl(struct drm_device *dev,
+                                             void *data, struct drm_file *filep);
+
+static inline
+struct nv_drm_gem_user_memory *nv_drm_gem_object_user_memory_lookup(
+    struct drm_device *dev,
+    struct drm_file *filp,
+    u32 handle)
+{
+    struct nv_drm_gem_object *nv_gem =
+            nv_drm_gem_object_lookup(dev, filp, handle);
+
+    if (nv_gem != NULL && nv_gem->ops != &__nv_gem_user_memory_ops) {
+        nv_drm_gem_object_unreference_unlocked(nv_gem);
+        return NULL;
+    }
+
+    return to_nv_user_memory(nv_gem);
+}
+
+#endif
+
+#endif /* __NVIDIA_DRM_GEM_USER_MEMORY_H__ */

NVIDIA-kernel-module-source-TempVersion/kernel-open/nvidia-drm/nvidia-drm-gem.c

@@ -0,0 +1,399 @@
+/*
+ * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#include "nvidia-drm-conftest.h"
+
+#if defined(NV_DRM_AVAILABLE)
+
+#include "nvidia-drm-priv.h"
+#include "nvidia-drm-ioctl.h"
+#include "nvidia-drm-prime-fence.h"
+#include "nvidia-drm-gem.h"
+#include "nvidia-drm-gem-nvkms-memory.h"
+#include "nvidia-drm-gem-user-memory.h"
+#include "nvidia-dma-resv-helper.h"
+#include "nvidia-drm-helper.h"
+#include "nvidia-drm-gem-dma-buf.h"
+#include "nvidia-drm-gem-nvkms-memory.h"
+
+#if defined(NV_DRM_DRM_DRV_H_PRESENT)
+#include <drm/drm_drv.h>
+#endif
+
+#if defined(NV_DRM_DRM_PRIME_H_PRESENT)
+#include <drm/drm_prime.h>
+#endif
+
+#if defined(NV_DRM_DRM_FILE_H_PRESENT)
+#include <drm/drm_file.h>
+#endif
+
+#include "linux/dma-buf.h"
+
+#include "nv-mm.h"
+
+void nv_drm_gem_free(struct drm_gem_object *gem)
+{
+    struct nv_drm_gem_object *nv_gem = to_nv_gem_object(gem);
+
+    /* Cleanup core gem object */
+    drm_gem_object_release(&nv_gem->base);
+
+#if defined(NV_DRM_FENCE_AVAILABLE) && !defined(NV_DRM_GEM_OBJECT_HAS_RESV)
+    nv_dma_resv_fini(&nv_gem->resv);
+#endif
+
+    nv_gem->ops->free(nv_gem);
+}
+
+#if !defined(NV_DRM_DRIVER_HAS_GEM_PRIME_CALLBACKS) && \
+    defined(NV_DRM_GEM_OBJECT_VMAP_HAS_MAP_ARG)
+
+/*
+ * The 'dma_buf_map' structure is renamed to 'iosys_map' by the commit
+ * 7938f4218168 ("dma-buf-map: Rename to iosys-map").
+ */
+#if defined(NV_LINUX_IOSYS_MAP_H_PRESENT)
+typedef struct iosys_map nv_sysio_map_t;
+#else
+typedef struct dma_buf_map nv_sysio_map_t;
+#endif
+
+static int nv_drm_gem_vmap(struct drm_gem_object *gem,
+                           nv_sysio_map_t *map)
+{
+    map->vaddr = nv_drm_gem_prime_vmap(gem);
+    if (map->vaddr == NULL) {
+        return -ENOMEM;
+    }
+    map->is_iomem = true;
+    return 0;
+}
+
+static void nv_drm_gem_vunmap(struct drm_gem_object *gem,
+                              nv_sysio_map_t *map)
+{
+    nv_drm_gem_prime_vunmap(gem, map->vaddr);
+    map->vaddr = NULL;
+}
+#endif
+
+#if !defined(NV_DRM_DRIVER_HAS_GEM_FREE_OBJECT) || \
+    !defined(NV_DRM_DRIVER_HAS_GEM_PRIME_CALLBACKS)
+static struct drm_gem_object_funcs nv_drm_gem_funcs = {
+    .free = nv_drm_gem_free,
+    .get_sg_table = nv_drm_gem_prime_get_sg_table,
+
+#if !defined(NV_DRM_DRIVER_HAS_GEM_PRIME_CALLBACKS)
+    .export  = drm_gem_prime_export,
+#if defined(NV_DRM_GEM_OBJECT_VMAP_HAS_MAP_ARG)
+    .vmap    = nv_drm_gem_vmap,
+    .vunmap  = nv_drm_gem_vunmap,
+#else
+    .vmap    = nv_drm_gem_prime_vmap,
+    .vunmap  = nv_drm_gem_prime_vunmap,
+#endif
+    .vm_ops  = &nv_drm_gem_vma_ops,
+#endif
+};
+#endif
+
+void nv_drm_gem_object_init(struct nv_drm_device *nv_dev,
+                            struct nv_drm_gem_object *nv_gem,
+                            const struct nv_drm_gem_object_funcs * const ops,
+                            size_t size,
+                            struct NvKmsKapiMemory *pMemory)
+{
+    struct drm_device *dev = nv_dev->dev;
+
+    nv_gem->nv_dev = nv_dev;
+    nv_gem->ops = ops;
+
+    nv_gem->pMemory = pMemory;
+
+    /* Initialize the gem object */
+
+#if defined(NV_DRM_FENCE_AVAILABLE)
+    nv_dma_resv_init(&nv_gem->resv);
+
+#if defined(NV_DRM_GEM_OBJECT_HAS_RESV)
+    nv_gem->base.resv = &nv_gem->resv;
+#endif
+
+#endif
+
+#if !defined(NV_DRM_DRIVER_HAS_GEM_FREE_OBJECT)
+    nv_gem->base.funcs = &nv_drm_gem_funcs;
+#endif
+
+    drm_gem_private_object_init(dev, &nv_gem->base, size);
+}
+
+struct drm_gem_object *nv_drm_gem_prime_import(struct drm_device *dev,
+                                               struct dma_buf *dma_buf)
+{
+#if defined(NV_DMA_BUF_OWNER_PRESENT)
+    struct drm_gem_object *gem_dst;
+    struct nv_drm_gem_object *nv_gem_src;
+
+    if (dma_buf->owner == dev->driver->fops->owner) {
+        nv_gem_src = to_nv_gem_object(dma_buf->priv);
+
+        if (nv_gem_src->base.dev != dev &&
+            nv_gem_src->ops->prime_dup != NULL) {
+            /*
+             * If we're importing from another NV device, try to handle the
+             * import internally rather than attaching through the dma-buf
+             * mechanisms.  Importing from the same device is even easier,
+             * and drm_gem_prime_import() handles that just fine.
+             */
+            gem_dst = nv_gem_src->ops->prime_dup(dev, nv_gem_src);
+
+            if (gem_dst)
+                return gem_dst;
+        }
+    }
+#endif /* NV_DMA_BUF_OWNER_PRESENT */
+
+    return drm_gem_prime_import(dev, dma_buf);
+}
+
+struct sg_table *nv_drm_gem_prime_get_sg_table(struct drm_gem_object *gem)
+{
+    struct nv_drm_gem_object *nv_gem = to_nv_gem_object(gem);
+
+    if (nv_gem->ops->prime_get_sg_table != NULL) {
+        return nv_gem->ops->prime_get_sg_table(nv_gem);
+    }
+
+    return ERR_PTR(-ENOTSUPP);
+}
+
+void *nv_drm_gem_prime_vmap(struct drm_gem_object *gem)
+{
+    struct nv_drm_gem_object *nv_gem = to_nv_gem_object(gem);
+
+    if (nv_gem->ops->prime_vmap != NULL) {
+        return nv_gem->ops->prime_vmap(nv_gem);
+    }
+
+    return ERR_PTR(-ENOTSUPP);
+}
+
+void nv_drm_gem_prime_vunmap(struct drm_gem_object *gem, void *address)
+{
+    struct nv_drm_gem_object *nv_gem = to_nv_gem_object(gem);
+
+    if (nv_gem->ops->prime_vunmap != NULL) {
+        nv_gem->ops->prime_vunmap(nv_gem, address);
+    }
+}
+
+#if defined(NV_DRM_DRIVER_HAS_GEM_PRIME_RES_OBJ)
+nv_dma_resv_t* nv_drm_gem_prime_res_obj(struct drm_gem_object *obj)
+{
+    struct nv_drm_gem_object *nv_gem = to_nv_gem_object(obj);
+
+    return &nv_gem->resv;
+}
+#endif
+
+int nv_drm_gem_map_offset_ioctl(struct drm_device *dev,
+                                void *data, struct drm_file *filep)
+{
+    struct nv_drm_device *nv_dev = to_nv_device(dev);
+    struct drm_nvidia_gem_map_offset_params *params = data;
+    struct nv_drm_gem_object *nv_gem;
+    int ret;
+
+    if ((nv_gem = nv_drm_gem_object_lookup(dev,
+                                           filep,
+                                           params->handle)) == NULL) {
+        NV_DRM_DEV_LOG_ERR(
+            nv_dev,
+            "Failed to lookup gem object for map: 0x%08x",
+            params->handle);
+        return -EINVAL;
+    }
+
+    if (nv_gem->ops->create_mmap_offset) {
+        ret = nv_gem->ops->create_mmap_offset(nv_dev, nv_gem, &params->offset);
+    } else {
+        NV_DRM_DEV_LOG_ERR(
+            nv_dev,
+            "Gem object type does not support mapping: 0x%08x",
+            params->handle);
+        ret = -EINVAL;
+    }
+
+    nv_drm_gem_object_unreference_unlocked(nv_gem);
+
+    return ret;
+}
+
+#if defined(NV_DRM_ATOMIC_MODESET_AVAILABLE)
+int nv_drm_mmap(struct file *file, struct vm_area_struct *vma)
+{
+    struct drm_file *priv = file->private_data;
+    struct drm_device *dev = priv->minor->dev;
+    struct drm_gem_object *obj = NULL;
+    struct drm_vma_offset_node *node;
+    int ret = 0;
+    struct nv_drm_gem_object *nv_gem;
+
+    drm_vma_offset_lock_lookup(dev->vma_offset_manager);
+    node = nv_drm_vma_offset_exact_lookup_locked(dev->vma_offset_manager,
+                                                 vma->vm_pgoff, vma_pages(vma));
+    if (likely(node)) {
+        obj = container_of(node, struct drm_gem_object, vma_node);
+        /*
+         * When the object is being freed, after it hits 0-refcnt it proceeds
+         * to tear down the object. In the process it will attempt to remove
+         * the VMA offset and so acquire this mgr->vm_lock.  Therefore if we
+         * find an object with a 0-refcnt that matches our range, we know it is
+         * in the process of being destroyed and will be freed as soon as we
+         * release the lock - so we have to check for the 0-refcnted object and
+         * treat it as invalid.
+         */
+        if (!kref_get_unless_zero(&obj->refcount))
+            obj = NULL;
+    }
+    drm_vma_offset_unlock_lookup(dev->vma_offset_manager);
+
+    if (!obj)
+        return -EINVAL;
+
+    nv_gem = to_nv_gem_object(obj);
+    if (nv_gem->ops->mmap == NULL) {
+        ret = -EINVAL;
+        goto done;
+    }
+
+    if (!nv_drm_vma_node_is_allowed(node, file)) {
+        ret = -EACCES;
+        goto done;
+    }
+
+#if defined(NV_DRM_VMA_OFFSET_NODE_HAS_READONLY)
+    if (node->readonly) {
+        if (vma->vm_flags & VM_WRITE) {
+            ret = -EINVAL;
+            goto done;
+        }
+        vma->vm_flags &= ~VM_MAYWRITE;
+    }
+#endif
+
+    ret = nv_gem->ops->mmap(nv_gem, vma);
+
+done:
+    nv_drm_gem_object_unreference_unlocked(nv_gem);
+
+    return ret;
+}
+#endif
+
+int nv_drm_gem_identify_object_ioctl(struct drm_device *dev,
+                                     void *data, struct drm_file *filep)
+{
+    struct drm_nvidia_gem_identify_object_params *p = data;
+    struct nv_drm_gem_dma_buf *nv_dma_buf;
+    struct nv_drm_gem_nvkms_memory *nv_nvkms_memory;
+    struct nv_drm_gem_user_memory *nv_user_memory;
+    struct nv_drm_gem_object *nv_gem = NULL;
+
+    if (!drm_core_check_feature(dev, DRIVER_MODESET)) {
+        return -EINVAL;
+    }
+
+    nv_dma_buf = nv_drm_gem_object_dma_buf_lookup(dev, filep, p->handle);
+    if (nv_dma_buf) {
+        p->object_type = NV_GEM_OBJECT_DMABUF;
+        nv_gem = &nv_dma_buf->base;
+        goto done;
+    }
+
+#if defined(NV_DRM_ATOMIC_MODESET_AVAILABLE)
+    nv_nvkms_memory = nv_drm_gem_object_nvkms_memory_lookup(dev, filep, p->handle);
+    if (nv_nvkms_memory) {
+        p->object_type = NV_GEM_OBJECT_NVKMS;
+        nv_gem = &nv_nvkms_memory->base;
+        goto done;
+    }
+#endif
+
+    nv_user_memory = nv_drm_gem_object_user_memory_lookup(dev, filep, p->handle);
+    if (nv_user_memory) {
+        p->object_type = NV_GEM_OBJECT_USERMEMORY;
+        nv_gem = &nv_user_memory->base;
+        goto done;
+    }
+
+    p->object_type = NV_GEM_OBJECT_UNKNOWN;
+
+done:
+    if (nv_gem) {
+        nv_drm_gem_object_unreference_unlocked(nv_gem);
+    }
+    return 0;
+}
+
+/* XXX Move these vma operations to os layer */
+
+static vm_fault_t __nv_drm_vma_fault(struct vm_area_struct *vma,
+                              struct vm_fault *vmf)
+{
+    struct drm_gem_object *gem = vma->vm_private_data;
+    struct nv_drm_gem_object *nv_gem = to_nv_gem_object(gem);
+
+    if (!nv_gem) {
+        return VM_FAULT_SIGBUS;
+    }
+
+    return nv_gem->ops->handle_vma_fault(nv_gem, vma, vmf);
+}
+
+/*
+ * Note that nv_drm_vma_fault() can be called for different or same
+ * ranges of the same drm_gem_object simultaneously.
+ */
+
+#if defined(NV_VM_OPS_FAULT_REMOVED_VMA_ARG)
+static vm_fault_t nv_drm_vma_fault(struct vm_fault *vmf)
+{
+    return __nv_drm_vma_fault(vmf->vma, vmf);
+}
+#else
+static vm_fault_t nv_drm_vma_fault(struct vm_area_struct *vma,
+                                struct vm_fault *vmf)
+{
+    return __nv_drm_vma_fault(vma, vmf);
+}
+#endif
+
+const struct vm_operations_struct nv_drm_gem_vma_ops = {
+    .open  = drm_gem_vm_open,
+    .fault = nv_drm_vma_fault,
+    .close = drm_gem_vm_close,
+};
+
+#endif /* NV_DRM_AVAILABLE */

NVIDIA-kernel-module-source-TempVersion/kernel-open/nvidia-drm/nvidia-drm-gem.h

@@ -0,0 +1,211 @@
+/*
+ * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef __NVIDIA_DRM_GEM_H__
+#define __NVIDIA_DRM_GEM_H__
+
+#include "nvidia-drm-conftest.h"
+
+#if defined(NV_DRM_AVAILABLE)
+
+#include "nvidia-drm-priv.h"
+
+#if defined(NV_DRM_DRMP_H_PRESENT)
+#include <drm/drmP.h>
+#endif
+
+#if defined(NV_DRM_DRM_GEM_H_PRESENT)
+#include <drm/drm_gem.h>
+#endif
+
+#include "nvkms-kapi.h"
+#include "nv-mm.h"
+
+#if defined(NV_DRM_FENCE_AVAILABLE)
+#include "nvidia-dma-fence-helper.h"
+#include "nvidia-dma-resv-helper.h"
+#endif
+
+struct nv_drm_gem_object;
+
+struct nv_drm_gem_object_funcs {
+    void (*free)(struct nv_drm_gem_object *nv_gem);
+    struct sg_table *(*prime_get_sg_table)(struct nv_drm_gem_object *nv_gem);
+    void *(*prime_vmap)(struct nv_drm_gem_object *nv_gem);
+    void (*prime_vunmap)(struct nv_drm_gem_object *nv_gem, void *address);
+    struct drm_gem_object *(*prime_dup)(struct drm_device *dev,
+                                        const struct nv_drm_gem_object *nv_gem_src);
+    int (*mmap)(struct nv_drm_gem_object *nv_gem, struct vm_area_struct *vma);
+    vm_fault_t (*handle_vma_fault)(struct nv_drm_gem_object *nv_gem,
+                                   struct vm_area_struct *vma,
+                                   struct vm_fault *vmf);
+    int (*create_mmap_offset)(struct nv_drm_device *nv_dev,
+                              struct nv_drm_gem_object *nv_gem,
+                              uint64_t *offset);
+};
+
+struct nv_drm_gem_object {
+    struct drm_gem_object base;
+
+    struct nv_drm_device *nv_dev;
+    const struct nv_drm_gem_object_funcs *ops;
+
+    struct NvKmsKapiMemory *pMemory;
+
+#if defined(NV_DRM_FENCE_AVAILABLE)
+    nv_dma_resv_t  resv;
+#endif
+};
+
+static inline struct nv_drm_gem_object *to_nv_gem_object(
+    struct drm_gem_object *gem)
+{
+    if (gem != NULL) {
+        return container_of(gem, struct nv_drm_gem_object, base);
+    }
+
+    return NULL;
+}
+
+/*
+ * drm_gem_object_{get/put}() added by commit
+ * e6b62714e87c8811d5564b6a0738dcde63a51774 (2017-02-28) and
+ * drm_gem_object_{reference/unreference}() removed by commit
+ * 3e70fd160cf0b1945225eaa08dd2cb8544f21cb8 (2018-11-15).
+ */
+
+static inline void
+nv_drm_gem_object_unreference_unlocked(struct nv_drm_gem_object *nv_gem)
+{
+#if defined(NV_DRM_GEM_OBJECT_GET_PRESENT)
+
+#if defined(NV_DRM_GEM_OBJECT_PUT_UNLOCK_PRESENT)
+    drm_gem_object_put_unlocked(&nv_gem->base);
+#else
+    drm_gem_object_put(&nv_gem->base);
+#endif
+
+#else
+    drm_gem_object_unreference_unlocked(&nv_gem->base);
+#endif
+}
+
+static inline void
+nv_drm_gem_object_unreference(struct nv_drm_gem_object *nv_gem)
+{
+#if defined(NV_DRM_GEM_OBJECT_GET_PRESENT)
+    drm_gem_object_put(&nv_gem->base);
+#else
+    drm_gem_object_unreference(&nv_gem->base);
+#endif
+}
+
+static inline int nv_drm_gem_handle_create_drop_reference(
+    struct drm_file *file_priv,
+    struct nv_drm_gem_object *nv_gem,
+    uint32_t *handle)
+{
+    int ret = drm_gem_handle_create(file_priv, &nv_gem->base, handle);
+
+    /* drop reference from allocate - handle holds it now */
+
+    nv_drm_gem_object_unreference_unlocked(nv_gem);
+
+    return ret;
+}
+
+static inline int nv_drm_gem_create_mmap_offset(
+    struct nv_drm_gem_object *nv_gem,
+    uint64_t *offset)
+{
+    int ret;
+
+    if ((ret = drm_gem_create_mmap_offset(&nv_gem->base)) < 0) {
+        NV_DRM_DEV_LOG_ERR(
+            nv_gem->nv_dev,
+            "drm_gem_create_mmap_offset failed with error code %d",
+            ret);
+        goto done;
+    }
+
+    *offset = drm_vma_node_offset_addr(&nv_gem->base.vma_node);
+
+done:
+
+    return ret;
+}
+
+void nv_drm_gem_free(struct drm_gem_object *gem);
+
+static inline struct nv_drm_gem_object *nv_drm_gem_object_lookup(
+    struct drm_device *dev,
+    struct drm_file *filp,
+    u32 handle)
+{
+#if (NV_DRM_GEM_OBJECT_LOOKUP_ARGUMENT_COUNT == 3)
+    return to_nv_gem_object(drm_gem_object_lookup(dev, filp, handle));
+#elif (NV_DRM_GEM_OBJECT_LOOKUP_ARGUMENT_COUNT == 2)
+    return to_nv_gem_object(drm_gem_object_lookup(filp, handle));
+#else
+    #error "Unknown argument count of drm_gem_object_lookup()"
+#endif
+}
+
+static inline int nv_drm_gem_handle_create(struct drm_file *filp,
+                                           struct nv_drm_gem_object *nv_gem,
+                                           uint32_t *handle)
+{
+    return drm_gem_handle_create(filp, &nv_gem->base, handle);
+}
+
+void nv_drm_gem_object_init(struct nv_drm_device *nv_dev,
+                            struct nv_drm_gem_object *nv_gem,
+                            const struct nv_drm_gem_object_funcs * const ops,
+                            size_t size,
+                            struct NvKmsKapiMemory *pMemory);
+
+struct drm_gem_object *nv_drm_gem_prime_import(struct drm_device *dev,
+                                               struct dma_buf *dma_buf);
+
+struct sg_table *nv_drm_gem_prime_get_sg_table(struct drm_gem_object *gem);
+
+void *nv_drm_gem_prime_vmap(struct drm_gem_object *gem);
+
+void nv_drm_gem_prime_vunmap(struct drm_gem_object *gem, void *address);
+
+#if defined(NV_DRM_DRIVER_HAS_GEM_PRIME_RES_OBJ)
+nv_dma_resv_t* nv_drm_gem_prime_res_obj(struct drm_gem_object *obj);
+#endif
+
+extern const struct vm_operations_struct nv_drm_gem_vma_ops;
+
+int nv_drm_gem_map_offset_ioctl(struct drm_device *dev,
+                                void *data, struct drm_file *filep);
+
+int nv_drm_mmap(struct file *file, struct vm_area_struct *vma);
+
+int nv_drm_gem_identify_object_ioctl(struct drm_device *dev,
+                                     void *data, struct drm_file *filep);
+
+#endif /* NV_DRM_AVAILABLE */
+
+#endif /* __NVIDIA_DRM_GEM_H__ */

NVIDIA-kernel-module-source-TempVersion/kernel-open/nvidia-drm/nvidia-drm-helper.c

@@ -0,0 +1,204 @@
+/*
+ * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+/*
+ * This file contains snapshots of DRM helper functions from the
+ * Linux kernel which are used by nvidia-drm.ko if the target kernel
+ * predates the helper function.  Having these functions consistently
+ * present simplifies nvidia-drm.ko source.
+ */
+
+#include "nvidia-drm-helper.h"
+
+#include "nvmisc.h"
+
+#if defined(NV_DRM_ATOMIC_MODESET_AVAILABLE)
+
+#if defined(NV_DRM_DRMP_H_PRESENT)
+#include <drm/drmP.h>
+#endif
+
+#if defined(NV_DRM_DRM_ATOMIC_UAPI_H_PRESENT)
+#include <drm/drm_atomic_uapi.h>
+#endif
+
+/*
+ * The inclusion of drm_framebuffer.h was removed from drm_crtc.h by commit
+ * 720cf96d8fecde29b72e1101f8a567a0ce99594f ("drm: Drop drm_framebuffer.h from
+ * drm_crtc.h") in linux-next, expected in v5.19-rc7.
+ *
+ * We only need drm_framebuffer.h for drm_framebuffer_put(), and it is always
+ * present (v4.9+) when drm_framebuffer_{put,get}() is present (v4.12+), so it
+ * is safe to unconditionally include it when drm_framebuffer_get() is present.
+ */
+#if defined(NV_DRM_FRAMEBUFFER_GET_PRESENT)
+#include <drm/drm_framebuffer.h>
+#endif
+
+static void __nv_drm_framebuffer_put(struct drm_framebuffer *fb)
+{
+#if defined(NV_DRM_FRAMEBUFFER_GET_PRESENT)
+    drm_framebuffer_put(fb);
+#else
+    drm_framebuffer_unreference(fb);
+#endif
+
+}
+
+/*
+ * drm_atomic_helper_disable_all() has been added by commit
+ * 1494276000db789c6d2acd85747be4707051c801, which is Signed-off-by:
+ *     Thierry Reding <treding@nvidia.com>
+ *     Daniel Vetter <daniel.vetter@ffwll.ch>
+ *
+ * drm_atomic_helper_disable_all() is copied from
+ * linux/drivers/gpu/drm/drm_atomic_helper.c and modified to use
+ * nv_drm_for_each_crtc instead of drm_for_each_crtc to loop over all crtcs,
+ * use nv_drm_for_each_*_in_state instead of for_each_connector_in_state to loop
+ * over all modeset object states, and use drm_atomic_state_free() if
+ * drm_atomic_state_put() is not available.
+ *
+ * drm_atomic_helper_disable_all() is copied from
+ *     linux/drivers/gpu/drm/drm_atomic_helper.c @
+ *     49d70aeaeca8f62b72b7712ecd1e29619a445866, which has the following
+ * copyright and license information:
+ *
+ * Copyright (C) 2014 Red Hat
+ * Copyright (C) 2014 Intel Corp.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors:
+ * Rob Clark <robdclark@gmail.com>
+ * Daniel Vetter <daniel.vetter@ffwll.ch>
+ */
+int nv_drm_atomic_helper_disable_all(struct drm_device *dev,
+                                     struct drm_modeset_acquire_ctx *ctx)
+{
+    struct drm_atomic_state *state;
+    struct drm_connector_state *conn_state;
+    struct drm_connector *conn;
+    struct drm_plane_state *plane_state;
+    struct drm_plane *plane;
+    struct drm_crtc_state *crtc_state;
+    struct drm_crtc *crtc;
+    unsigned plane_mask = 0;
+    int ret, i;
+
+    state = drm_atomic_state_alloc(dev);
+    if (!state)
+        return -ENOMEM;
+
+    state->acquire_ctx = ctx;
+
+    nv_drm_for_each_crtc(crtc, dev) {
+        crtc_state = drm_atomic_get_crtc_state(state, crtc);
+        if (IS_ERR(crtc_state)) {
+            ret = PTR_ERR(crtc_state);
+            goto free;
+        }
+
+        crtc_state->active = false;
+
+        ret = drm_atomic_set_mode_prop_for_crtc(crtc_state, NULL);
+        if (ret < 0)
+            goto free;
+
+        ret = drm_atomic_add_affected_planes(state, crtc);
+        if (ret < 0)
+            goto free;
+
+        ret = drm_atomic_add_affected_connectors(state, crtc);
+        if (ret < 0)
+            goto free;
+    }
+
+    nv_drm_for_each_connector_in_state(state, conn, conn_state, i) {
+        ret = drm_atomic_set_crtc_for_connector(conn_state, NULL);
+        if (ret < 0)
+            goto free;
+    }
+
+    nv_drm_for_each_plane_in_state(state, plane, plane_state, i) {
+        ret = drm_atomic_set_crtc_for_plane(plane_state, NULL);
+        if (ret < 0)
+            goto free;
+
+        drm_atomic_set_fb_for_plane(plane_state, NULL);
+        plane_mask |= NVBIT(drm_plane_index(plane));
+        plane->old_fb = plane->fb;
+    }
+
+    ret = drm_atomic_commit(state);
+free:
+    if (plane_mask) {
+        drm_for_each_plane_mask(plane, dev, plane_mask) {
+            if (ret == 0) {
+                plane->fb = NULL;
+                plane->crtc = NULL;
+
+                WARN_ON(plane->state->fb);
+                WARN_ON(plane->state->crtc);
+
+                if (plane->old_fb)
+                    __nv_drm_framebuffer_put(plane->old_fb);
+           }
+           plane->old_fb = NULL;
+       }
+    }
+
+#if defined(NV_DRM_ATOMIC_STATE_REF_COUNTING_PRESENT)
+    drm_atomic_state_put(state);
+#else
+    if (ret != 0) {
+        drm_atomic_state_free(state);
+    } else {
+        /*
+         * In case of success, drm_atomic_commit() takes care to cleanup and
+         * free @state.
+         *
+         * Comment placed above drm_atomic_commit() says: The caller must not
+         * free or in any other way access @state. If the function fails then
+         * the caller must clean up @state itself.
+         */
+    }
+#endif
+    return ret;
+}
+
+#endif /* NV_DRM_ATOMIC_MODESET_AVAILABLE */

NVIDIA-kernel-module-source-TempVersion/kernel-open/nvidia-drm/nvidia-drm-helper.h

@@ -0,0 +1,584 @@
+/*
+ * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef __NVIDIA_DRM_HELPER_H__
+#define __NVIDIA_DRM_HELPER_H__
+
+#include "nvidia-drm-conftest.h"
+
+#if defined(NV_DRM_AVAILABLE)
+
+#if defined(NV_DRM_DRMP_H_PRESENT)
+#include <drm/drmP.h>
+#endif
+
+#if defined(NV_DRM_DRM_DRV_H_PRESENT)
+#include <drm/drm_drv.h>
+#endif
+
+/*
+ * drm_dev_put() is added by commit 9a96f55034e41b4e002b767e9218d55f03bdff7d
+ * (2017-09-26) and drm_dev_unref() is removed by
+ * ba1d345401476a5f7fbad622607c5a1f95e59b31 (2018-11-15).
+ *
+ * drm_dev_unref() has been added and drm_dev_free() removed by commit -
+ *
+ *      2014-01-29: 099d1c290e2ebc3b798961a6c177c3aef5f0b789
+ */
+static inline void nv_drm_dev_free(struct drm_device *dev)
+{
+#if defined(NV_DRM_DEV_PUT_PRESENT)
+    drm_dev_put(dev);
+#elif defined(NV_DRM_DEV_UNREF_PRESENT)
+    drm_dev_unref(dev);
+#else
+    drm_dev_free(dev);
+#endif
+}
+
+#if defined(NV_DRM_DRM_PRIME_H_PRESENT)
+#include <drm/drm_prime.h>
+#endif
+
+static inline struct sg_table*
+nv_drm_prime_pages_to_sg(struct drm_device *dev,
+                         struct page **pages, unsigned int nr_pages)
+{
+#if defined(NV_DRM_PRIME_PAGES_TO_SG_HAS_DRM_DEVICE_ARG)
+    return drm_prime_pages_to_sg(dev, pages, nr_pages);
+#else
+    return drm_prime_pages_to_sg(pages, nr_pages);
+#endif
+}
+
+#if defined(NV_DRM_ATOMIC_MODESET_AVAILABLE)
+
+/*
+ * drm_for_each_connector(), drm_for_each_crtc(), drm_for_each_fb(),
+ * drm_for_each_encoder and drm_for_each_plane() were added by kernel
+ * commit 6295d607ad34ee4e43aab3f20714c2ef7a6adea1 which was
+ * Signed-off-by:
+ *     Daniel Vetter <daniel.vetter@intel.com>
+ * drm_for_each_connector(), drm_for_each_crtc(), drm_for_each_fb(),
+ * drm_for_each_encoder and drm_for_each_plane() are copied from
+ *      include/drm/drm_crtc @
+ *      6295d607ad34ee4e43aab3f20714c2ef7a6adea1
+ * which has the following copyright and license information:
+ *
+ * Copyright © 2006 Keith Packard
+ * Copyright © 2007-2008 Dave Airlie
+ * Copyright © 2007-2008 Intel Corporation
+ *   Jesse Barnes <jesse.barnes@intel.com>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+#include <drm/drm_crtc.h>
+
+#if defined(drm_for_each_plane)
+#define nv_drm_for_each_plane(plane, dev) \
+    drm_for_each_plane(plane, dev)
+#else
+#define nv_drm_for_each_plane(plane, dev) \
+    list_for_each_entry(plane, &(dev)->mode_config.plane_list, head)
+#endif
+
+#if defined(drm_for_each_crtc)
+#define nv_drm_for_each_crtc(crtc, dev) \
+    drm_for_each_crtc(crtc, dev)
+#else
+#define nv_drm_for_each_crtc(crtc, dev) \
+    list_for_each_entry(crtc, &(dev)->mode_config.crtc_list, head)
+#endif
+
+#if defined(NV_DRM_CONNECTOR_LIST_ITER_PRESENT)
+#define nv_drm_for_each_connector(connector, conn_iter, dev) \
+        drm_for_each_connector_iter(connector, conn_iter)
+#elif defined(drm_for_each_connector)
+#define nv_drm_for_each_connector(connector, conn_iter, dev) \
+    drm_for_each_connector(connector, dev)
+#else
+#define nv_drm_for_each_connector(connector, conn_iter, dev) \
+    WARN_ON(!mutex_is_locked(&dev->mode_config.mutex));      \
+    list_for_each_entry(connector, &(dev)->mode_config.connector_list, head)
+#endif
+
+#if defined(drm_for_each_encoder)
+#define nv_drm_for_each_encoder(encoder, dev) \
+    drm_for_each_encoder(encoder, dev)
+#else
+#define nv_drm_for_each_encoder(encoder, dev) \
+    list_for_each_entry(encoder, &(dev)->mode_config.encoder_list, head)
+#endif
+
+#if defined(drm_for_each_fb)
+#define nv_drm_for_each_fb(fb, dev) \
+    drm_for_each_fb(fb, dev)
+#else
+#define nv_drm_for_each_fb(fb, dev) \
+    list_for_each_entry(fb, &(dev)->mode_config.fb_list, head)
+#endif
+
+#include <drm/drm_atomic.h>
+#include <drm/drm_atomic_helper.h>
+
+int nv_drm_atomic_helper_disable_all(struct drm_device *dev,
+                                     struct drm_modeset_acquire_ctx *ctx);
+
+/*
+ * for_each_connector_in_state(), for_each_crtc_in_state() and
+ * for_each_plane_in_state() were added by kernel commit
+ * df63b9994eaf942afcdb946d27a28661d7dfbf2a which was Signed-off-by:
+ *      Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com>
+ *      Daniel Vetter <daniel.vetter@ffwll.ch>
+ *
+ * for_each_connector_in_state(), for_each_crtc_in_state() and
+ * for_each_plane_in_state() were copied from
+ *      include/drm/drm_atomic.h @
+ *      21a01abbe32a3cbeb903378a24e504bfd9fe0648
+ * which has the following copyright and license information:
+ *
+ * Copyright (C) 2014 Red Hat
+ * Copyright (C) 2014 Intel Corp.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors:
+ * Rob Clark <robdclark@gmail.com>
+ * Daniel Vetter <daniel.vetter@ffwll.ch>
+ */
+
+/**
+ * nv_drm_for_each_connector_in_state - iterate over all connectors in an
+ * atomic update
+ * @__state: &struct drm_atomic_state pointer
+ * @connector: &struct drm_connector iteration cursor
+ * @connector_state: &struct drm_connector_state iteration cursor
+ * @__i: int iteration cursor, for macro-internal use
+ *
+ * This iterates over all connectors in an atomic update. Note that before the
+ * software state is committed (by calling drm_atomic_helper_swap_state(), this
+ * points to the new state, while afterwards it points to the old state. Due to
+ * this tricky confusion this macro is deprecated.
+ */
+#if !defined(for_each_connector_in_state)
+#define nv_drm_for_each_connector_in_state(__state,                         \
+                                           connector, connector_state, __i) \
+       for ((__i) = 0;                                                      \
+            (__i) < (__state)->num_connector &&                             \
+            ((connector) = (__state)->connectors[__i].ptr,                  \
+            (connector_state) = (__state)->connectors[__i].state, 1);       \
+            (__i)++)                                                        \
+               for_each_if (connector)
+#else
+#define nv_drm_for_each_connector_in_state(__state,                         \
+                                           connector, connector_state, __i) \
+    for_each_connector_in_state(__state, connector, connector_state, __i)
+#endif
+
+
+/**
+ * nv_drm_for_each_crtc_in_state - iterate over all CRTCs in an atomic update
+ * @__state: &struct drm_atomic_state pointer
+ * @crtc: &struct drm_crtc iteration cursor
+ * @crtc_state: &struct drm_crtc_state iteration cursor
+ * @__i: int iteration cursor, for macro-internal use
+ *
+ * This iterates over all CRTCs in an atomic update. Note that before the
+ * software state is committed (by calling drm_atomic_helper_swap_state(), this
+ * points to the new state, while afterwards it points to the old state. Due to
+ * this tricky confusion this macro is deprecated.
+ */
+#if !defined(for_each_crtc_in_state)
+#define nv_drm_for_each_crtc_in_state(__state, crtc, crtc_state, __i) \
+       for ((__i) = 0;                                                \
+            (__i) < (__state)->dev->mode_config.num_crtc &&           \
+            ((crtc) = (__state)->crtcs[__i].ptr,                      \
+            (crtc_state) = (__state)->crtcs[__i].state, 1);           \
+            (__i)++)                                                  \
+               for_each_if (crtc_state)
+#else
+#define nv_drm_for_each_crtc_in_state(__state, crtc, crtc_state, __i) \
+    for_each_crtc_in_state(__state, crtc, crtc_state, __i)
+#endif
+
+/**
+ * nv_drm_for_each_plane_in_state - iterate over all planes in an atomic update
+ * @__state: &struct drm_atomic_state pointer
+ * @plane: &struct drm_plane iteration cursor
+ * @plane_state: &struct drm_plane_state iteration cursor
+ * @__i: int iteration cursor, for macro-internal use
+ *
+ * This iterates over all planes in an atomic update. Note that before the
+ * software state is committed (by calling drm_atomic_helper_swap_state(), this
+ * points to the new state, while afterwards it points to the old state. Due to
+ * this tricky confusion this macro is deprecated.
+ */
+#if !defined(for_each_plane_in_state)
+#define nv_drm_for_each_plane_in_state(__state, plane, plane_state, __i) \
+       for ((__i) = 0;                                                   \
+            (__i) < (__state)->dev->mode_config.num_total_plane &&       \
+            ((plane) = (__state)->planes[__i].ptr,                       \
+            (plane_state) = (__state)->planes[__i].state, 1);            \
+            (__i)++)                                                     \
+               for_each_if (plane_state)
+#else
+#define nv_drm_for_each_plane_in_state(__state, plane, plane_state, __i) \
+    for_each_plane_in_state(__state, plane, plane_state, __i)
+#endif
+
+static inline struct drm_crtc *nv_drm_crtc_find(struct drm_device *dev,
+    uint32_t id)
+{
+#if defined(NV_DRM_MODE_OBJECT_FIND_HAS_FILE_PRIV_ARG)
+    return drm_crtc_find(dev, NULL /* file_priv */, id);
+#else
+    return drm_crtc_find(dev, id);
+#endif
+}
+
+static inline struct drm_encoder *nv_drm_encoder_find(struct drm_device *dev,
+    uint32_t id)
+{
+#if defined(NV_DRM_MODE_OBJECT_FIND_HAS_FILE_PRIV_ARG)
+    return drm_encoder_find(dev, NULL /* file_priv */, id);
+#else
+    return drm_encoder_find(dev, id);
+#endif
+}
+
+/*
+ * drm_connector_for_each_possible_encoder() is added by commit
+ * 83aefbb887b59df0b3520965c3701e01deacfc52 which was Signed-off-by:
+ *     Ville Syrjälä <ville.syrjala@linux.intel.com>
+ *
+ * drm_connector_for_each_possible_encoder() is copied from
+ * include/drm/drm_connector.h and modified to use nv_drm_encoder_find()
+ * instead of drm_encoder_find().
+ *
+ * drm_connector_for_each_possible_encoder() is copied from
+ *      include/drm/drm_connector.h @
+ *      83aefbb887b59df0b3520965c3701e01deacfc52
+ * which has the following copyright and license information:
+ *
+ * Copyright (c) 2016 Intel Corporation
+ *
+ * Permission to use, copy, modify, distribute, and sell this software and its
+ * documentation for any purpose is hereby granted without fee, provided that
+ * the above copyright notice appear in all copies and that both that copyright
+ * notice and this permission notice appear in supporting documentation, and
+ * that the name of the copyright holders not be used in advertising or
+ * publicity pertaining to distribution of the software without specific,
+ * written prior permission.  The copyright holders make no representations
+ * about the suitability of this software for any purpose.  It is provided "as
+ * is" without express or implied warranty.
+ *
+ * THE COPYRIGHT HOLDERS DISCLAIM ALL WARRANTIES WITH REGARD TO THIS SOFTWARE,
+ * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO
+ * EVENT SHALL THE COPYRIGHT HOLDERS BE LIABLE FOR ANY SPECIAL, INDIRECT OR
+ * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE,
+ * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
+ * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE
+ * OF THIS SOFTWARE.
+ */
+
+#if defined(NV_DRM_DRM_CONNECTOR_H_PRESENT)
+#include <drm/drm_connector.h>
+#endif
+
+/**
+ * nv_drm_connector_for_each_possible_encoder - iterate connector's possible
+ * encoders
+ * @connector: &struct drm_connector pointer
+ * @encoder: &struct drm_encoder pointer used as cursor
+ * @__i: int iteration cursor, for macro-internal use
+ */
+#if !defined(drm_connector_for_each_possible_encoder)
+
+#if !defined(for_each_if)
+#define for_each_if(condition) if (!(condition)) {} else
+#endif
+
+#define __nv_drm_connector_for_each_possible_encoder(connector, encoder, __i) \
+       for ((__i) = 0; (__i) < ARRAY_SIZE((connector)->encoder_ids) &&        \
+                    (connector)->encoder_ids[(__i)] != 0; (__i)++)            \
+               for_each_if((encoder) =                                        \
+                           nv_drm_encoder_find((connector)->dev,              \
+                                               (connector)->encoder_ids[(__i)]))
+
+#define nv_drm_connector_for_each_possible_encoder(connector, encoder) \
+    {                                                                  \
+        unsigned int __i;                                              \
+        __nv_drm_connector_for_each_possible_encoder(connector, encoder, __i)
+
+#define nv_drm_connector_for_each_possible_encoder_end \
+    }
+
+#else
+
+#if NV_DRM_CONNECTOR_FOR_EACH_POSSIBLE_ENCODER_ARGUMENT_COUNT == 3
+
+#define nv_drm_connector_for_each_possible_encoder(connector, encoder) \
+    {                                                                  \
+        unsigned int __i;                                              \
+        drm_connector_for_each_possible_encoder(connector, encoder, __i)
+
+#define nv_drm_connector_for_each_possible_encoder_end \
+    }
+
+#else
+
+#define nv_drm_connector_for_each_possible_encoder(connector, encoder) \
+    drm_connector_for_each_possible_encoder(connector, encoder)
+
+#define nv_drm_connector_for_each_possible_encoder_end
+
+#endif
+
+#endif
+
+static inline int
+nv_drm_connector_attach_encoder(struct drm_connector *connector,
+                                struct drm_encoder *encoder)
+{
+#if defined(NV_DRM_CONNECTOR_FUNCS_HAVE_MODE_IN_NAME)
+    return drm_mode_connector_attach_encoder(connector, encoder);
+#else
+    return drm_connector_attach_encoder(connector, encoder);
+#endif
+}
+
+static inline int
+nv_drm_connector_update_edid_property(struct drm_connector *connector,
+                                      const struct edid *edid)
+{
+#if defined(NV_DRM_CONNECTOR_FUNCS_HAVE_MODE_IN_NAME)
+    return drm_mode_connector_update_edid_property(connector, edid);
+#else
+    return drm_connector_update_edid_property(connector, edid);
+#endif
+}
+
+#if defined(NV_DRM_CONNECTOR_LIST_ITER_PRESENT)
+#include <drm/drm_connector.h>
+
+static inline
+void nv_drm_connector_list_iter_begin(struct drm_device *dev,
+                                      struct drm_connector_list_iter *iter)
+{
+#if defined(NV_DRM_CONNECTOR_LIST_ITER_BEGIN_PRESENT)
+    drm_connector_list_iter_begin(dev, iter);
+#else
+    drm_connector_list_iter_get(dev, iter);
+#endif
+}
+
+static inline
+void nv_drm_connector_list_iter_end(struct drm_connector_list_iter *iter)
+{
+#if defined(NV_DRM_CONNECTOR_LIST_ITER_BEGIN_PRESENT)
+    drm_connector_list_iter_end(iter);
+#else
+    drm_connector_list_iter_put(iter);
+#endif
+}
+#endif
+
+/*
+ * The drm_format_num_planes() function was added by commit d0d110e09629 drm:
+ * Add drm_format_num_planes() utility function in v3.3 (2011-12-20). Prototype
+ * was moved from drm_crtc.h to drm_fourcc.h by commit ae4df11a0f53 (drm: Move
+ * format-related helpers to drm_fourcc.c) in v4.8 (2016-06-09).
+ * drm_format_num_planes() has been removed by commit 05c452c115bf (drm: Remove
+ * users of drm_format_num_planes) in v5.3 (2019-05-16).
+ *
+ * drm_format_info() is available only from v4.10 (2016-10-18), added by commit
+ * 84770cc24f3a (drm: Centralize format information).
+ */
+#include <drm/drm_crtc.h>
+#include <drm/drm_fourcc.h>
+
+static inline int nv_drm_format_num_planes(uint32_t format)
+{
+#if defined(NV_DRM_FORMAT_NUM_PLANES_PRESENT)
+    return drm_format_num_planes(format);
+#else
+    const struct drm_format_info *info = drm_format_info(format);
+    return info != NULL ? info->num_planes : 1;
+#endif
+}
+
+#if defined(NV_DRM_FORMAT_MODIFIERS_PRESENT)
+/*
+ * DRM_FORMAT_MOD_LINEAR was also defined after the original modifier support
+ * was added to the kernel, as a more explicit alias of DRM_FORMAT_MOD_NONE
+ */
+#if !defined(DRM_FORMAT_MOD_VENDOR_NONE)
+#define DRM_FORMAT_MOD_VENDOR_NONE 0
+#endif
+
+#if !defined(DRM_FORMAT_MOD_LINEAR)
+#define DRM_FORMAT_MOD_LINEAR fourcc_mod_code(NONE, 0)
+#endif
+
+/*
+ * DRM_FORMAT_MOD_INVALID was defined after the original modifier support was
+ * added to the kernel, for use as a sentinel value.
+ */
+#if !defined(DRM_FORMAT_RESERVED)
+#define DRM_FORMAT_RESERVED ((1ULL << 56) - 1)
+#endif
+
+#if !defined(DRM_FORMAT_MOD_INVALID)
+#define DRM_FORMAT_MOD_INVALID fourcc_mod_code(NONE, DRM_FORMAT_RESERVED)
+#endif
+
+/*
+ * DRM_FORMAT_MOD_VENDOR_NVIDIA was previously called
+ * DRM_FORMAT_MOD_VNEDOR_NV.
+ */
+#if !defined(DRM_FORMAT_MOD_VENDOR_NVIDIA)
+#define DRM_FORMAT_MOD_VENDOR_NVIDIA DRM_FORMAT_MOD_VENDOR_NV
+#endif
+
+/*
+ * DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D is a relatively new addition to the
+ * upstream kernel headers compared to the other format modifiers.
+ */
+#if !defined(DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D)
+#define DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(c, s, g, k, h) \
+    fourcc_mod_code(NVIDIA, (0x10 | \
+                             ((h) & 0xf) | \
+                             (((k) & 0xff) << 12) | \
+                             (((g) & 0x3) << 20) | \
+                             (((s) & 0x1) << 22) | \
+                             (((c) & 0x7) << 23)))
+#endif
+
+#endif /* defined(NV_DRM_FORMAT_MODIFIERS_PRESENT) */
+
+/*
+ * drm_vma_offset_exact_lookup_locked() were added
+ * by kernel commit 2225cfe46bcc which was Signed-off-by:
+ *      Daniel Vetter <daniel.vetter@intel.com>
+ *
+ * drm_vma_offset_exact_lookup_locked() were copied from
+ *      include/drm/drm_vma_manager.h @ 2225cfe46bcc
+ * which has the following copyright and license information:
+ *
+ * Copyright (c) 2013 David Herrmann <dh.herrmann@gmail.com>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#include <drm/drm_vma_manager.h>
+
+/**
+ * nv_drm_vma_offset_exact_lookup_locked() - Look up node by exact address
+ * @mgr: Manager object
+ * @start: Start address (page-based, not byte-based)
+ * @pages: Size of object (page-based)
+ *
+ * Same as drm_vma_offset_lookup_locked() but does not allow any offset into the node.
+ * It only returns the exact object with the given start address.
+ *
+ * RETURNS:
+ * Node at exact start address @start.
+ */
+static inline struct drm_vma_offset_node *
+nv_drm_vma_offset_exact_lookup_locked(struct drm_vma_offset_manager *mgr,
+                                      unsigned long start,
+                                      unsigned long pages)
+{
+#if defined(NV_DRM_VMA_OFFSET_EXACT_LOOKUP_LOCKED_PRESENT)
+    return drm_vma_offset_exact_lookup_locked(mgr, start, pages);
+#else
+    struct drm_vma_offset_node *node;
+
+    node = drm_vma_offset_lookup_locked(mgr, start, pages);
+    return (node && node->vm_node.start == start) ? node : NULL;
+#endif
+}
+
+static inline bool
+nv_drm_vma_node_is_allowed(struct drm_vma_offset_node *node,
+                           struct file *filp)
+{
+#if defined(NV_DRM_VMA_NODE_IS_ALLOWED_HAS_TAG_ARG)
+    return drm_vma_node_is_allowed(node, filp->private_data);
+#else
+    return drm_vma_node_is_allowed(node, filp);
+#endif
+}
+
+#endif /* defined(NV_DRM_ATOMIC_MODESET_AVAILABLE) */
+
+#endif /* defined(NV_DRM_AVAILABLE) */
+
+#endif /* __NVIDIA_DRM_HELPER_H__ */

NVIDIA-kernel-module-source-TempVersion/kernel-open/nvidia-drm/nvidia-drm-ioctl.h

@@ -0,0 +1,235 @@
+/*
+ * Copyright (c) 2015-2016, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef _UAPI_NVIDIA_DRM_IOCTL_H_
+#define _UAPI_NVIDIA_DRM_IOCTL_H_
+
+#include <drm/drm.h>
+
+/*
+ * We should do our best to keep these values constant. Any change to these will
+ * be backwards incompatible with client applications that might be using them
+ */
+#define DRM_NVIDIA_GET_CRTC_CRC32                   0x00
+#define DRM_NVIDIA_GEM_IMPORT_NVKMS_MEMORY          0x01
+#define DRM_NVIDIA_GEM_IMPORT_USERSPACE_MEMORY      0x02
+#define DRM_NVIDIA_GET_DEV_INFO                     0x03
+#define DRM_NVIDIA_FENCE_SUPPORTED                  0x04
+#define DRM_NVIDIA_FENCE_CONTEXT_CREATE             0x05
+#define DRM_NVIDIA_GEM_FENCE_ATTACH                 0x06
+#define DRM_NVIDIA_GET_CLIENT_CAPABILITY            0x08
+#define DRM_NVIDIA_GEM_EXPORT_NVKMS_MEMORY          0x09
+#define DRM_NVIDIA_GEM_MAP_OFFSET                   0x0a
+#define DRM_NVIDIA_GEM_ALLOC_NVKMS_MEMORY           0x0b
+#define DRM_NVIDIA_GET_CRTC_CRC32_V2                0x0c
+#define DRM_NVIDIA_GEM_EXPORT_DMABUF_MEMORY         0x0d
+#define DRM_NVIDIA_GEM_IDENTIFY_OBJECT              0x0e
+
+#define DRM_IOCTL_NVIDIA_GEM_IMPORT_NVKMS_MEMORY                           \
+    DRM_IOWR((DRM_COMMAND_BASE + DRM_NVIDIA_GEM_IMPORT_NVKMS_MEMORY),      \
+             struct drm_nvidia_gem_import_nvkms_memory_params)
+
+#define DRM_IOCTL_NVIDIA_GEM_IMPORT_USERSPACE_MEMORY                       \
+    DRM_IOWR((DRM_COMMAND_BASE + DRM_NVIDIA_GEM_IMPORT_USERSPACE_MEMORY),  \
+             struct drm_nvidia_gem_import_userspace_memory_params)
+
+#define DRM_IOCTL_NVIDIA_GET_DEV_INFO                                      \
+    DRM_IOWR((DRM_COMMAND_BASE + DRM_NVIDIA_GET_DEV_INFO),                 \
+             struct drm_nvidia_get_dev_info_params)
+
+/*
+ * XXX Solaris compiler has issues with DRM_IO. None of this is supported on
+ * Solaris anyway, so just skip it.
+ *
+ * 'warning: suggest parentheses around arithmetic in operand of |'
+ */
+#if defined(NV_LINUX)
+#define DRM_IOCTL_NVIDIA_FENCE_SUPPORTED                         \
+    DRM_IO(DRM_COMMAND_BASE + DRM_NVIDIA_FENCE_SUPPORTED)
+#else
+#define DRM_IOCTL_NVIDIA_FENCE_SUPPORTED 0
+#endif
+
+#define DRM_IOCTL_NVIDIA_FENCE_CONTEXT_CREATE                        \
+    DRM_IOWR((DRM_COMMAND_BASE + DRM_NVIDIA_FENCE_CONTEXT_CREATE),   \
+             struct drm_nvidia_fence_context_create_params)
+
+#define DRM_IOCTL_NVIDIA_GEM_FENCE_ATTACH                            \
+    DRM_IOW((DRM_COMMAND_BASE + DRM_NVIDIA_GEM_FENCE_ATTACH),        \
+            struct drm_nvidia_gem_fence_attach_params)
+
+#define DRM_IOCTL_NVIDIA_GET_CLIENT_CAPABILITY                       \
+    DRM_IOWR((DRM_COMMAND_BASE + DRM_NVIDIA_GET_CLIENT_CAPABILITY),  \
+             struct drm_nvidia_get_client_capability_params)
+
+#define DRM_IOCTL_NVIDIA_GET_CRTC_CRC32                              \
+    DRM_IOWR((DRM_COMMAND_BASE + DRM_NVIDIA_GET_CRTC_CRC32),         \
+             struct drm_nvidia_get_crtc_crc32_params)
+
+#define DRM_IOCTL_NVIDIA_GET_CRTC_CRC32_V2                           \
+    DRM_IOWR((DRM_COMMAND_BASE + DRM_NVIDIA_GET_CRTC_CRC32_V2),      \
+              struct drm_nvidia_get_crtc_crc32_v2_params)
+
+#define DRM_IOCTL_NVIDIA_GEM_EXPORT_NVKMS_MEMORY                           \
+    DRM_IOWR((DRM_COMMAND_BASE + DRM_NVIDIA_GEM_EXPORT_NVKMS_MEMORY),      \
+              struct drm_nvidia_gem_export_nvkms_memory_params)
+
+#define DRM_IOCTL_NVIDIA_GEM_MAP_OFFSET                              \
+    DRM_IOWR((DRM_COMMAND_BASE + DRM_NVIDIA_GEM_MAP_OFFSET),         \
+             struct drm_nvidia_gem_map_offset_params)
+
+#define DRM_IOCTL_NVIDIA_GEM_ALLOC_NVKMS_MEMORY                      \
+    DRM_IOWR((DRM_COMMAND_BASE + DRM_NVIDIA_GEM_ALLOC_NVKMS_MEMORY), \
+              struct drm_nvidia_gem_alloc_nvkms_memory_params)
+
+#define DRM_IOCTL_NVIDIA_GEM_EXPORT_DMABUF_MEMORY                      \
+    DRM_IOWR((DRM_COMMAND_BASE + DRM_NVIDIA_GEM_EXPORT_DMABUF_MEMORY), \
+              struct drm_nvidia_gem_export_dmabuf_memory_params)
+
+#define DRM_IOCTL_NVIDIA_GEM_IDENTIFY_OBJECT                      \
+    DRM_IOWR((DRM_COMMAND_BASE + DRM_NVIDIA_GEM_IDENTIFY_OBJECT), \
+              struct drm_nvidia_gem_identify_object_params)
+
+struct drm_nvidia_gem_import_nvkms_memory_params {
+    uint64_t mem_size;           /* IN */
+
+    uint64_t nvkms_params_ptr;   /* IN */
+    uint64_t nvkms_params_size;  /* IN */
+
+    uint32_t handle;             /* OUT */
+
+    uint32_t __pad;
+};
+
+struct drm_nvidia_gem_import_userspace_memory_params {
+    uint64_t size;               /* IN Size of memory in bytes */
+    uint64_t address;            /* IN Virtual address of userspace memory */
+    uint32_t handle;             /* OUT Handle to gem object */
+};
+
+struct drm_nvidia_get_dev_info_params {
+    uint32_t gpu_id;             /* OUT */
+    uint32_t primary_index;      /* OUT; the "card%d" value */
+
+    /* See DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D definitions of these */
+    uint32_t generic_page_kind;    /* OUT */
+    uint32_t page_kind_generation; /* OUT */
+    uint32_t sector_layout;        /* OUT */
+};
+
+struct drm_nvidia_fence_context_create_params {
+    uint32_t handle;            /* OUT GEM handle to fence context */
+
+    uint32_t index;             /* IN Index of semaphore to use for fencing */
+    uint64_t size;              /* IN Size of semaphore surface in bytes */
+
+    /* Params for importing userspace semaphore surface */
+    uint64_t import_mem_nvkms_params_ptr;  /* IN */
+    uint64_t import_mem_nvkms_params_size; /* IN */
+
+    /* Params for creating software signaling event */
+    uint64_t event_nvkms_params_ptr;  /* IN */
+    uint64_t event_nvkms_params_size; /* IN */
+};
+
+struct drm_nvidia_gem_fence_attach_params {
+    uint32_t handle;                /* IN GEM handle to attach fence to */
+    uint32_t fence_context_handle;  /* IN GEM handle to fence context on which fence is run on */
+    uint32_t sem_thresh;            /* IN Semaphore value to reach before signal */
+};
+
+struct drm_nvidia_get_client_capability_params {
+    uint64_t capability;    /* IN Client capability enum */
+    uint64_t value;         /* OUT Client capability value */
+};
+
+/* Struct that stores Crc value and if it is supported by hardware */
+struct drm_nvidia_crtc_crc32 {
+    uint32_t value; /* Read value, undefined if supported is false */
+    uint8_t supported; /* Supported boolean, true if readable by hardware */
+};
+
+struct drm_nvidia_crtc_crc32_v2_out {
+    struct drm_nvidia_crtc_crc32  compositorCrc32;        /* OUT compositor hardware CRC32 value */
+    struct drm_nvidia_crtc_crc32  rasterGeneratorCrc32;   /* OUT raster generator CRC32 value */
+    struct drm_nvidia_crtc_crc32  outputCrc32;            /* OUT SF/SOR CRC32 value */
+};
+
+struct drm_nvidia_get_crtc_crc32_v2_params {
+    uint32_t crtc_id;                             /* IN CRTC identifier */
+    struct drm_nvidia_crtc_crc32_v2_out crc32;    /* OUT Crc32 output structure */
+};
+
+struct drm_nvidia_get_crtc_crc32_params {
+    uint32_t crtc_id;      /* IN CRTC identifier */
+    uint32_t crc32;        /* OUT CRC32 value */
+};
+
+struct drm_nvidia_gem_export_nvkms_memory_params {
+    uint32_t handle;             /* IN */
+    uint32_t __pad;
+
+    uint64_t nvkms_params_ptr;   /* IN */
+    uint64_t nvkms_params_size;  /* IN */
+};
+
+struct drm_nvidia_gem_map_offset_params {
+    uint32_t handle;             /* IN Handle to gem object */
+    uint32_t __pad;
+
+    uint64_t offset;             /* OUT Fake offset */
+};
+
+#define NV_GEM_ALLOC_NO_SCANOUT                     (1 << 0)
+
+struct drm_nvidia_gem_alloc_nvkms_memory_params {
+    uint32_t handle;              /* OUT */
+    uint8_t  block_linear;        /* IN */
+    uint8_t  compressible;        /* IN/OUT */
+    uint16_t __pad;
+
+    uint64_t memory_size;         /* IN */
+    uint32_t flags;               /* IN */
+};
+
+struct drm_nvidia_gem_export_dmabuf_memory_params {
+    uint32_t handle;   /* IN GEM Handle*/
+    uint32_t __pad;
+
+    uint64_t nvkms_params_ptr;   /* IN */
+    uint64_t nvkms_params_size;  /* IN */
+};
+
+typedef enum {
+    NV_GEM_OBJECT_NVKMS,
+    NV_GEM_OBJECT_DMABUF,
+    NV_GEM_OBJECT_USERMEMORY,
+
+    NV_GEM_OBJECT_UNKNOWN = 0x7fffffff  /* Force size of 32-bits. */
+} drm_nvidia_gem_object_type;
+
+struct drm_nvidia_gem_identify_object_params {
+    uint32_t                    handle;         /* IN GEM handle*/
+    drm_nvidia_gem_object_type  object_type;    /* OUT GEM object type */
+};
+
+#endif /* _UAPI_NVIDIA_DRM_IOCTL_H_ */

NVIDIA-kernel-module-source-TempVersion/kernel-open/nvidia-drm/nvidia-drm-linux.c

@@ -0,0 +1,186 @@
+/*
+ * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#include <linux/module.h>
+#include <linux/slab.h>
+#include <linux/err.h>
+
+#include "nvidia-drm-os-interface.h"
+#include "nvidia-drm.h"
+
+#include "nvidia-drm-conftest.h"
+
+#if defined(NV_DRM_AVAILABLE)
+
+#if defined(NV_DRM_DRMP_H_PRESENT)
+#include <drm/drmP.h>
+#endif
+
+#include <linux/vmalloc.h>
+
+#include "nv-mm.h"
+
+MODULE_PARM_DESC(
+    modeset,
+    "Enable atomic kernel modesetting (1 = enable, 0 = disable (default))");
+bool nv_drm_modeset_module_param = false;
+module_param_named(modeset, nv_drm_modeset_module_param, bool, 0400);
+
+void *nv_drm_calloc(size_t nmemb, size_t size)
+{
+    return kzalloc(nmemb * size, GFP_KERNEL);
+}
+
+void nv_drm_free(void *ptr)
+{
+    if (IS_ERR(ptr)) {
+        return;
+    }
+
+    kfree(ptr);
+}
+
+char *nv_drm_asprintf(const char *fmt, ...)
+{
+    va_list ap;
+    char *p;
+
+    va_start(ap, fmt);
+    p = kvasprintf(GFP_KERNEL, fmt, ap);
+    va_end(ap);
+
+    return p;
+}
+
+#if defined(NVCPU_X86) || defined(NVCPU_X86_64)
+  #define WRITE_COMBINE_FLUSH()    asm volatile("sfence":::"memory")
+#elif defined(NVCPU_FAMILY_ARM)
+  #if defined(NVCPU_ARM)
+    #define WRITE_COMBINE_FLUSH()  { dsb(); outer_sync(); }
+  #elif defined(NVCPU_AARCH64)
+    #define WRITE_COMBINE_FLUSH()  mb()
+  #endif
+#elif defined(NVCPU_PPC64LE)
+  #define WRITE_COMBINE_FLUSH()    asm volatile("sync":::"memory")
+#endif
+
+void nv_drm_write_combine_flush(void)
+{
+    WRITE_COMBINE_FLUSH();
+}
+
+int nv_drm_lock_user_pages(unsigned long address,
+                           unsigned long pages_count, struct page ***pages)
+{
+    struct mm_struct *mm = current->mm;
+    struct page **user_pages;
+    int pages_pinned;
+
+    user_pages = nv_drm_calloc(pages_count, sizeof(*user_pages));
+
+    if (user_pages == NULL) {
+        return -ENOMEM;
+    }
+
+    nv_mmap_read_lock(mm);
+
+    pages_pinned = NV_PIN_USER_PAGES(address, pages_count, FOLL_WRITE,
+                                     user_pages, NULL);
+    nv_mmap_read_unlock(mm);
+
+    if (pages_pinned < 0 || (unsigned)pages_pinned < pages_count) {
+        goto failed;
+    }
+
+    *pages = user_pages;
+
+    return 0;
+
+failed:
+
+    if (pages_pinned > 0) {
+        int i;
+
+        for (i = 0; i < pages_pinned; i++) {
+           NV_UNPIN_USER_PAGE(user_pages[i]);
+        }
+    }
+
+    nv_drm_free(user_pages);
+
+    return (pages_pinned < 0) ? pages_pinned : -EINVAL;
+}
+
+void nv_drm_unlock_user_pages(unsigned long  pages_count, struct page **pages)
+{
+    unsigned long i;
+
+    for (i = 0; i < pages_count; i++) {
+        set_page_dirty_lock(pages[i]);
+        NV_UNPIN_USER_PAGE(pages[i]);
+    }
+
+    nv_drm_free(pages);
+}
+
+void *nv_drm_vmap(struct page **pages, unsigned long pages_count)
+{
+    return vmap(pages, pages_count, VM_USERMAP, PAGE_KERNEL);
+}
+
+void nv_drm_vunmap(void *address)
+{
+    vunmap(address);
+}
+
+#endif /* NV_DRM_AVAILABLE */
+
+/*************************************************************************
+ * Linux loading support code.
+ *************************************************************************/
+
+static int __init nv_linux_drm_init(void)
+{
+    return nv_drm_init();
+}
+
+static void __exit nv_linux_drm_exit(void)
+{
+    nv_drm_exit();
+}
+
+module_init(nv_linux_drm_init);
+module_exit(nv_linux_drm_exit);
+
+#if defined(MODULE_LICENSE)
+
+  MODULE_LICENSE("Dual MIT/GPL");
+
+
+
+#endif
+#if defined(MODULE_INFO)
+  MODULE_INFO(supported, "external");
+#endif
+#if defined(MODULE_VERSION)
+  MODULE_VERSION(NV_VERSION_STRING);
+#endif

NVIDIA-kernel-module-source-TempVersion/kernel-open/nvidia-drm/nvidia-drm-modeset.c

@@ -0,0 +1,577 @@
+/*
+ * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#include "nvidia-drm-conftest.h" /* NV_DRM_ATOMIC_MODESET_AVAILABLE */
+
+#if defined(NV_DRM_ATOMIC_MODESET_AVAILABLE)
+
+#include "nvidia-drm-priv.h"
+#include "nvidia-drm-modeset.h"
+#include "nvidia-drm-crtc.h"
+#include "nvidia-drm-os-interface.h"
+#include "nvidia-drm-helper.h"
+
+#if defined(NV_DRM_DRMP_H_PRESENT)
+#include <drm/drmP.h>
+#endif
+
+#if defined(NV_DRM_DRM_VBLANK_H_PRESENT)
+#include <drm/drm_vblank.h>
+#endif
+
+#include <drm/drm_atomic.h>
+#include <drm/drm_atomic_helper.h>
+#include <drm/drm_crtc.h>
+
+struct nv_drm_atomic_state {
+    struct NvKmsKapiRequestedModeSetConfig config;
+    struct drm_atomic_state base;
+};
+
+static inline struct nv_drm_atomic_state *to_nv_atomic_state(
+    struct drm_atomic_state *state)
+{
+    return container_of(state, struct nv_drm_atomic_state, base);
+}
+
+struct drm_atomic_state *nv_drm_atomic_state_alloc(struct drm_device *dev)
+{
+    struct nv_drm_atomic_state *nv_state =
+            nv_drm_calloc(1, sizeof(*nv_state));
+
+    if (nv_state == NULL || drm_atomic_state_init(dev, &nv_state->base) < 0) {
+        nv_drm_free(nv_state);
+        return NULL;
+    }
+
+    return &nv_state->base;
+}
+
+void nv_drm_atomic_state_clear(struct drm_atomic_state *state)
+{
+    drm_atomic_state_default_clear(state);
+}
+
+void nv_drm_atomic_state_free(struct drm_atomic_state *state)
+{
+    struct nv_drm_atomic_state *nv_state =
+                    to_nv_atomic_state(state);
+    drm_atomic_state_default_release(state);
+    nv_drm_free(nv_state);
+}
+
+/**
+ * __will_generate_flip_event - Check whether event is going to be generated by
+ * hardware when it flips from old crtc/plane state to current one. This
+ * function is called after drm_atomic_helper_swap_state(), therefore new state
+ * is swapped into current state.
+ */
+static bool __will_generate_flip_event(struct drm_crtc *crtc,
+                                       struct drm_crtc_state *old_crtc_state)
+{
+    struct drm_crtc_state *new_crtc_state = crtc->state;
+    struct nv_drm_crtc_state *nv_new_crtc_state =
+        to_nv_crtc_state(new_crtc_state);
+    struct drm_plane_state *old_plane_state = NULL;
+    struct drm_plane *plane = NULL;
+    struct drm_plane *primary_plane = crtc->primary;
+    bool primary_event = false;
+    bool overlay_event = false;
+    int i;
+
+    if (!old_crtc_state->active  && !new_crtc_state->active) {
+        /*
+         * crtc is not active in old and new states therefore all planes are
+         * disabled, hardware can not generate flip events.
+         */
+        return false;
+    }
+
+    /* Find out whether primary & overlay flip done events will be generated. */
+    nv_drm_for_each_plane_in_state(old_crtc_state->state,
+        plane, old_plane_state, i) {
+        if (old_plane_state->crtc != crtc) {
+           continue;
+        }
+
+        if (plane->type == DRM_PLANE_TYPE_CURSOR) {
+            continue;
+        }
+
+        /*
+         * Hardware generates flip event for only those
+         * planes which were active previously.
+         */
+        if (old_crtc_state->active && old_plane_state->fb != NULL) {
+            nv_new_crtc_state->nv_flip->pending_events++;
+        }
+    }
+
+    return nv_new_crtc_state->nv_flip->pending_events != 0;
+}
+
+static int __nv_drm_put_back_post_fence_fd(
+    struct nv_drm_plane_state *plane_state,
+    const struct NvKmsKapiLayerReplyConfig *layer_reply_config)
+{
+    int fd = layer_reply_config->postSyncptFd;
+
+    if ((fd >= 0) && (plane_state->fd_user_ptr != NULL)) {
+        if (put_user(fd, plane_state->fd_user_ptr)) {
+            return -EFAULT;
+        }
+
+        /*! set back to Null and let set_property specify it again */
+        plane_state->fd_user_ptr = NULL;
+    }
+    return 0;
+}
+
+static int __nv_drm_get_syncpt_data(
+    struct nv_drm_device *nv_dev,
+    struct drm_crtc *crtc,
+    struct drm_crtc_state *old_crtc_state,
+    struct NvKmsKapiRequestedModeSetConfig *requested_config,
+    struct NvKmsKapiModeSetReplyConfig *reply_config)
+{
+    struct nv_drm_crtc *nv_crtc = to_nv_crtc(crtc);
+    struct NvKmsKapiHeadReplyConfig *head_reply_config;
+    struct nv_drm_plane_state *plane_state;
+    struct drm_crtc_state *new_crtc_state = crtc->state;
+    struct drm_plane_state *old_plane_state = NULL;
+    struct drm_plane_state *new_plane_state = NULL;
+    struct drm_plane *plane = NULL;
+    int i, ret;
+
+    if (!old_crtc_state->active && !new_crtc_state->active) {
+        /*
+         * crtc is not active in old and new states therefore all planes are
+         * disabled, exit early.
+         */
+        return 0;
+    }
+
+    head_reply_config = &reply_config->headReplyConfig[nv_crtc->head];
+
+    nv_drm_for_each_plane_in_state(old_crtc_state->state, plane, old_plane_state, i) {
+        struct nv_drm_plane *nv_plane = to_nv_plane(plane);
+
+        if (plane->type == DRM_PLANE_TYPE_CURSOR || old_plane_state->crtc != crtc) {
+            continue;
+        }
+
+        new_plane_state = plane->state;
+
+        if (new_plane_state->crtc != crtc) {
+            continue;
+        }
+
+        plane_state = to_nv_drm_plane_state(new_plane_state);
+
+        ret = __nv_drm_put_back_post_fence_fd(
+            plane_state,
+            &head_reply_config->layerReplyConfig[nv_plane->layer_idx]);
+
+        if (ret != 0) {
+            return ret;
+        }
+    }
+
+    return 0;
+}
+
+/**
+ * nv_drm_atomic_commit - validate/commit modeset config
+ * @dev: DRM device
+ * @state: atomic state tracking atomic update
+ * @commit: commit/check modeset config associated with atomic update
+ *
+ * @state tracks atomic update and modeset objects affected
+ * by the atomic update, but the state of the modeset objects it contains
+ * depends on the current stage of the update.
+ * At the commit stage, the proposed state is already stored in the current
+ * state, and @state contains old state for all affected modeset objects.
+ * At the check/validation stage, @state contains the proposed state for
+ * all affected objects.
+ *
+ * Sequence of atomic update -
+ *   1. The check/validation of proposed atomic state,
+ *   2. Do any other steps that might fail,
+ *   3. Put the proposed state into the current state pointers,
+ *   4. Actually commit the hardware state,
+ *   5. Cleanup old state.
+ *
+ * The function nv_drm_atomic_apply_modeset_config() is getting called
+ * at stages (1) and (4) after drm_atomic_helper_swap_state().
+ */
+static int
+nv_drm_atomic_apply_modeset_config(struct drm_device *dev,
+                                   struct drm_atomic_state *state,
+                                   bool commit)
+{
+    struct nv_drm_device *nv_dev = to_nv_device(dev);
+    struct NvKmsKapiRequestedModeSetConfig *requested_config =
+        &(to_nv_atomic_state(state)->config);
+    struct NvKmsKapiModeSetReplyConfig reply_config = { };
+    struct drm_crtc *crtc;
+    struct drm_crtc_state *crtc_state;
+    int i;
+    int ret;
+
+    memset(requested_config, 0, sizeof(*requested_config));
+
+    /* Loop over affected crtcs and construct NvKmsKapiRequestedModeSetConfig */
+    nv_drm_for_each_crtc_in_state(state, crtc, crtc_state, i) {
+        /*
+         * When committing a state, the new state is already stored in
+         * crtc->state. When checking a proposed state, the proposed state is
+         * stored in crtc_state.
+         */
+        struct drm_crtc_state *new_crtc_state =
+                               commit ? crtc->state : crtc_state;
+        struct nv_drm_crtc *nv_crtc = to_nv_crtc(crtc);
+
+        requested_config->headRequestedConfig[nv_crtc->head] =
+            to_nv_crtc_state(new_crtc_state)->req_config;
+
+        requested_config->headsMask |= 1 << nv_crtc->head;
+
+        if (commit) {
+            struct drm_crtc_state *old_crtc_state = crtc_state;
+            struct nv_drm_crtc_state *nv_new_crtc_state =
+                to_nv_crtc_state(new_crtc_state);
+
+            nv_new_crtc_state->nv_flip->event = new_crtc_state->event;
+            nv_new_crtc_state->nv_flip->pending_events = 0;
+            new_crtc_state->event = NULL;
+
+            /*
+             * If flip event will be generated by hardware
+             * then defer flip object processing to flip event from hardware.
+             */
+            if (__will_generate_flip_event(crtc, old_crtc_state)) {
+                nv_drm_crtc_enqueue_flip(nv_crtc,
+                                         nv_new_crtc_state->nv_flip);
+
+                nv_new_crtc_state->nv_flip = NULL;
+            }
+        }
+    }
+
+    if (commit && nvKms->systemInfo.bAllowWriteCombining) {
+        /*
+         * XXX This call is required only if dumb buffer is going
+         * to be presented.
+         */
+         nv_drm_write_combine_flush();
+    }
+
+    if (!nvKms->applyModeSetConfig(nv_dev->pDevice,
+                                   requested_config,
+                                   &reply_config,
+                                   commit)) {
+        return -EINVAL;
+    }
+
+    if (commit && nv_dev->supportsSyncpts) {
+        nv_drm_for_each_crtc_in_state(state, crtc, crtc_state, i) {
+            /*! loop over affected crtcs and get NvKmsKapiModeSetReplyConfig */
+            ret = __nv_drm_get_syncpt_data(
+                      nv_dev, crtc, crtc_state, requested_config, &reply_config);
+            if (ret != 0) {
+                return ret;
+            }
+        }
+    }
+
+    return 0;
+}
+
+int nv_drm_atomic_check(struct drm_device *dev,
+                        struct drm_atomic_state *state)
+{
+    int ret = 0;
+
+    if ((ret = drm_atomic_helper_check(dev, state)) != 0) {
+        goto done;
+    }
+
+    ret = nv_drm_atomic_apply_modeset_config(dev,
+                                             state, false /* commit */);
+
+done:
+    return ret;
+}
+
+/**
+ * __nv_drm_handle_flip_event - handle flip occurred event
+ * @nv_crtc: crtc on which flip has been occurred
+ *
+ * This handler dequeues the first nv_drm_flip from the crtc's flip_list,
+ * generates an event if requested at flip time, and frees the nv_drm_flip.
+ */
+static void __nv_drm_handle_flip_event(struct nv_drm_crtc *nv_crtc)
+{
+    struct drm_device *dev = nv_crtc->base.dev;
+    struct nv_drm_device *nv_dev = to_nv_device(dev);
+    struct nv_drm_flip *nv_flip;
+
+    /*
+     * Acquire event_lock before nv_flip object dequeue, otherwise immediate
+     * flip event delivery from nv_drm_atomic_commit() races ahead and
+     * messes up with event delivery order.
+     */
+    spin_lock(&dev->event_lock);
+    nv_flip = nv_drm_crtc_dequeue_flip(nv_crtc);
+    if (likely(nv_flip != NULL)) {
+        struct nv_drm_flip *nv_deferred_flip, *nv_next_deferred_flip;
+
+        if (nv_flip->event != NULL) {
+            drm_crtc_send_vblank_event(&nv_crtc->base, nv_flip->event);
+        }
+
+        /*
+         * Process flips that were deferred until processing of this nv_flip
+         * object.
+         */
+        list_for_each_entry_safe(nv_deferred_flip,
+                                 nv_next_deferred_flip,
+                                 &nv_flip->deferred_flip_list, list_entry) {
+
+            if (nv_deferred_flip->event != NULL) {
+                drm_crtc_send_vblank_event(&nv_crtc->base,
+                                           nv_deferred_flip->event);
+            }
+            list_del(&nv_deferred_flip->list_entry);
+
+            nv_drm_free(nv_deferred_flip);
+        }
+    }
+    spin_unlock(&dev->event_lock);
+
+    wake_up_all(&nv_dev->flip_event_wq);
+
+    nv_drm_free(nv_flip);
+}
+
+int nv_drm_atomic_commit(struct drm_device *dev,
+                         struct drm_atomic_state *state,
+                         bool nonblock)
+{
+    int ret = -EBUSY;
+
+    int i;
+    struct drm_crtc *crtc = NULL;
+    struct drm_crtc_state *crtc_state = NULL;
+    struct nv_drm_device *nv_dev = to_nv_device(dev);
+
+    /*
+     * drm_mode_config_funcs::atomic_commit() mandates to return -EBUSY
+     * for nonblocking commit if previous updates (commit tasks/flip event) are
+     * pending. In case of blocking commits it mandates to wait for previous
+     * updates to complete.
+     */
+    if (nonblock) {
+        nv_drm_for_each_crtc_in_state(state, crtc, crtc_state, i) {
+            struct nv_drm_crtc *nv_crtc = to_nv_crtc(crtc);
+
+            /*
+             * Here you aren't required to hold nv_drm_crtc::flip_list_lock
+             * because:
+             *
+             * The core DRM driver acquires lock for all affected crtcs before
+             * calling into ->commit() hook, therefore it is not possible for
+             * other threads to call into ->commit() hook affecting same crtcs
+             * and enqueue flip objects into flip_list -
+             *
+             *   nv_drm_atomic_commit_internal()
+             *     |-> nv_drm_atomic_apply_modeset_config(commit=true)
+             *           |-> nv_drm_crtc_enqueue_flip()
+             *
+             * Only possibility is list_empty check races with code path
+             * dequeuing flip object -
+             *
+             *   __nv_drm_handle_flip_event()
+             *     |-> nv_drm_crtc_dequeue_flip()
+             *
+             * But this race condition can't lead list_empty() to return
+             * incorrect result. nv_drm_crtc_dequeue_flip() in the middle of
+             * updating the list could not trick us into thinking the list is
+             * empty when it isn't.
+             */
+            if (!list_empty(&nv_crtc->flip_list)) {
+                return -EBUSY;
+            }
+        }
+    }
+
+#if defined(NV_DRM_ATOMIC_HELPER_SWAP_STATE_HAS_STALL_ARG)
+
+    /*
+     * nv_drm_atomic_commit_internal()
+     * implements blocking/non-blocking atomic commit using
+     * nv_drm_crtc::flip_list, it does not require any help from core DRM
+     * helper functions to stall commit processing.  Therefore passing false to
+     * 'stall' parameter.
+     * In this context, failure from drm_atomic_helper_swap_state() is not
+     * expected.
+     */
+
+#if defined(NV_DRM_ATOMIC_HELPER_SWAP_STATE_RETURN_INT)
+    ret = drm_atomic_helper_swap_state(state, false /* stall */);
+    if (WARN_ON(ret != 0)) {
+        return ret;
+    }
+#else
+    drm_atomic_helper_swap_state(state, false /* stall */);
+#endif
+
+#else
+    drm_atomic_helper_swap_state(dev, state);
+#endif
+
+    /*
+     * nv_drm_atomic_commit_internal() must not return failure after
+     * calling drm_atomic_helper_swap_state().
+     */
+
+    if ((ret = nv_drm_atomic_apply_modeset_config(
+                    dev,
+                    state, true /* commit */)) != 0) {
+        NV_DRM_DEV_LOG_ERR(
+            nv_dev,
+            "Failed to apply atomic modeset.  Error code: %d",
+            ret);
+
+        goto done;
+    }
+
+    nv_drm_for_each_crtc_in_state(state, crtc, crtc_state, i) {
+        struct nv_drm_crtc *nv_crtc = to_nv_crtc(crtc);
+        struct nv_drm_crtc_state *nv_new_crtc_state =
+            to_nv_crtc_state(crtc->state);
+
+        /*
+         * If nv_drm_atomic_apply_modeset_config() hasn't consumed the flip
+         * object, no event will be generated for this flip, and we need process
+         * it:
+         */
+
+        if (nv_new_crtc_state->nv_flip != NULL) {
+            /*
+             * First, defer processing of all pending flips for this crtc until
+             * last flip in the queue has been processed. This is to ensure a
+             * correct order in event delivery.
+             */
+            spin_lock(&nv_crtc->flip_list_lock);
+            if (!list_empty(&nv_crtc->flip_list)) {
+                struct nv_drm_flip *nv_last_flip =
+                    list_last_entry(&nv_crtc->flip_list,
+                                    struct nv_drm_flip, list_entry);
+
+                list_add(&nv_new_crtc_state->nv_flip->list_entry,
+                    &nv_last_flip->deferred_flip_list);
+
+                nv_new_crtc_state->nv_flip = NULL;
+            }
+            spin_unlock(&nv_crtc->flip_list_lock);
+        }
+
+        if (nv_new_crtc_state->nv_flip != NULL) {
+            /*
+             * Then, if no more pending flips for this crtc, deliver event for the
+             * current flip.
+             */
+            if (nv_new_crtc_state->nv_flip->event != NULL) {
+                spin_lock(&dev->event_lock);
+                drm_crtc_send_vblank_event(crtc,
+                                           nv_new_crtc_state->nv_flip->event);
+                spin_unlock(&dev->event_lock);
+            }
+
+            nv_drm_free(nv_new_crtc_state->nv_flip);
+            nv_new_crtc_state->nv_flip = NULL;
+        }
+
+        if (!nonblock) {
+            /*
+             * Here you aren't required to hold nv_drm_crtc::flip_list_lock
+             * because:
+             *
+             * The core DRM driver acquires lock for all affected crtcs before
+             * calling into ->commit() hook, therefore it is not possible for
+             * other threads to call into ->commit() hook affecting same crtcs
+             * and enqueue flip objects into flip_list -
+             *
+             *   nv_drm_atomic_commit_internal()
+             *     |-> nv_drm_atomic_apply_modeset_config(commit=true)
+             *           |-> nv_drm_crtc_enqueue_flip()
+             *
+             * Only possibility is list_empty check races with code path
+             * dequeuing flip object -
+             *
+             *   __nv_drm_handle_flip_event()
+             *     |-> nv_drm_crtc_dequeue_flip()
+             *
+             * But this race condition can't lead list_empty() to return
+             * incorrect result. nv_drm_crtc_dequeue_flip() in the middle of
+             * updating the list could not trick us into thinking the list is
+             * empty when it isn't.
+             */
+            if (wait_event_timeout(
+                    nv_dev->flip_event_wq,
+                    list_empty(&nv_crtc->flip_list),
+                    3 * HZ /* 3 second */) == 0) {
+                NV_DRM_DEV_LOG_ERR(
+                    nv_dev,
+                    "Flip event timeout on head %u", nv_crtc->head);
+            }
+        }
+    }
+
+done:
+
+#if defined(NV_DRM_ATOMIC_STATE_REF_COUNTING_PRESENT)
+    /*
+     * If ref counting is present, state will be freed when the caller
+     * drops its reference after we return.
+     */
+#else
+    drm_atomic_state_free(state);
+#endif
+
+    return 0;
+}
+
+void nv_drm_handle_flip_occurred(struct nv_drm_device *nv_dev,
+                                 NvU32 head, NvU32 plane)
+{
+    struct nv_drm_crtc *nv_crtc = nv_drm_crtc_lookup(nv_dev, head);
+
+    if (NV_DRM_WARN(nv_crtc == NULL)) {
+        return;
+    }
+
+    __nv_drm_handle_flip_event(nv_crtc);
+}
+
+#endif

NVIDIA-kernel-module-source-TempVersion/kernel-open/nvidia-drm/nvidia-drm-modeset.h

@@ -0,0 +1,53 @@
+/*
+ * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef __NVIDIA_DRM_MODESET_H__
+#define __NVIDIA_DRM_MODESET_H__
+
+#include "nvidia-drm-conftest.h"
+
+#if defined(NV_DRM_ATOMIC_MODESET_AVAILABLE)
+
+#include "nvkms-kapi.h"
+
+struct drm_device;
+struct drm_atomic_state;
+
+struct drm_atomic_state *nv_drm_atomic_state_alloc(struct drm_device *dev);
+void nv_drm_atomic_state_clear(struct drm_atomic_state *state);
+void nv_drm_atomic_state_free(struct drm_atomic_state *state);
+
+int nv_drm_atomic_check(struct drm_device *dev,
+                        struct drm_atomic_state *state);
+
+int nv_drm_atomic_commit(struct drm_device *dev,
+                         struct drm_atomic_state *state, bool nonblock);
+
+
+void nv_drm_handle_flip_occurred(struct nv_drm_device *nv_dev,
+                                 NvU32 head, NvU32 plane);
+
+int nv_drm_shut_down_all_crtcs(struct drm_device *dev);
+
+#endif /* NV_DRM_ATOMIC_MODESET_AVAILABLE */
+
+#endif /* __NVIDIA_DRM_MODESET_H__ */

NVIDIA-kernel-module-source-TempVersion/kernel-open/nvidia-drm/nvidia-drm-os-interface.h

@@ -0,0 +1,56 @@
+/*
+ * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef __NVIDIA_DRM_OS_INTERFACE_H__
+#define __NVIDIA_DRM_OS_INTERFACE_H__
+
+#include "nvidia-drm-conftest.h" /* NV_DRM_AVAILABLE */
+
+#include "nvtypes.h"
+
+#if defined(NV_DRM_AVAILABLE)
+
+struct page;
+
+/* Set to true when the atomic modeset feature is enabled. */
+extern bool nv_drm_modeset_module_param;
+
+void *nv_drm_calloc(size_t nmemb, size_t size);
+
+void nv_drm_free(void *ptr);
+
+char *nv_drm_asprintf(const char *fmt, ...);
+
+void nv_drm_write_combine_flush(void);
+
+int nv_drm_lock_user_pages(unsigned long address,
+                           unsigned long pages_count, struct page ***pages);
+
+void nv_drm_unlock_user_pages(unsigned long  pages_count, struct page **pages);
+
+void *nv_drm_vmap(struct page **pages, unsigned long pages_count);
+
+void nv_drm_vunmap(void *address);
+
+#endif
+
+#endif /* __NVIDIA_DRM_OS_INTERFACE_H__ */

NVIDIA-kernel-module-source-TempVersion/kernel-open/nvidia-drm/nvidia-drm-prime-fence.c

@@ -0,0 +1,527 @@
+/*
+ * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#include "nvidia-drm-conftest.h"
+
+#if defined(NV_DRM_AVAILABLE)
+
+#if defined(NV_DRM_DRMP_H_PRESENT)
+#include <drm/drmP.h>
+#endif
+
+#include "nvidia-drm-priv.h"
+#include "nvidia-drm-ioctl.h"
+#include "nvidia-drm-gem.h"
+#include "nvidia-drm-prime-fence.h"
+#include "nvidia-dma-resv-helper.h"
+
+#if defined(NV_DRM_FENCE_AVAILABLE)
+
+#include "nvidia-dma-fence-helper.h"
+
+struct nv_drm_fence_context {
+    struct nv_drm_device *nv_dev;
+
+    uint32_t context;
+
+    NvU64 fenceSemIndex; /* Index into semaphore surface */
+
+    /* Mapped semaphore surface */
+    struct NvKmsKapiMemory *pSemSurface;
+    NvU32 *pLinearAddress;
+
+    /* Protects nv_drm_fence_context::{pending, last_seqno} */
+    spinlock_t lock;
+
+    /*
+     * Software signaling structures. __nv_drm_fence_context_new()
+     * allocates channel event and __nv_drm_fence_context_destroy() frees it.
+     * There are no simultaneous read/write access to 'cb', therefore it does
+     * not require spin-lock protection.
+     */
+    struct NvKmsKapiChannelEvent *cb;
+
+    /* List of pending fences which are not yet signaled */
+    struct list_head pending;
+
+    unsigned last_seqno;
+};
+
+struct nv_drm_prime_fence {
+    struct list_head list_entry;
+    nv_dma_fence_t base;
+    spinlock_t lock;
+};
+
+static inline
+struct nv_drm_prime_fence *to_nv_drm_prime_fence(nv_dma_fence_t *fence)
+{
+    return container_of(fence, struct nv_drm_prime_fence, base);
+}
+
+static const char*
+nv_drm_gem_prime_fence_op_get_driver_name(nv_dma_fence_t *fence)
+{
+    return "NVIDIA";
+}
+
+static const char*
+nv_drm_gem_prime_fence_op_get_timeline_name(nv_dma_fence_t *fence)
+{
+    return "nvidia.prime";
+}
+
+static bool nv_drm_gem_prime_fence_op_enable_signaling(nv_dma_fence_t *fence)
+{
+    // DO NOTHING
+    return true;
+}
+
+static void nv_drm_gem_prime_fence_op_release(nv_dma_fence_t *fence)
+{
+    struct nv_drm_prime_fence *nv_fence = to_nv_drm_prime_fence(fence);
+    nv_drm_free(nv_fence);
+}
+
+static signed long
+nv_drm_gem_prime_fence_op_wait(nv_dma_fence_t *fence,
+                               bool intr, signed long timeout)
+{
+    /*
+     * If the waiter requests to wait with no timeout, force a timeout to ensure
+     * that it won't get stuck forever in the kernel if something were to go
+     * wrong with signaling, such as a malicious userspace not releasing the
+     * semaphore.
+     *
+     * 96 ms (roughly 6 frames @ 60 Hz) is arbitrarily chosen to be long enough
+     * that it should never get hit during normal operation, but not so long
+     * that the system becomes unresponsive.
+     */
+    return nv_dma_fence_default_wait(fence, intr,
+                              (timeout == MAX_SCHEDULE_TIMEOUT) ?
+                                  msecs_to_jiffies(96) : timeout);
+}
+
+static const nv_dma_fence_ops_t nv_drm_gem_prime_fence_ops = {
+    .get_driver_name = nv_drm_gem_prime_fence_op_get_driver_name,
+    .get_timeline_name = nv_drm_gem_prime_fence_op_get_timeline_name,
+    .enable_signaling = nv_drm_gem_prime_fence_op_enable_signaling,
+    .release = nv_drm_gem_prime_fence_op_release,
+    .wait = nv_drm_gem_prime_fence_op_wait,
+};
+
+static inline void
+__nv_drm_prime_fence_signal(struct nv_drm_prime_fence *nv_fence)
+{
+    list_del(&nv_fence->list_entry);
+    nv_dma_fence_signal(&nv_fence->base);
+    nv_dma_fence_put(&nv_fence->base);
+}
+
+static void nv_drm_gem_prime_force_fence_signal(
+    struct nv_drm_fence_context *nv_fence_context)
+{
+    WARN_ON(!spin_is_locked(&nv_fence_context->lock));
+
+    while (!list_empty(&nv_fence_context->pending)) {
+        struct nv_drm_prime_fence *nv_fence = list_first_entry(
+            &nv_fence_context->pending,
+            typeof(*nv_fence),
+            list_entry);
+
+        __nv_drm_prime_fence_signal(nv_fence);
+    }
+}
+
+static void nv_drm_gem_prime_fence_event
+(
+    void *dataPtr,
+    NvU32 dataU32
+)
+{
+    struct nv_drm_fence_context *nv_fence_context = dataPtr;
+
+    spin_lock(&nv_fence_context->lock);
+
+    while (!list_empty(&nv_fence_context->pending)) {
+        struct nv_drm_prime_fence *nv_fence = list_first_entry(
+            &nv_fence_context->pending,
+            typeof(*nv_fence),
+            list_entry);
+
+        /* Index into surface with 16 byte stride */
+        unsigned int seqno = *((nv_fence_context->pLinearAddress) +
+                               (nv_fence_context->fenceSemIndex * 4));
+
+        if (nv_fence->base.seqno > seqno) {
+            /*
+             * Fences in list are placed in increasing order of sequence
+             * number, breaks a loop once found first fence not
+             * ready to signal.
+             */
+            break;
+        }
+
+        __nv_drm_prime_fence_signal(nv_fence);
+    }
+
+    spin_unlock(&nv_fence_context->lock);
+}
+
+static inline struct nv_drm_fence_context *__nv_drm_fence_context_new(
+    struct nv_drm_device *nv_dev,
+    struct drm_nvidia_fence_context_create_params *p)
+{
+    struct nv_drm_fence_context *nv_fence_context;
+    struct NvKmsKapiMemory *pSemSurface;
+    NvU32 *pLinearAddress;
+
+    /* Allocate backup nvkms resources */
+
+    pSemSurface = nvKms->importMemory(nv_dev->pDevice,
+                                      p->size,
+                                      p->import_mem_nvkms_params_ptr,
+                                      p->import_mem_nvkms_params_size);
+    if (!pSemSurface) {
+        NV_DRM_DEV_LOG_ERR(
+            nv_dev,
+            "Failed to import fence semaphore surface");
+
+        goto failed;
+    }
+
+    if (!nvKms->mapMemory(nv_dev->pDevice,
+                          pSemSurface,
+                          NVKMS_KAPI_MAPPING_TYPE_KERNEL,
+                          (void **) &pLinearAddress)) {
+        NV_DRM_DEV_LOG_ERR(
+            nv_dev,
+            "Failed to map fence semaphore surface");
+
+        goto failed_to_map_memory;
+    }
+
+    /*
+     * Allocate a fence context object, initialize it and allocate channel
+     * event for it.
+     */
+
+    if ((nv_fence_context = nv_drm_calloc(
+                    1,
+                    sizeof(*nv_fence_context))) == NULL) {
+        goto failed_alloc_fence_context;
+    }
+
+    /*
+     * nv_dma_fence_context_alloc() cannot fail, so we do not need
+     * to check a return value.
+     */
+
+    *nv_fence_context = (struct nv_drm_fence_context) {
+        .nv_dev = nv_dev,
+        .context = nv_dma_fence_context_alloc(1),
+        .pSemSurface = pSemSurface,
+        .pLinearAddress = pLinearAddress,
+        .fenceSemIndex = p->index,
+    };
+
+    INIT_LIST_HEAD(&nv_fence_context->pending);
+
+    spin_lock_init(&nv_fence_context->lock);
+
+    /*
+     * Except 'cb', the fence context should be completely initialized
+     * before channel event allocation because the fence context may start
+     * receiving events immediately after allocation.
+     *
+     * There are no simultaneous read/write access to 'cb', therefore it does
+     * not require spin-lock protection.
+     */
+    nv_fence_context->cb =
+        nvKms->allocateChannelEvent(nv_dev->pDevice,
+                                    nv_drm_gem_prime_fence_event,
+                                    nv_fence_context,
+                                    p->event_nvkms_params_ptr,
+                                    p->event_nvkms_params_size);
+    if (!nv_fence_context->cb) {
+        NV_DRM_DEV_LOG_ERR(nv_dev,
+                           "Failed to allocate fence signaling event");
+        goto failed_to_allocate_channel_event;
+    }
+
+    return nv_fence_context;
+
+failed_to_allocate_channel_event:
+    nv_drm_free(nv_fence_context);
+
+failed_alloc_fence_context:
+
+    nvKms->unmapMemory(nv_dev->pDevice,
+                       pSemSurface,
+                       NVKMS_KAPI_MAPPING_TYPE_KERNEL,
+                       (void *) pLinearAddress);
+
+failed_to_map_memory:
+    nvKms->freeMemory(nv_dev->pDevice, pSemSurface);
+
+failed:
+    return NULL;
+}
+
+static void __nv_drm_fence_context_destroy(
+    struct nv_drm_fence_context *nv_fence_context)
+{
+    struct nv_drm_device *nv_dev = nv_fence_context->nv_dev;
+
+    /*
+     * Free channel event before destroying the fence context, otherwise event
+     * callback continue to get called.
+     */
+    nvKms->freeChannelEvent(nv_dev->pDevice, nv_fence_context->cb);
+
+    /* Force signal all pending fences and empty pending list */
+    spin_lock(&nv_fence_context->lock);
+
+    nv_drm_gem_prime_force_fence_signal(nv_fence_context);
+
+    spin_unlock(&nv_fence_context->lock);
+
+    /* Free nvkms resources */
+
+    nvKms->unmapMemory(nv_dev->pDevice,
+                       nv_fence_context->pSemSurface,
+                       NVKMS_KAPI_MAPPING_TYPE_KERNEL,
+                       (void *) nv_fence_context->pLinearAddress);
+
+    nvKms->freeMemory(nv_dev->pDevice, nv_fence_context->pSemSurface);
+
+    nv_drm_free(nv_fence_context);
+}
+
+static nv_dma_fence_t *__nv_drm_fence_context_create_fence(
+    struct nv_drm_fence_context *nv_fence_context,
+    unsigned int seqno)
+{
+    struct nv_drm_prime_fence *nv_fence;
+    int ret = 0;
+
+    if ((nv_fence = nv_drm_calloc(1, sizeof(*nv_fence))) == NULL) {
+        ret = -ENOMEM;
+        goto out;
+    }
+
+    spin_lock(&nv_fence_context->lock);
+
+    /*
+     * If seqno wrapped, force signal fences to make sure none of them
+     * get stuck.
+     */
+    if (seqno < nv_fence_context->last_seqno) {
+        nv_drm_gem_prime_force_fence_signal(nv_fence_context);
+    }
+
+    INIT_LIST_HEAD(&nv_fence->list_entry);
+
+    spin_lock_init(&nv_fence->lock);
+
+    nv_dma_fence_init(&nv_fence->base, &nv_drm_gem_prime_fence_ops,
+                      &nv_fence->lock, nv_fence_context->context,
+                      seqno);
+
+    list_add_tail(&nv_fence->list_entry, &nv_fence_context->pending);
+
+    nv_fence_context->last_seqno = seqno;
+
+    spin_unlock(&nv_fence_context->lock);
+
+out:
+    return ret != 0 ? ERR_PTR(ret) : &nv_fence->base;
+}
+
+int nv_drm_fence_supported_ioctl(struct drm_device *dev,
+                                 void *data, struct drm_file *filep)
+{
+    struct nv_drm_device *nv_dev = to_nv_device(dev);
+    return nv_dev->pDevice ? 0 : -EINVAL;
+}
+
+struct nv_drm_gem_fence_context {
+    struct nv_drm_gem_object base;
+    struct nv_drm_fence_context *nv_fence_context;
+};
+
+static inline struct nv_drm_gem_fence_context *to_gem_fence_context(
+    struct nv_drm_gem_object *nv_gem)
+{
+    if (nv_gem != NULL) {
+        return container_of(nv_gem, struct nv_drm_gem_fence_context, base);
+    }
+
+    return NULL;
+}
+
+/*
+ * Tear down of the 'struct nv_drm_gem_fence_context' object is not expected
+ * to be happen from any worker thread, if that happen it causes dead-lock
+ * because tear down sequence calls to flush all existing
+ * worker thread.
+ */
+static void __nv_drm_gem_fence_context_free(struct nv_drm_gem_object *nv_gem)
+{
+    struct nv_drm_gem_fence_context *nv_gem_fence_context =
+        to_gem_fence_context(nv_gem);
+
+    __nv_drm_fence_context_destroy(nv_gem_fence_context->nv_fence_context);
+
+    nv_drm_free(nv_gem_fence_context);
+}
+
+const struct nv_drm_gem_object_funcs nv_gem_fence_context_ops = {
+    .free = __nv_drm_gem_fence_context_free,
+};
+
+static inline
+struct nv_drm_gem_fence_context *__nv_drm_gem_object_fence_context_lookup(
+    struct drm_device *dev,
+    struct drm_file *filp,
+    u32 handle)
+{
+    struct nv_drm_gem_object *nv_gem =
+            nv_drm_gem_object_lookup(dev, filp, handle);
+
+    if (nv_gem != NULL && nv_gem->ops != &nv_gem_fence_context_ops) {
+        nv_drm_gem_object_unreference_unlocked(nv_gem);
+        return NULL;
+    }
+
+    return to_gem_fence_context(nv_gem);
+}
+
+int nv_drm_fence_context_create_ioctl(struct drm_device *dev,
+                                      void *data, struct drm_file *filep)
+{
+    struct nv_drm_device *nv_dev = to_nv_device(dev);
+    struct drm_nvidia_fence_context_create_params *p = data;
+    struct nv_drm_gem_fence_context *nv_gem_fence_context = NULL;
+
+    if ((nv_gem_fence_context = nv_drm_calloc(
+                1,
+                sizeof(struct nv_drm_gem_fence_context))) == NULL) {
+        goto done;
+    }
+
+    if ((nv_gem_fence_context->nv_fence_context =
+                __nv_drm_fence_context_new(nv_dev, p)) == NULL) {
+        goto fence_context_new_failed;
+    }
+
+    nv_drm_gem_object_init(nv_dev,
+                           &nv_gem_fence_context->base,
+                           &nv_gem_fence_context_ops,
+                           0 /* size */,
+                           NULL /* pMemory */);
+
+    return nv_drm_gem_handle_create_drop_reference(filep,
+                                                   &nv_gem_fence_context->base,
+                                                   &p->handle);
+
+fence_context_new_failed:
+    nv_drm_free(nv_gem_fence_context);
+
+done:
+    return -ENOMEM;
+}
+
+int nv_drm_gem_fence_attach_ioctl(struct drm_device *dev,
+                                  void *data, struct drm_file *filep)
+{
+    int ret = -EINVAL;
+    struct nv_drm_device *nv_dev = to_nv_device(dev);
+    struct drm_nvidia_gem_fence_attach_params *p = data;
+
+    struct nv_drm_gem_object *nv_gem;
+    struct nv_drm_gem_fence_context *nv_gem_fence_context;
+
+    nv_dma_fence_t *fence;
+
+    nv_gem = nv_drm_gem_object_lookup(nv_dev->dev, filep, p->handle);
+
+    if (!nv_gem) {
+        NV_DRM_DEV_LOG_ERR(
+            nv_dev,
+            "Failed to lookup gem object for fence attach: 0x%08x",
+            p->handle);
+
+        goto done;
+    }
+
+    if((nv_gem_fence_context = __nv_drm_gem_object_fence_context_lookup(
+                nv_dev->dev,
+                filep,
+                p->fence_context_handle)) == NULL) {
+
+        NV_DRM_DEV_LOG_ERR(
+            nv_dev,
+            "Failed to lookup gem object for fence context: 0x%08x",
+            p->fence_context_handle);
+
+        goto fence_context_lookup_failed;
+    }
+
+    if (IS_ERR(fence = __nv_drm_fence_context_create_fence(
+                            nv_gem_fence_context->nv_fence_context,
+                            p->sem_thresh))) {
+        ret = PTR_ERR(fence);
+
+        NV_DRM_DEV_LOG_ERR(
+            nv_dev,
+            "Failed to allocate fence: 0x%08x", p->handle);
+
+        goto fence_context_create_fence_failed;
+    }
+
+    nv_dma_resv_lock(&nv_gem->resv, NULL);
+
+    ret = nv_dma_resv_reserve_fences(&nv_gem->resv, 1, false);
+    if (ret == 0) {
+        nv_dma_resv_add_excl_fence(&nv_gem->resv, fence);
+    } else {
+        NV_DRM_DEV_LOG_ERR(
+            nv_dev,
+            "Failed to reserve fence. Error code: %d", ret);
+    }
+
+    nv_dma_resv_unlock(&nv_gem->resv);
+
+fence_context_create_fence_failed:
+    nv_drm_gem_object_unreference_unlocked(&nv_gem_fence_context->base);
+
+fence_context_lookup_failed:
+    nv_drm_gem_object_unreference_unlocked(nv_gem);
+
+done:
+    return ret;
+}
+
+#endif /* NV_DRM_FENCE_AVAILABLE */
+
+#endif /* NV_DRM_AVAILABLE */

NVIDIA-kernel-module-source-TempVersion/kernel-open/nvidia-drm/nvidia-drm-prime-fence.h

@@ -0,0 +1,48 @@
+/*
+ * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef __NVIDIA_DRM_PRIME_FENCE_H__
+#define __NVIDIA_DRM_PRIME_FENCE_H__
+
+#include "nvidia-drm-conftest.h"
+
+#if defined(NV_DRM_AVAILABLE)
+
+struct drm_file;
+struct drm_device;
+
+#if defined(NV_DRM_FENCE_AVAILABLE)
+
+int nv_drm_fence_supported_ioctl(struct drm_device *dev,
+                                 void *data, struct drm_file *filep);
+
+int nv_drm_fence_context_create_ioctl(struct drm_device *dev,
+                                      void *data, struct drm_file *filep);
+
+int nv_drm_gem_fence_attach_ioctl(struct drm_device *dev,
+                                  void *data, struct drm_file *filep);
+
+#endif /* NV_DRM_FENCE_AVAILABLE */
+
+#endif /* NV_DRM_AVAILABLE */
+
+#endif /* __NVIDIA_DRM_PRIME_FENCE_H__ */

NVIDIA-kernel-module-source-TempVersion/kernel-open/nvidia-drm/nvidia-drm-priv.h

@@ -0,0 +1,144 @@
+/*
+ * Copyright (c) 2015-2022, NVIDIA CORPORATION. All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef __NVIDIA_DRM_PRIV_H__
+#define __NVIDIA_DRM_PRIV_H__
+
+#include "nvidia-drm-conftest.h" /* NV_DRM_AVAILABLE */
+
+#if defined(NV_DRM_AVAILABLE)
+
+#if defined(NV_DRM_DRMP_H_PRESENT)
+#include <drm/drmP.h>
+#endif
+
+#if defined(NV_DRM_DRM_DEVICE_H_PRESENT)
+#include <drm/drm_device.h>
+#endif
+
+#if defined(NV_DRM_DRM_GEM_H_PRESENT)
+#include <drm/drm_gem.h>
+#endif
+
+#include "nvidia-drm-os-interface.h"
+
+#include "nvkms-kapi.h"
+
+#define NV_DRM_LOG_ERR(__fmt, ...) \
+    DRM_ERROR("[nvidia-drm] " __fmt "\n", ##__VA_ARGS__)
+
+#define NV_DRM_LOG_INFO(__fmt, ...) \
+    DRM_INFO("[nvidia-drm] " __fmt "\n", ##__VA_ARGS__)
+
+#define NV_DRM_DEV_LOG_INFO(__dev, __fmt, ...) \
+    NV_DRM_LOG_INFO("[GPU ID 0x%08x] " __fmt, __dev->gpu_info.gpu_id, ##__VA_ARGS__)
+
+#define NV_DRM_DEV_LOG_ERR(__dev, __fmt, ...) \
+    NV_DRM_LOG_ERR("[GPU ID 0x%08x] " __fmt, __dev->gpu_info.gpu_id, ##__VA_ARGS__)
+
+#define NV_DRM_WARN(__condition) WARN_ON((__condition))
+
+#define NV_DRM_DEBUG_DRIVER(__fmt, ...) \
+    DRM_DEBUG_DRIVER("[nvidia-drm] " __fmt "\n", ##__VA_ARGS__)
+
+#define NV_DRM_DEV_DEBUG_DRIVER(__dev, __fmt, ...) \
+    DRM_DEBUG_DRIVER("[GPU ID 0x%08x] " __fmt,     \
+                     __dev->gpu_info.gpu_id, ##__VA_ARGS__)
+
+struct nv_drm_device {
+    nv_gpu_info_t gpu_info;
+
+    struct drm_device *dev;
+
+    struct NvKmsKapiDevice *pDevice;
+
+#if defined(NV_DRM_ATOMIC_MODESET_AVAILABLE)
+    /*
+     * Lock to protect drm-subsystem and fields of this structure
+     * from concurrent access.
+     *
+     * Do not hold this lock if some lock from core drm-subsystem
+     * is already held, locking order should be like this -
+     *
+     *   mutex_lock(nv_drm_device::lock);
+     *     ....
+     *     mutex_lock(drm_device::mode_config::lock);
+     *     ....
+     *     .......
+     *     mutex_unlock(drm_device::mode_config::lock);
+     *     ........
+     *     ..
+     *     mutex_lock(drm_device::struct_mutex);
+     *     ....
+     *     ........
+     *     mutex_unlock(drm_device::struct_mutex);
+     *     ..
+     *   mutex_unlock(nv_drm_device::lock);
+     */
+    struct mutex lock;
+
+    NvU32 pitchAlignment;
+
+    NvU8 genericPageKind;
+    NvU8 pageKindGeneration;
+    NvU8 sectorLayout;
+#if defined(NV_DRM_FORMAT_MODIFIERS_PRESENT)
+    NvU64 modifiers[6 /* block linear */ + 1 /* linear */ + 1 /* terminator */];
+#endif
+
+    atomic_t enable_event_handling;
+
+    /**
+     * @flip_event_wq:
+     *
+     * The wait queue on which nv_drm_atomic_commit_internal() sleeps until
+     * next flip event occurs.
+     */
+    wait_queue_head_t flip_event_wq;
+
+#endif
+
+    NvBool hasVideoMemory;
+
+    NvBool supportsSyncpts;
+
+    struct drm_property *nv_out_fence_property;
+    struct drm_property *nv_input_colorspace_property;
+
+#if defined(NV_DRM_HAS_HDR_OUTPUT_METADATA)
+    struct drm_property *nv_hdr_output_metadata_property;
+#endif
+
+    struct nv_drm_device *next;
+};
+
+static inline struct nv_drm_device *to_nv_device(
+    struct drm_device *dev)
+{
+    return dev->dev_private;
+}
+
+extern const struct NvKmsKapiFunctionsTable* const nvKms;
+
+#endif /* defined(NV_DRM_AVAILABLE) */
+
+#endif /* __NVIDIA_DRM_PRIV_H__ */

NVIDIA-kernel-module-source-TempVersion/kernel-open/nvidia-drm/nvidia-drm-utils.c

@@ -0,0 +1,231 @@
+/*
+ * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#include "nvidia-drm-conftest.h" /* NV_DRM_ATOMIC_MODESET_AVAILABLE */
+
+#if defined(NV_DRM_ATOMIC_MODESET_AVAILABLE)
+
+#if defined(NV_DRM_DRMP_H_PRESENT)
+#include <drm/drmP.h>
+#endif
+
+#if defined(NV_DRM_DRM_PLANE_H_PRESENT)
+#include <drm/drm_plane.h>
+#endif
+
+#include <drm/drm_modes.h>
+#include <uapi/drm/drm_fourcc.h>
+
+#include "nvidia-drm-priv.h"
+#include "nvidia-drm-utils.h"
+
+struct NvKmsKapiConnectorInfo*
+nvkms_get_connector_info(struct NvKmsKapiDevice *pDevice,
+                         NvKmsKapiConnector hConnector)
+{
+    struct NvKmsKapiConnectorInfo *connectorInfo =
+                           nv_drm_calloc(1, sizeof(*connectorInfo));
+
+    if (connectorInfo == NULL) {
+        return ERR_PTR(-ENOMEM);
+    }
+
+    if (!nvKms->getConnectorInfo(pDevice, hConnector, connectorInfo)) {
+        nv_drm_free(connectorInfo);
+
+        return ERR_PTR(-EINVAL);
+    }
+
+    return connectorInfo;
+}
+
+int
+nvkms_connector_signal_to_drm_encoder_signal(NvKmsConnectorSignalFormat format)
+{
+    switch (format) {
+        default:
+        case NVKMS_CONNECTOR_SIGNAL_FORMAT_UNKNOWN:
+            return DRM_MODE_ENCODER_NONE;
+        case NVKMS_CONNECTOR_SIGNAL_FORMAT_TMDS:
+        case NVKMS_CONNECTOR_SIGNAL_FORMAT_DP:
+            return DRM_MODE_ENCODER_TMDS;
+        case NVKMS_CONNECTOR_SIGNAL_FORMAT_LVDS:
+            return DRM_MODE_ENCODER_LVDS;
+        case NVKMS_CONNECTOR_SIGNAL_FORMAT_VGA:
+            return DRM_MODE_ENCODER_DAC;
+        case NVKMS_CONNECTOR_SIGNAL_FORMAT_DSI:
+            return DRM_MODE_ENCODER_DSI;
+    }
+}
+
+int nvkms_connector_type_to_drm_connector_type(NvKmsConnectorType type,
+                                               NvBool internal)
+{
+    switch (type) {
+        default:
+        case NVKMS_CONNECTOR_TYPE_UNKNOWN:
+            return DRM_MODE_CONNECTOR_Unknown;
+        case NVKMS_CONNECTOR_TYPE_DP:
+            return
+                internal ?
+                DRM_MODE_CONNECTOR_eDP : DRM_MODE_CONNECTOR_DisplayPort;
+        case NVKMS_CONNECTOR_TYPE_HDMI:
+            return DRM_MODE_CONNECTOR_HDMIA;
+        case NVKMS_CONNECTOR_TYPE_DVI_D:
+            return DRM_MODE_CONNECTOR_DVID;
+        case NVKMS_CONNECTOR_TYPE_DVI_I:
+            return DRM_MODE_CONNECTOR_DVII;
+        case NVKMS_CONNECTOR_TYPE_LVDS:
+            return DRM_MODE_CONNECTOR_LVDS;
+        case NVKMS_CONNECTOR_TYPE_VGA:
+            return DRM_MODE_CONNECTOR_VGA;
+        case NVKMS_CONNECTOR_TYPE_DSI:
+            return DRM_MODE_CONNECTOR_DSI;
+        case NVKMS_CONNECTOR_TYPE_DP_SERIALIZER:
+            return DRM_MODE_CONNECTOR_DisplayPort;
+    }
+}
+
+void
+nvkms_display_mode_to_drm_mode(const struct NvKmsKapiDisplayMode *displayMode,
+                               struct drm_display_mode *mode)
+{
+#if defined(NV_DRM_DISPLAY_MODE_HAS_VREFRESH)
+    mode->vrefresh    = (displayMode->timings.refreshRate + 500) / 1000; /* In Hz */
+#endif
+
+    mode->clock       = (displayMode->timings.pixelClockHz + 500) / 1000; /* In Hz */
+
+    mode->hdisplay    = displayMode->timings.hVisible;
+    mode->hsync_start = displayMode->timings.hSyncStart;
+    mode->hsync_end   = displayMode->timings.hSyncEnd;
+    mode->htotal      = displayMode->timings.hTotal;
+    mode->hskew       = displayMode->timings.hSkew;
+
+    mode->vdisplay    = displayMode->timings.vVisible;
+    mode->vsync_start = displayMode->timings.vSyncStart;
+    mode->vsync_end   = displayMode->timings.vSyncEnd;
+    mode->vtotal      = displayMode->timings.vTotal;
+
+    if (displayMode->timings.flags.interlaced) {
+        mode->flags |= DRM_MODE_FLAG_INTERLACE;
+    }
+
+    if (displayMode->timings.flags.doubleScan) {
+        mode->flags |= DRM_MODE_FLAG_DBLSCAN;
+    }
+
+    if (displayMode->timings.flags.hSyncPos) {
+        mode->flags |= DRM_MODE_FLAG_PHSYNC;
+    }
+
+    if (displayMode->timings.flags.hSyncNeg) {
+        mode->flags |= DRM_MODE_FLAG_NHSYNC;
+    }
+
+    if (displayMode->timings.flags.vSyncPos) {
+        mode->flags |= DRM_MODE_FLAG_PVSYNC;
+    }
+
+    if (displayMode->timings.flags.vSyncNeg) {
+        mode->flags |= DRM_MODE_FLAG_NVSYNC;
+    }
+
+    mode->width_mm  = displayMode->timings.widthMM;
+    mode->height_mm = displayMode->timings.heightMM;
+
+    if (strlen(displayMode->name) != 0) {
+        memcpy(
+            mode->name, displayMode->name,
+            min(sizeof(mode->name), sizeof(displayMode->name)));
+
+        mode->name[sizeof(mode->name) - 1] = '\0';
+    } else {
+        drm_mode_set_name(mode);
+    }
+}
+
+void drm_mode_to_nvkms_display_mode(const struct drm_display_mode *src,
+                                    struct NvKmsKapiDisplayMode *dst)
+{
+#if defined(NV_DRM_DISPLAY_MODE_HAS_VREFRESH)
+    dst->timings.refreshRate  = src->vrefresh * 1000;
+#else
+    dst->timings.refreshRate  = drm_mode_vrefresh(src) * 1000;
+#endif
+
+    dst->timings.pixelClockHz = src->clock * 1000; /* In Hz */
+
+    dst->timings.hVisible   = src->hdisplay;
+    dst->timings.hSyncStart = src->hsync_start;
+    dst->timings.hSyncEnd   = src->hsync_end;
+    dst->timings.hTotal     = src->htotal;
+    dst->timings.hSkew      = src->hskew;
+
+    dst->timings.vVisible   = src->vdisplay;
+    dst->timings.vSyncStart = src->vsync_start;
+    dst->timings.vSyncEnd   = src->vsync_end;
+    dst->timings.vTotal     = src->vtotal;
+
+    if (src->flags & DRM_MODE_FLAG_INTERLACE) {
+        dst->timings.flags.interlaced = NV_TRUE;
+    } else {
+        dst->timings.flags.interlaced = NV_FALSE;
+    }
+
+    if (src->flags & DRM_MODE_FLAG_DBLSCAN) {
+        dst->timings.flags.doubleScan = NV_TRUE;
+    } else {
+        dst->timings.flags.doubleScan = NV_FALSE;
+    }
+
+    if (src->flags & DRM_MODE_FLAG_PHSYNC) {
+        dst->timings.flags.hSyncPos = NV_TRUE;
+    } else {
+        dst->timings.flags.hSyncPos = NV_FALSE;
+    }
+
+    if (src->flags & DRM_MODE_FLAG_NHSYNC) {
+        dst->timings.flags.hSyncNeg = NV_TRUE;
+    } else {
+       dst->timings.flags.hSyncNeg = NV_FALSE;
+    }
+
+    if (src->flags & DRM_MODE_FLAG_PVSYNC) {
+        dst->timings.flags.vSyncPos = NV_TRUE;
+    } else {
+        dst->timings.flags.vSyncPos = NV_FALSE;
+    }
+
+    if (src->flags & DRM_MODE_FLAG_NVSYNC) {
+        dst->timings.flags.vSyncNeg = NV_TRUE;
+    } else {
+        dst->timings.flags.vSyncNeg = NV_FALSE;
+    }
+
+    dst->timings.widthMM  = src->width_mm;
+    dst->timings.heightMM = src->height_mm;
+
+    memcpy(dst->name, src->name, min(sizeof(dst->name), sizeof(src->name)));
+}
+
+#endif

NVIDIA-kernel-module-source-TempVersion/kernel-open/nvidia-drm/nvidia-drm-utils.h

@@ -0,0 +1,54 @@
+/*
+ * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef __NVIDIA_DRM_UTILS_H__
+#define __NVIDIA_DRM_UTILS_H__
+
+#include "nvidia-drm-conftest.h"
+
+#if defined(NV_DRM_ATOMIC_MODESET_AVAILABLE)
+
+#include "nvkms-kapi.h"
+
+enum drm_plane_type;
+struct drm_display_mode;
+
+struct NvKmsKapiConnectorInfo*
+nvkms_get_connector_info(struct NvKmsKapiDevice *pDevice,
+                         NvKmsKapiConnector hConnector);
+
+int nvkms_connector_signal_to_drm_encoder_signal(
+    NvKmsConnectorSignalFormat format);
+
+int nvkms_connector_type_to_drm_connector_type(NvKmsConnectorType type,
+                                               NvBool internal);
+
+void nvkms_display_mode_to_drm_mode(
+    const struct NvKmsKapiDisplayMode *displayMode,
+    struct drm_display_mode *mode);
+
+void drm_mode_to_nvkms_display_mode(const struct drm_display_mode *src,
+                                    struct NvKmsKapiDisplayMode *dst);
+
+#endif /* NV_DRM_ATOMIC_MODESET_AVAILABLE */
+
+#endif /* __NVIDIA_DRM_UTILS_H__ */

NVIDIA-kernel-module-source-TempVersion/kernel-open/nvidia-drm/nvidia-drm.Kbuild

@@ -0,0 +1,124 @@
+###########################################################################
+# Kbuild fragment for nvidia-drm.ko
+###########################################################################
+
+#
+# Define NVIDIA_DRM_{SOURCES,OBJECTS}
+#
+
+NVIDIA_DRM_SOURCES =
+NVIDIA_DRM_SOURCES += nvidia-drm/nvidia-drm.c
+NVIDIA_DRM_SOURCES += nvidia-drm/nvidia-drm-drv.c
+NVIDIA_DRM_SOURCES += nvidia-drm/nvidia-drm-utils.c
+NVIDIA_DRM_SOURCES += nvidia-drm/nvidia-drm-crtc.c
+NVIDIA_DRM_SOURCES += nvidia-drm/nvidia-drm-encoder.c
+NVIDIA_DRM_SOURCES += nvidia-drm/nvidia-drm-connector.c
+NVIDIA_DRM_SOURCES += nvidia-drm/nvidia-drm-gem.c
+NVIDIA_DRM_SOURCES += nvidia-drm/nvidia-drm-fb.c
+NVIDIA_DRM_SOURCES += nvidia-drm/nvidia-drm-modeset.c
+NVIDIA_DRM_SOURCES += nvidia-drm/nvidia-drm-prime-fence.c
+NVIDIA_DRM_SOURCES += nvidia-drm/nvidia-drm-linux.c
+NVIDIA_DRM_SOURCES += nvidia-drm/nvidia-drm-helper.c
+NVIDIA_DRM_SOURCES += nvidia-drm/nv-pci-table.c
+NVIDIA_DRM_SOURCES += nvidia-drm/nvidia-drm-gem-nvkms-memory.c
+NVIDIA_DRM_SOURCES += nvidia-drm/nvidia-drm-gem-user-memory.c
+NVIDIA_DRM_SOURCES += nvidia-drm/nvidia-drm-gem-dma-buf.c
+NVIDIA_DRM_SOURCES += nvidia-drm/nvidia-drm-format.c
+
+NVIDIA_DRM_OBJECTS = $(patsubst %.c,%.o,$(NVIDIA_DRM_SOURCES))
+
+obj-m += nvidia-drm.o
+nvidia-drm-y := $(NVIDIA_DRM_OBJECTS)
+
+NVIDIA_DRM_KO = nvidia-drm/nvidia-drm.ko
+
+NV_KERNEL_MODULE_TARGETS += $(NVIDIA_DRM_KO)
+
+#
+# Define nvidia-drm.ko-specific CFLAGS.
+#
+
+NVIDIA_DRM_CFLAGS += -I$(src)/nvidia-drm
+NVIDIA_DRM_CFLAGS += -UDEBUG -U_DEBUG -DNDEBUG -DNV_BUILD_MODULE_INSTANCES=0
+
+$(call ASSIGN_PER_OBJ_CFLAGS, $(NVIDIA_DRM_OBJECTS), $(NVIDIA_DRM_CFLAGS))
+
+#
+# Register the conftests needed by nvidia-drm.ko
+#
+
+NV_OBJECTS_DEPEND_ON_CONFTEST += $(NVIDIA_DRM_OBJECTS)
+
+NV_CONFTEST_GENERIC_COMPILE_TESTS += drm_available
+NV_CONFTEST_GENERIC_COMPILE_TESTS += drm_atomic_available
+NV_CONFTEST_GENERIC_COMPILE_TESTS += is_export_symbol_gpl_refcount_inc
+NV_CONFTEST_GENERIC_COMPILE_TESTS += is_export_symbol_gpl_refcount_dec_and_test
+NV_CONFTEST_GENERIC_COMPILE_TESTS += drm_alpha_blending_available
+
+NV_CONFTEST_FUNCTION_COMPILE_TESTS += drm_dev_unref
+NV_CONFTEST_FUNCTION_COMPILE_TESTS += drm_reinit_primary_mode_group
+NV_CONFTEST_FUNCTION_COMPILE_TESTS += get_user_pages_remote
+NV_CONFTEST_FUNCTION_COMPILE_TESTS += get_user_pages
+NV_CONFTEST_FUNCTION_COMPILE_TESTS += pin_user_pages_remote
+NV_CONFTEST_FUNCTION_COMPILE_TESTS += pin_user_pages
+NV_CONFTEST_FUNCTION_COMPILE_TESTS += drm_gem_object_lookup
+NV_CONFTEST_FUNCTION_COMPILE_TESTS += drm_atomic_state_ref_counting
+NV_CONFTEST_FUNCTION_COMPILE_TESTS += drm_driver_has_gem_prime_res_obj
+NV_CONFTEST_FUNCTION_COMPILE_TESTS += drm_atomic_helper_connector_dpms
+NV_CONFTEST_FUNCTION_COMPILE_TESTS += drm_connector_funcs_have_mode_in_name
+NV_CONFTEST_FUNCTION_COMPILE_TESTS += vmf_insert_pfn
+NV_CONFTEST_FUNCTION_COMPILE_TESTS += drm_framebuffer_get
+NV_CONFTEST_FUNCTION_COMPILE_TESTS += drm_gem_object_get
+NV_CONFTEST_FUNCTION_COMPILE_TESTS += drm_dev_put
+NV_CONFTEST_FUNCTION_COMPILE_TESTS += drm_format_num_planes
+NV_CONFTEST_FUNCTION_COMPILE_TESTS += drm_connector_for_each_possible_encoder
+NV_CONFTEST_FUNCTION_COMPILE_TESTS += drm_rotation_available
+NV_CONFTEST_FUNCTION_COMPILE_TESTS += drm_vma_offset_exact_lookup_locked
+NV_CONFTEST_FUNCTION_COMPILE_TESTS += drm_gem_object_put_unlocked
+NV_CONFTEST_FUNCTION_COMPILE_TESTS += nvhost_dma_fence_unpack
+
+NV_CONFTEST_TYPE_COMPILE_TESTS += drm_bus_present
+NV_CONFTEST_TYPE_COMPILE_TESTS += drm_bus_has_bus_type
+NV_CONFTEST_TYPE_COMPILE_TESTS += drm_bus_has_get_irq
+NV_CONFTEST_TYPE_COMPILE_TESTS += drm_bus_has_get_name
+NV_CONFTEST_TYPE_COMPILE_TESTS += drm_driver_has_device_list
+NV_CONFTEST_TYPE_COMPILE_TESTS += drm_driver_has_legacy_dev_list
+NV_CONFTEST_TYPE_COMPILE_TESTS += drm_driver_has_set_busid
+NV_CONFTEST_TYPE_COMPILE_TESTS += drm_crtc_state_has_connectors_changed
+NV_CONFTEST_TYPE_COMPILE_TESTS += drm_init_function_args
+NV_CONFTEST_TYPE_COMPILE_TESTS += drm_helper_mode_fill_fb_struct
+NV_CONFTEST_TYPE_COMPILE_TESTS += drm_master_drop_has_from_release_arg
+NV_CONFTEST_TYPE_COMPILE_TESTS += drm_driver_unload_has_int_return_type
+NV_CONFTEST_TYPE_COMPILE_TESTS += vm_fault_has_address
+NV_CONFTEST_TYPE_COMPILE_TESTS += vm_ops_fault_removed_vma_arg
+NV_CONFTEST_TYPE_COMPILE_TESTS += drm_atomic_helper_crtc_destroy_state_has_crtc_arg
+NV_CONFTEST_TYPE_COMPILE_TESTS += drm_atomic_helper_plane_destroy_state_has_plane_arg
+NV_CONFTEST_TYPE_COMPILE_TESTS += drm_mode_object_find_has_file_priv_arg
+NV_CONFTEST_TYPE_COMPILE_TESTS += dma_buf_owner
+NV_CONFTEST_TYPE_COMPILE_TESTS += drm_connector_list_iter
+NV_CONFTEST_TYPE_COMPILE_TESTS += drm_atomic_helper_swap_state_has_stall_arg
+NV_CONFTEST_TYPE_COMPILE_TESTS += drm_driver_prime_flag_present
+NV_CONFTEST_TYPE_COMPILE_TESTS += vm_fault_t
+NV_CONFTEST_TYPE_COMPILE_TESTS += drm_gem_object_has_resv
+NV_CONFTEST_TYPE_COMPILE_TESTS += drm_crtc_state_has_async_flip
+NV_CONFTEST_TYPE_COMPILE_TESTS += drm_crtc_state_has_pageflip_flags
+NV_CONFTEST_TYPE_COMPILE_TESTS += drm_format_modifiers_present
+NV_CONFTEST_TYPE_COMPILE_TESTS += mm_has_mmap_lock
+NV_CONFTEST_TYPE_COMPILE_TESTS += drm_vma_node_is_allowed_has_tag_arg
+NV_CONFTEST_TYPE_COMPILE_TESTS += drm_vma_offset_node_has_readonly
+NV_CONFTEST_TYPE_COMPILE_TESTS += drm_display_mode_has_vrefresh
+NV_CONFTEST_TYPE_COMPILE_TESTS += drm_driver_master_set_has_int_return_type
+NV_CONFTEST_TYPE_COMPILE_TESTS += drm_driver_has_gem_free_object
+NV_CONFTEST_TYPE_COMPILE_TESTS += drm_prime_pages_to_sg_has_drm_device_arg
+NV_CONFTEST_TYPE_COMPILE_TESTS += drm_driver_has_gem_prime_callbacks
+NV_CONFTEST_TYPE_COMPILE_TESTS += drm_crtc_atomic_check_has_atomic_state_arg
+NV_CONFTEST_TYPE_COMPILE_TESTS += drm_gem_object_vmap_has_map_arg
+NV_CONFTEST_TYPE_COMPILE_TESTS += drm_plane_atomic_check_has_atomic_state_arg
+NV_CONFTEST_TYPE_COMPILE_TESTS += drm_device_has_pdev
+NV_CONFTEST_TYPE_COMPILE_TESTS += drm_crtc_state_has_no_vblank
+NV_CONFTEST_TYPE_COMPILE_TESTS += drm_mode_config_has_allow_fb_modifiers
+NV_CONFTEST_TYPE_COMPILE_TESTS += drm_has_hdr_output_metadata
+NV_CONFTEST_TYPE_COMPILE_TESTS += dma_resv_add_fence
+NV_CONFTEST_TYPE_COMPILE_TESTS += dma_resv_reserve_fences
+NV_CONFTEST_TYPE_COMPILE_TESTS += reservation_object_reserve_shared_has_num_fences_arg
+NV_CONFTEST_TYPE_COMPILE_TESTS += drm_connector_has_override_edid

NVIDIA-kernel-module-source-TempVersion/kernel-open/nvidia-drm/nvidia-drm.c

@@ -0,0 +1,59 @@
+/*
+ * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#include "nvidia-drm.h"
+
+#if defined(NV_DRM_AVAILABLE)
+
+#include "nvidia-drm-priv.h"
+#include "nvidia-drm-drv.h"
+
+static struct NvKmsKapiFunctionsTable nvKmsFuncsTable = {
+    .versionString = NV_VERSION_STRING,
+};
+
+const struct NvKmsKapiFunctionsTable* const nvKms = &nvKmsFuncsTable;
+
+#endif
+
+int nv_drm_init(void)
+{
+#if defined(NV_DRM_AVAILABLE)
+    if (!nvKmsKapiGetFunctionsTable(&nvKmsFuncsTable)) {
+        NV_DRM_LOG_ERR(
+            "Version mismatch: nvidia-modeset.ko(%s) nvidia-drm.ko(%s)",
+            nvKmsFuncsTable.versionString, NV_VERSION_STRING);
+        return -EINVAL;
+    }
+
+    return nv_drm_probe_devices();
+#else
+    return 0;
+#endif
+}
+
+void nv_drm_exit(void)
+{
+#if defined(NV_DRM_AVAILABLE)
+    nv_drm_remove_devices();
+#endif
+}

NVIDIA-kernel-module-source-TempVersion/kernel-open/nvidia-drm/nvidia-drm.h

@@ -0,0 +1,31 @@
+/*
+ * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef __NVIDIA_DRM_H__
+#define __NVIDIA_DRM_H__
+
+#include "nvidia-drm-conftest.h"
+
+int nv_drm_init(void);
+void nv_drm_exit(void);
+
+#endif /* __NVIDIA_DRM_H__ */